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2016-07-31util/inteltool: fix memory leakPatrick Georgi
A struct pci_dev was allocated but not freed. Change-Id: I6a8bbef6a118fc1f0aa7037e72c4d0dda9208f4b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1353037 Reviewed-on: https://review.coreboot.org/15971 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-31util/cbmem: Initialize variablePatrick Georgi
There can be cases where "found" wasn't initialized, do so. Change-Id: Ifef8d61daa70e27ec39b7a8f3481d2316dfaa36e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1347334 Reviewed-on: https://review.coreboot.org/15969 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-31nvramtool: Don't consider reserved regions to be "out of range"Patrick Georgi
Reserved regions showed different behavior for debug and regular builds. Debug output was unfriendly, regular was wrong. Print a proper error message and exit instead. Change-Id: I9842ff61f7d554800e2041e8c4c607f22b2df79f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1287076 Reviewed-on: https://review.coreboot.org/15968 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-31superiotool: Add Nuvoton NCT6791DOmar Pakker
This adds support for the Nuvoton NCT6791D Super I/O chip to the superiotool. The implementation is based on the Datasheet supplied by Nuvoton: Datasheet Version: January 8th, 2016 Revision 1.11 Datasheet deviation: - Defaults for control registers 0x20 and 0x21 are invalid. Datasheet: 0xc562. Actual: 0xc803. Change-Id: I8ced9738cd41960cbab7b5ea38ff19192d210672 Signed-off-by: Omar Pakker <omarpakker+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/15252 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-31Remove extra newlines from the end of all coreboot files.Martin Roth
This removes the newlines from all files found by the new int-015-final-newlines script. Change-Id: I65b6d5b403fe3fa30b7ac11958cc0f9880704ed7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15975 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-31buildgcc: Apply patches with -p1Nico Huber
Turned out that there are versions of the patch command that use the left hand side path for new files created by a patch. This behavior is incompatible with some of our patches. Stripping the topmost dir from the path with -p1 helps. While touching that line, I couldn't resist to drop a command substituion (the `echo $patch`). It really shouldn't be necessary as the path to the patch file is already expanded in the head of the for loop. Change-Id: I95398605db6dd54a8b08d8bc84c6602edbea6e10 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/15908 Reviewed-by: Idwer Vollering <vidwer@gmail.com> Tested-by: build bot (Jenkins)
2016-07-30util/chromeos: Make scripts executableStefan Reinauer
crosfirmware.sh and extract_blobs.sh are not executable, change that. Change-Id: Ib04df580a9acd4a422aedbdc15013b2ef505459a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/15922 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Omar Pakker Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-28viatool/quirks: Add newline to end of filePaul Menzel
Change-Id: If505021c6dd4bc1c98094dc6e4a3da1ea7753859 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/15916 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-07-28util: Correct typo in MSR_EBC_SOFT_POWERONElyes HAOUAS
Change-Id: Iba5fc92d8740d0bb7d41f8a83513ba7fb97be592 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15900 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-28util/msrtool: update register for Pentium4_laterElyes HAOUAS
Update MSR's registers regarding "Intel® 64 and IA-32 Architectures Software Developer’s Manual"- April 2015. "64-ia-32-architectures-software-developer-manual-325462.pdf" Change-Id: I71e399c4a6fef9de6a5581b64a6918660b2f8445 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15798 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2016-07-28msrtool/README: Remove trailing spacesElyes HAOUAS
Change-Id: I8b7d2263591608e0ab9504262bb06eac4cb52850 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15779 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-27Rename VB_SOURCE to VBOOT_SOURCE for increased clarityPaul Kocialkowski
This renames the VB_SOURCE variable to VBOOT_SOURCE in the build system, providing increased clarity about what it represents. Since the submodule itself is called "vboot", it makes sense to use that name in full instead of a very shortened (and confusing) version of it. Change-Id: Ib343b6642363665ec1205134832498a59b7c4a26 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/15824 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-21buildgcc: Never set GMP CFLAGS manually in order to get the right flagsPaul Kocialkowski
When no CFLAGS are explicitly provided to it, the GMP configure script will figure out the best optimization flags to use on its own. In particular, it will setup the march, mfpu and mtune flags based on hardware detection. However, when CFLAGS are provided, they are used as-is and such detection doesn't happen. When the march, mfpu and mtune flags are not provided (which happens when GMP wasn't built already), not only will related optimizations be disabled, but some code might not build because of missing support. This happens with NEON instructions on ARMv7 hosts. Thus, it is better not to set CFLAGS and leave it up to the GMP configure script to get them right and still reuse those later. Change-Id: I6ffcbac1298523d1b8ddf29a8bca1b00298828a7 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/15452 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-07-20cbmem: share additional time stamps IDsAntonello Dettori
Split the additional time stamps concerning depthcharge from the cbmem utility sourcecode and move them into commonlib/timestamp_serialized.h header. Change-Id: Ic23c3bc12eac246336b2ba7c7c39eb2673897d5a Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/15725 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-16buildgcc: Update the revision to 1.41Martin Roth
The binutils patch went in without updating the revision, so we need to update it now. This was done in commit bcfa7ccb (buildgcc: Update to binutils-2.26.1 & Fix aarch64 build issue) Change-Id: Ifad4a2e3973f1f60d0ea840945e2bd097e1b4474 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15712 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-14buildgcc: Update to binutils-2.26.1 & Fix aarch64 build issueMartin Roth
- Update to the latest version of GNU binutils - Add a patch to undo the changes to binutils done by commit c1baaddf so that arm-trusted-firmware builds correctly again. Test: Build arm-trusted-firmware (ATF) with this patch. Build ATF with binutils 2.26.1 changing the '.align x,0' to '.align x', which changes the padding bytes to NOP instructions. Verify that everything except the padding bytes is the same. See https://sourceware.org/bugzilla/show_bug.cgi?id=20364 for more information about this issue. Change-Id: I559c863c307b4146f8be8ab44b15c9c606555544 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15711 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-14util/riscvtools: Provide a tohost/fromhost symbols so Spike doesn't hangJonathan Neuschäfer
See https://github.com/riscv/riscv-isa-sim/issues/54 for more information. Change-Id: I8cda8dc07866d395eb3ce5d94df8232840fa8b82 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15288 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-07-12kconfig: add olddefconfig target to helpMartin Roth
olddefconfig is used to expand the miniconfig files with all the default values removed by the 'savedefconfig' target. Change-Id: Ic9c62f4c334919e8be478d30099819b90891670a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15319 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-05buildgcc: Add option to bootstrap a host gccNico Huber
Bootstrapping gcc is the recommended way if your host gcc's version doesn't match the gcc version you're going to build. While a build with an outdated host gcc usually succeeds, an outdated gnat seems to be a bigger issue. v3: Some library controversy: gcc likes the libraries it ships with most but we don't want to install shared libraries. So we build them static --disable-shared) and install only the minimum (libgcc, libada, libstdc++). However, as the code of these libraries might be used to build a shared library we have to compile them with `-fPIC`. v4: o Updated getopt strings. o The workaround for clang (-fbracket-depth=1024) isn't needed for bootstrapping and also breaks the build, as clang is only used for the first stage in that case and gcc doesn't know that option. So far build tested with `make BUILDGCC_OPTIONS="-b -l c,ada"` on o Ubuntu 14.04 "Trusty Tahr" (i386) o Debian 8 "Jessie" (x86_64) (building python (-S) works too) o current Arch Linux (x86_64) o FreeBSD 10.3 (x86_64) (with gcc-aux package) and with clang host compiler, thus C only: `make BUILDGCC_OPTIONS="-b"` on o Debian 8 "Jessie" (x86_64) o FreeBSD 10.3 (x86_64) v5: Rebased after toolchain updates to GCC 5.3.0 etc. Build tested with `make BUILDGCC_OPTIONS="-b -l c,ada"` on o Debian 8 "Jessie" (x86_64) Change-Id: Icb47d3e9dbafc55737fbc3ce62a084fb9d5f359a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/13473 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-05buildgcc: Make package build() function more versatileNico Huber
Refactor build() to make things more flexible: Add a parameter that tells if we build a package for the host or for a target architecture. This is just passed to the build_$package() function and can be used later to take different steps in each case (e.g. for bootstrapping a host gcc). Move .success files into the destination directory. That way we can tell that a package has been built even if the package build directory has been removed. Change-Id: I52a7245714a040d11f6e1ac8bdbff8057bb7f0a1 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/13471 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-04fmaptool: Accept hex values with uppercase lettersPatrick Georgi
Due to a newer flex version with which the scanner was recreated, we also have to make the compiler less strict on the generated code. Change-Id: I3758c0dcb2f5661d072b54a30d6a4ebe094854e6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/15482 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-02cbfstool: Require "-m ARCH" to extract payloads and stagesAntonello Dettori
Require the user to specify which architecture the payload/stage was built for before extracting it. Change-Id: I8ffe90a6af24e76739fd25456383a566edb0da7e Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/15438 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-01util/kconfig: Fix gconfig buildJonathan Neuschäfer
This linker error was the problem: build/util/kconfig/zconf.tab.o: In function `conf_read_simple': /home/jn/dev/coreboot/util/kconfig/confdata.c:413: undefined reference to `kconfig_warnings' /home/jn/dev/coreboot/util/kconfig/confdata.c:413: undefined reference to `kconfig_warnings' build/util/kconfig/zconf.tab.o: In function `sym_calc_value': /home/jn/dev/coreboot/util/kconfig/symbol.c:388: undefined reference to `kconfig_warnings' /home/jn/dev/coreboot/util/kconfig/symbol.c:388: undefined reference to `kconfig_warnings' collect2: error: ld returned 1 exit status /home/jn/dev/coreboot/util/kconfig/Makefile:339: recipe for target 'build/util/kconfig/gconf' failed make: *** [build/util/kconfig/gconf] Error 1 Change-Id: I4a667c7c15b35618fb9ad536f2be5044b8031ab4 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15505 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-06-29rebase.sh: Update to current cros branchMartin Roth
Change-Id: I04add4e6fc957cb9a0cdefe79ec9e97e3cebdf8e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15322 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-06-26ifwitool: Fix gcc error due to shadowed global declarationWerner Zeh
The name 'bpdt_size' is used for a function as well as ia local variable. As ifwitool is compiled using HOSTCC, there can be an older gcc version used for the compilation. With gcc version 4.4.7 I get the following error: declaration of 'bpdt_size' shadows a global declaration To fix it, rename the function to get_bpdt_size so that names are unique now. Change-Id: I47791c705ac4ab28307c52b86940a7a14a5cfef8 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15343 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24src/commonlib/lz4_wrapper: Correct inline asm for unaligned 64-bit copyBenjamin Barenblat
Rewrite inline assembly for ARMv7+ to correctly annotate inputs and outputs. On ARM GCC 6.1.1, this causes assembly output to change from the incorrect @ r0 is allocated to hold dst and x0 @ r1 is allocated to hold src and x1 ldr r0, [r1] @ clobbers dst! ldr r1, [r1, #4] str r0, [r0] str r1, [r0, #4] to the correct @ r0 is allocated to hold dst @ r1 is allocated to hold src and x1 @ r3 is allocated to hold x0 ldr r3, [r1] ldr r1, [r1, #4] str r3, [r0] str r1, [r0, #4] Also modify checkpatch.pl to ignore spaces before opening brackets when used in inline assembly. Change-Id: I255995f5e0a7b1a95375258755a93972c51d79b8 Signed-off-by: Benjamin Barenblat <bbaren@google.com> Reviewed-on: https://review.coreboot.org/15216 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-21cbfstool: Change CONFIG_FMD_GENPARSER if not set to nAlexander Couzens
When doing make in util/cbfstool it contaminates the tree because it generates the fmd_parser. Change-Id: Ida855d1e57560c76d3fcfcc8e2f7f75bcdfdd5d4 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/15221 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-06-21fmaptool: Make base offsets absolute in fmap_config.hJulius Werner
fmaptool generates a header file used to hardcode certain values from the FMAP in coreboot's binaries, to avoid having to find and parse the FMAP manually for every access. For the offset of the FMAP itself this has already been using the absolute offset from the base of the whole ROM, but for individual CBFS sections it only used the offset from the immediate parent FMAP region. Since the code using it intentionally has no knowledge of the whole section tree, this causes problems as soon as the CBFS is a child section of something not at absolute offset 0 (as is the case for most x86 Chromebooks). Change-Id: If0c516083949fe5ac8cdae85e00a4461dcbdf853 Reported-by: Rolf Evers-Fischer <embedded24@evers-fischer.de> Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15273 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-21util/riscvtools: Add script that turns coreboot.rom into an ELFJonathan Neuschäfer
This is required because SPIKE doesn't support loading flat files yet. Change-Id: If745d78712ca8108b5dcc21591201bc2d3f70b86 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/14964 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-17cbfstool: Extract payload in ELFAntonello Dettori
Implement function that automatically converts a SELF payload, extracted from the CBFS, into an ELF file. The code has been tested on the following payloads: Working: GRUB, FILO, SeaBIOS, nvramcui, coreinfo and tint Currently not working: none Change-Id: I51599e65419bfa4ada8fe24b119acb20c9936227 Signed-off-by: Antonello Dettori <dettori.an@gmail.com> Reviewed-on: https://review.coreboot.org/15139 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-17elfwriter: Fix multi-phdrs ELFs parsingAntonello Dettori
Allow to write multiple phdrs, one for each non-consecutive section of the ELF. Previously it only worked for ELFs contaning a single program header. Change-Id: If6f95e999373a0cab4414b811e8ced4c93c67c30 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/15215 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-16ifwitool: Calculate checksum for subpart_dirFurquan Shaikh
Checksum is calculated by using 2s complement method. 8-bit sum of the entire subpart directory from first byte of header to last byte of last partition directory entry. BUG=chrome-os-partner:53508 Change-Id: I991d79dfdb5331ab732bf0d71cf8223d63426fa8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15200 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-15ifwitool: Fix calculation of dst_sizeRolf Evers-Fischer
Change-Id: I07523252eacffb323e2bb54c306f5e9ac83e4cbd Signed-off-by: Rolf Evers-Fischer <embedded24@evers-fischer.de> Reviewed-on: https://review.coreboot.org/15162 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-12ifwitool: Do not calculate checksum for subpart_dirFurquan Shaikh
1. The checksum method that was documented is not correct. So, no use filling in a value based on wrong calculations. This can be added back once updated information is available. 2. Checksum does not seem to affect the booting up of SoC. So, fill in 0 for now. Change-Id: I0e49ac8e0e04abb6d7c9be70323612bdef309975 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15145 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-12ifwitool: Correct pack order and header orderFurquan Shaikh
Update pack and header order and mark the entries as mandatory and recommended w.r.t. ordering (mandatory = essential for booting, recommended = okay to change, but this config is tested and known to work). Change-Id: Ia089bdaa0703de830bb9553130caf91a3665d2c4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15144 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-12autoport: Add prompt for enabling unsafe inteltool glx optionChris Ching
Change-Id: Ib674ab7ca8b6464de553a86536b1762fda98d94e Signed-off-by: Chris Ching <chingcodes@google.com> Reviewed-on: https://review.coreboot.org/14901 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-09util/checklist: Add bootblock supportLee Leahy
Scan the boot block when building it with C_ENVIRONMENT_BOOTBLOCK selected. TEST=Build and run with Galileo Gen2 Change-Id: I922f761c31e95efde0975d8572c47084b91b2879 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15130 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-08inteltool: handle unsafe dumping of graphics registersStefan Tauner
The current implementation from Vladimir simply dumps 1 MB of memory contents starting at the base address of the second PCI device (which most likely is the VGA controller on Intel systems). This locks up a number of different systems, e.g. my Ibex Peak-based T410s. This patch documents the issue and stops dumping the graphics registers for the -a/--all parameter. Change-Id: I581bdc63db60afaf4792bc11fbeed73aab57f63a Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/14627 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-06-08cbfstool: Allow to easily build the individual toolsAntonello Dettori
Adds a label for each tool included in the cbfstool package in order to build them more easily through Make. Change-Id: Id1e5164240cd12d22cba18d7cc4571fbadad38af Signed-off-by: Antonello Dettori <dettori.an@gmail.com> Reviewed-on: https://review.coreboot.org/15075 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-04intelmetool: Add the X99 ISA Bridge device idOmar Pakker
This adds the ISA bridge device id for the Intel C160/X99 series chipset to the intelmetool. Change-Id: I2e7db0fe1692985ebb167b9a44ab412a45a9f3bd Signed-off-by: Omar Pakker <omarpakker+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/15053 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-03Add Board Checklist SupportLee Leahy
Build the <board>_checklist.html file which contains a checklist table for each stage of coreboot. This processing builds a set of implemented (done) routines which are marked green in the table. The remaining required routines (work-to-do) are marked red in the table and the optional routines are marked yellow in the table. The table heading for each stage contains a completion percentage in terms of count of routines (done .vs. required). Add some Kconfig values: * CREATE_BOARD_CHECKLIST - When selected creates the checklist file * MAKE_CHECKLIST_PUBLIC - Copies the checklist file into the Documenation directory * CHECKLIST_DATA_FILE_LOCATION - Location of the checklist data files: * <stage>_complete.dat - Lists all of the weak routines * <stage>_optional.dat - Lists weak routines which may be optionally implemented TEST=Build with Galileo Gen2. Change-Id: Ie056f8bb6d45ff7f3bc6390b5630b5063f54c527 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15011 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-01ifwitool: Fix syntax issues with ifwitoolFurquan Shaikh
Change-Id: Ie7a12a39116ee08f5e24c81c97695201169a63f7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15022 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-30ifwitool: Add new tool for managing IFWI imagesFurquan Shaikh
- Supports following operations: 1. add raw/dir sub-partition 2. extract raw/dir sub-partition 3. print info 4. delete raw sub-partition 5. replace raw/dir sub-partition Change-Id: I683a0ab13cc50eb60eecca34db4a8ffefc8dccbd Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14896 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-28util/cbfstool: Include commonlib/helpers.h in common.hFurquan Shaikh
This avoids re-declaring common macros like ARRAY_SIZE, MIN, MAX and ALIGN. Also removes the issues around including both files in any tool. Also, fix comparison error in various files by replacing int with size_t. Change-Id: I06c763e5dd1bec97e8335499468bbdb016eb28e5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14978 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-26cbfstool: Move cbfs_file_get_header to fit.cFurquan Shaikh
Since fit.c is the only caller of this function move it out of common.c and into fit.c. Change-Id: I64cc31a6d89ee425c5b07745ea5ca9437e2f3fcf Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14949 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-26superiotool: Add support for chip NCT6102D / NCT6106DRoberto Muñoz Gómez
Add support for chip NCT6102D / NCT6106D in superiotool Change-Id: I689ff8e796f43a5aac144e9898df750407588b1f Signed-off-by: Roberto Muñoz Gómez <munoz.roberto@gmail.com> Reviewed-on: https://review.coreboot.org/14206 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2016-05-18util/cbfstool: allow option to honor FSP modules' linked addressAaron Durbin
If '-b' isn't passed when adding an FSP file type to CBFS allow the currently linked address to be used. i.e. don't relocate the FSP module and just add it to CBFS. Change-Id: I61fefd962ca9cf8aff7a4ca2bea52341ab41d67b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14839 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-18board_status: Abort early if the coreboot image doesn't existJonathan Neuschäfer
Change-Id: I274c990e69634ebcb9dd77470cbf1515281de312 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/14683 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-16sconfig: Add a new generic device typeDuncan Laurie
Add support for a basic generic device in the devicetree to bind to a device that does not have a specific bus, but may need to be described in tables for the operating system. For instance some chips may have various GPIO connections that need described but do not fall under any other device. In order to support this export the basic 'scan_static_bus()' that can be used in a device_operations->scan_bus() method to scan for the generic devices. It has been possible to get a semi-generic device by using a fake PNP device, but that isn't really appropriate for many devices. Also Re-generate the shipped files for sconfig. Use flex 2.6.0 to avoid everything being rewritten. Clean up the local paths that leak into the generated configs. Change-Id: If45a5b18825bdb2cf1e4ba4297ee426cbd1678e3 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14789 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-05-16sconfig: Add 10bit addressing mode to i2c device typeDuncan Laurie
Use the second token for an i2c device entry in devicetree.cb to indicate if it should use 10-bit addressing or 7-bit. The default if not provided is to use 7-bit addressing, but it can be changed to 10-bit addressing with the ".1" suffix. For example: chip drivers/i2c/generic device i2c 3a.1 on end end Change-Id: I1d81a7e154fbc040def4d99ad07966fac242a472 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14788 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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