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2019-01-07crossgcc: Update Python to version 3.7.2Elyes HAOUAS
Change-Id: Ie0b3d31ba116314308d4fcc36a19587370fff7cc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30560 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-06util/ifdtool: Fix regions_collide() checkNico Huber
The old version was unnecessarily complex and allowed one region to include the other. Change-Id: Ibf7faf8103c8945b82c3962b5a7b82c3288b871f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/30673 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-05crossgcc: Update CMake to version 3.13.2Elyes HAOUAS
Change-Id: Ifd9e82d564e4e49194ac48786fd233cbf97a55c5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-05crossgcc: Update GDB to version 8.2.1Elyes HAOUAS
Change-Id: I454843dcabe7e3fa4b13dd58ce81ba9f25b5a432 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-05crossgcc: Update LLVM to 7.0.1Elyes HAOUAS
Change-Id: I7d88f0c36a254d8b2e3e76f632f46f0d2a4ad6f8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-05util/inteltool: fix PCR init of Sunrise Point-LP devicesShaleen Jain
Fixes getting a dump of GPIO registers for these devices. Change-Id: I80f05a170152969ba45d6aee33ab7ed5296ee496 Signed-off-by: Shaleen Jain <shaleen@jain.sh> Reviewed-on: https://review.coreboot.org/c/30604 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04crossgcc: Update acpica and Expat versionsElyes HAOUAS
Update: * acpica to version 20181213 changes in this version: https://acpica.org/node/163 * Expat to version 2.2.6 changes in this version: https://github.com/libexpat/libexpat/blob/R_2_2_6/expat/Changes Change-Id: Ib67cf26497a0c2c2a364741675b13e4ce0190e41 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-04util/superiotool: Add ITE IT8786E-IKyösti Mälkki
Based on IT8786E-I V0.4.1 datasheet with following remark: "Please note that the IT8786E-I V0.4.1 is applicable only to the D version." Signed-off-by: Kyösti Mälkki <kyosti.malkki@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ibf6e290abb01ae1b6b28173a83e88d1d99663ad4 Reviewed-on: https://review.coreboot.org/c/30334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-04util/autoport/readme.md: Correct minor inconsistencyAngel Pons
Commit a5072af67d85 ("util/autoport: Use romstage.c instead of early_southbridge.c") changed where the SPD map is. Reflect that. Change-Id: Id0bd1778617371bac5921c4eae63d0beb088216c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/30655 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04util/gitconfig/pre-commit: Use clang-format to sanitise commitsEdward O'Callaghan
Use the `git-format' tool to sanitise coreboot commits such that they conform to coreboot's coding style. This fancy piece of machinary allows one to have LibFormat from Clang to automatically check your commit conforms to coreboot's coding style, fix any issues automatically and provides you a diff you may review and apply at your convenience. N.B. When the `clang-format' binary is not found we issue a warning that the test was skipped and carry on as usual. Hence, this is strictly non-enforcing at this current time. You may use it at your leisure. Change-Id: If49017ea82f0707efd47cae5978a286a9af8f3b7 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: https://review.coreboot.org/c/8037 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04crossgcc: Update acpica to 20180927Stefan Reinauer
Update to latest version of iasl: (From the acpica.org changelogs) * Fixed a regression introduced in version 20180927 that could cause the compiler to fault, especially with NamePaths containing one or more carats (^). Such as: ^^_SB_PCI0 * Added a new remark for the Sleep() operator when the sleep time operand is larger than one second. This is a very long time for the ASL/BIOS code and may not be what was intended by the ASL writer. * Implemented detection of extraneous/redundant uses of the Offset() operator within a Field Unit list. A remark is now issued for these. For example, the first two of the Offset() operators below are extraneous. Because both the compiler and the interpreter track the offsets automatically, these Offsets simply refer to the current offset and are unnecessary. Note, when optimization is enabled, the iASL compiler will in fact remove the redundant Offset operators and will not emit any AML code for them. Change-Id: I46a1b1be44328aa2172f4741e9fd0c9b0f4e0430 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/28944 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04crossgcc: Update software versionsStefan Reinauer
Update toolchain to the following software versions: o Python 3.5.1 -> 3.7.0 o LLVM 6.0.0 -> 7.0.0 o Expat 2.2.1 -> 2.2.5 o MPC 1.0.3 -> 1.1.0 o MPFR 3.1.5 -> 4.0.1 Change-Id: I66c6138c7b65c73a89b3cf980bb08950d8fffe6a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/28887 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-03util/chromeos/crosfirmware.sh: Print more messagesTristan Corrick
The existing code has several messages that are only printed when the DEBUG variable is set. These messages are not verbose, and are quite useful to see how the script is progressing. So, print them unconditionally. Change-Id: I8f78e4563f0b4a42f831194a6e526284c2fbcd92 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-03util/chromeos/crosfirmware.sh: Check for dependenciesTristan Corrick
crosfirmware.sh has dependencies that might not be installed on some systems. If a dependency is missing, provide a clear message about the issue and how to resolve it. Change-Id: I265bd03666f1273d3c22b60aae860c48c758005b Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30549 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-03util/chromeos/crosfirmware.sh: Print download statusTristan Corrick
It's quite useful to know the download progress, as it can take a while even with a fast connection. For example, the peppy recovery image is ~600 MiB. It also lets the user know that disk space is being filled. Change-Id: I8c175f9095478ffe33c95b7ef9907c25b5f10f8c Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30548 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-03util/chromeos/crosfirmware.sh: Add /sbin to PATHTristan Corrick
On some systems, such as Debian 9.6, `parted` and `debugfs` are located in /sbin. Adding /sbin to PATH means that this script can work when run as a regular user. Change-Id: I151dba467e2b196f13093334273dae8a05865491 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-28util/xcompile/xcompile: Use tab for indentElyes HAOUAS
Change-Id: I9878e6d962004003e2c05a6cdb8ecb0a3a02ae66 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-28util/inteltool: Add support for Sunrise Point LPMatthew Garrett
Used documents: 334658 (Sunrise Point-LP I/O datasheet vol. 1) 334659 (Sunrise Point-LP I/O datasheet vol. 2) 332690 (Sunrise Point I/O datasheet vol. 1) Change-Id: I16237ffc9a225b46271f2a51d77a7f28dfc36138 Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/28623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-24util/cbfstool/cbfstool.c: Fix typoFrans Hendriks
Fix typo of 'top-aligned' BUG=N/A TEST=Intel CherryHill CRB Change-Id: I6dc2f150d8ec245070257384b406a570498400b2 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/30337 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-21util/release: Don't assume the source is in a directory called corebootPatrick Georgi
Change-Id: I384ff2f01b38916851522411d0c25c49793fe480 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-21util/release: Use "gpg", not "gpg2" for creating signaturesPatrick Georgi
It's the common name. Change-Id: Iafa793b961847b2c98282fd035ea96ddf6109012 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-12-21util/release/genrelnotes: Don't assume we're on origin/masterPatrick Georgi
A release may be done from an older commit. It's also not a problem as commits are stored in the reflog (unlike local changes that the script guards properly). Change-Id: I26f1c16c1cdfc9e77e28528b3327ce30c5b82b19 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-12-21util/release: Test for rename(1) in genrelnotesPatrick Georgi
It's a separate package on debian, so it may not be installed with perl. Change-Id: Id82661e1d7e6a025f5b207e3bd61669abc32d328 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-12-21util/release: Also keep 3rdparty/fsp in the blobs tarballPatrick Georgi
Change-Id: I089519f685377ae02155817bb042f83d79d1af6c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-12-20util/xcompile/xcompile: Enable x86_64 supportPatrick Rudolph
Similar to i686 on x86_32, compile for nocona on x86_64. Nocona is the first Pentium 4 CPU that has long mode support. Required for 64bit support. Change-Id: Ied28f98f89610a748be8d66cf35814e9112a4407 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/29877 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-19zoombini: remove support for deprecated zoombini boardBob Moragues
Change-Id: Iab2737940f07afb4f5a29ff50e6cb2a22027c51b Signed-off-by: Bob Moragues <moragues@chromium.org> Reviewed-on: https://review.coreboot.org/c/30094 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-19util/crossgcc/buildgcc: Remove quotation marks around hashesJonathan Neuschäfer
They were not originally printed, and serve no good purpose, so let's remove them again. Change-Id: I4e00477f2e143f93fd27ba6a083977a667a3eb48 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/28829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-19utils: introduce find_usbdebug.sh to help find USB debug portsStefan Tauner
Carl-Daniel made this script a long time ago but it never was picked up in the tree. Now that USB debugging is way more common it makes sense to include it. I have made a number of changes to the original version: * -h help text * check for running as root * enhanced readability (test -> if) * new execution flow and refined output that better shows the device(s) attached to the debug port(s) * handling of Intel rate-matching hubs * hiding of (bogus) error messages from lspci and lsusb Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Change-Id: Iadf775e990f5c5f91a28d57e3331d1f59acee305 Reviewed-on: https://review.coreboot.org/c/9305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-19util/cbfstool/cbfs-mkstage: Support x86_64Patrick Rudolph
Add support for relocations on x86_64. Required for 64bit romstage. Change-Id: I1ff223d3476776297b501813a953356dd6fa9d67 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/30115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-12-19util/cbfstool: Support AMD64 rmodulesPatrick Rudolph
Add support for 64bit rmodule, as required for relocatable ramstage on x86_64. Change-Id: I7fbb3b4c0f76ce82c090b5f16f67a728b6bf94a5 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/29874 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-18util/lint/spelling.txt: Protect "acknowledgement" entryJonathan Neuschäfer
In commit eceba31c7f ("util/lint: Set "acknowledgement" correct"), the word "acknowledgement" was removed from util/lint/spelling.txt. A more robust solution is to comment it out, as done for "sepc" in commit afa5ec8d5f ("util/lint: Update spelling.txt to latest linux version"). Change-Id: Ia976dedc9b31190d22e7b946f14709d5c4577f71 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/30167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-18util/util_readme: Don't recommend running this script with "sh"Jonathan Neuschäfer
util/util_readme/util_readme.sh is specifically a bash script and requires bash-specific features such as "[[". It doesn't work when run with a "sh" shell that only implements POSIX features, such as dash. Thus, tell the user to run the script directly, in which case the #! line is used. Change-Id: I5706ffe857c5a148e9776571a377ad8647f9a4c2 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/30162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-18util/bucts: Add a description.md fileJonathan Neuschäfer
Change-Id: I367703ffcd8d10dec0c67b61c9ebbefd497424fd Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/30161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-18util/board_status.sh: Fix command for fetching the kernel logArthur Heymans
94b761c8e (util/board_status: run dmesg with sudo) attempted to fetch the console as root locally but instead sudo was put in front of the remote path which runs as root anyways. Also unless quotation marks are used the cmd function will see 'sudo' and 'dmesg' as separate aruguments. Change-Id: Ib9e9e4b443f4e3ad04c5fda2c2ce626255a190f2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-05util/scripts/maintainers.go: file: queries are more stable with quotesPatrick Georgi
The gerrit docs aren't very explicit about it, but file:"^foo$" is more robust than file:^foo$. Change-Id: I16c7d972d365cd04ca5fbb78012ad4eaad667be6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/29781 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03cbmem: Enable AArch64 supportAdam Kallai
TEST=on Chromebook Kevin with 64bit userland, it works well. Change-Id: If16065000214c6cff9c14a14c5b5f44faca38153 Signed-off-by: Adam Kallai <kadam@inf.u-szeged.hu> Reviewed-on: https://review.coreboot.org/c/29978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-30arch/power8: Rename to ppc64Jonathan Neuschäfer
POWER8 is a specific implementation of ppc64, which is by now outdated (POWER9 has been on the market for a while). Rename arch/power8/ to potentially cover a wider range of hardware. TEST=Toolchains built before/after this commit can build coreboot for emulation/qemu-power8 from before/after this commit. Change-Id: I2d6f08b12a9ffc8a652ddcd6f24ad85ecb33ca52 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/29943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
2018-11-30broadcom: Remove SoC and board supportPhilipp Deppenwiese
The reason for this code cleanup is the legacy Google Purin board which isn't available anymore and AFAIK never made it into the stores. * Remove broadcom cygnus SoC support * Remove /util/broadcom tool * Remove Google Purin mainboard * Remove MAINTAINERS entries Change-Id: I148dd7eb0192d396cb69bc26c4062f88a764771a Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/29905 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-29util/inteltool: Add Apollo Lake LPC ID and allow to read PCRsNico Huber
The P2SB (PCI to Side-Band) bridge is on a different PCI device on APL. Hence, we have to decide based on the LPC ID which device to query. Also fix a comment. Change-Id: Ie20d7d2d246629d085bcf4740ba28b1e81e6a12a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/29896 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-28mb/*/*/Kconfig: Remove useless commentElyes HAOUAS
Change-Id: Ibdff50761a205d936b0ebe067f418be0a2051798 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hellsenberg <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: David Guckian Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-28romcc: Increase buffer size to fit max string sizeMartin Roth
On the updated builder image, the build is failing because the system compiler has been updated to GCC 8.2.0. It complains about the possibility of overflow when putting one 30 character buffer plus 2 characters into another 30 character buffer. To fix this, increase the recipient buffer size by 2. romcc.c:3645:2: note: 'sprintf' output between 3 and 32 bytes into a destination of size 30 [-Werror=format-overflow=] sprintf(buf, "\"%s\"", scratch); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ romcc.c:3649:2: note: 'sprintf' output between 3 and 32 bytes into a destination of size 30 [-Werror=format-overflow=] sprintf(buf, "\"%s\"", scratch); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Change-Id: I7879a7202cc3ff52301b10118fc49fcc601f133e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/29850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-11-27cbmem: Fix remaining mapped memory accesses to use aligned_memcpy()Julius Werner
aligned_memcpy() was introduced to fix issues with platforms that don't allow unaligned accesses to areas mapped with /dev/mem, but we missed a few spots. Fix them. Change-Id: I97ea953455b41a50023ceaca7eb148d60e6b8097 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/29848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-11-26util/crossgcc: Document how to build the toolchain for another locationPatrick Georgi
One common issue with the toolchain is that it takes a very long time to build while it's somewhat volatile inside the coreboot tree. Installing the toolchain elsewhere helps keep it safe but since there is no reliable default location outside the tree, keep the default as is. Change-Id: Ic414cddfd3c7097412f3f2c3c7ec7b7191fa32de Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/29826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-11-24util/scripts/maintainers.go: drop special case for "THE REST"Patrick Georgi
It's not useful anymore. Change-Id: Iba7f10dc87301911ff5f73c182b41c268fba310a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/29658 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-23mb: Set coreboot as DSDT's manufacturer model IDElyes HAOUAS
Field 'OEMID' & "OEM Table ID" are related to DSDT table not to mainboard. So use macro to set them respectvely to "COREv4" and "COREBOOT". Change-Id: I060e07a730e721df4a86128ee89bfe168c69f31e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Guckian
2018-11-23util/cbfstool: Fix GCC error due to a shadowed declarationWerner Zeh
There is already a function with the name buffer_size(). Adding a local variable with the same name will lead to the following error on older GCC versions (e.g. version 4.4.7): declaration of 'buffer_size' shadows a global declaration To fix this rename the local variable to buffer_len. Change-Id: Ifae3a17152f2f9852d29a4ac038f7e5a75a41614 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/29776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2018-11-22util/cbfstool/rmodule.{c,h}: Fix typo and correct headerFrans Hendriks
Header contains ':' in copyright line. rmdoule is a typo Remove the ';' and correct typo to rmodule. BUG=N/A TEST=N/A Change-Id: I05b1fb80a81682646c9fba3d234de235b6bc9e8c Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2018-11-22riscv: fix bug of sifive-gpt.pyXiang Wang
The GPT version must be "00 00 01 00" and the little endian should be represented as 0x10000. Please refer to: https://en.wikipedia.org/wiki/GUID_Partition_Table Change-Id: Ib025197fc96f32823e687a89de0cee51c952b031 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/c/29767 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-21util/ifdtool: Add IceLake platform support under IFDv2Aamir Bohra
Change-Id: Ib69a2cbc3d8ab9f35c940e95b0edb4b04b50b716 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1162995 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/c/29696 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-21ACPI: Fix DSDT's revision fieldElyes HAOUAS
DSDT revision is =1 for ACPI v1 and =2 for greater ACPI version. This will cause the AML interpreter to use 32-bit integers and math if the version is 1, and 64-bit if the version is >=2. Current spec version is 2 for ACPI 6.2-a. Change-Id: I77372882d5c77b7ed52dcdd88028403df6f6fa7f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29626 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 10:58:04 +0000