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2008-06-21flashrom: Increase delay in probe_jedec() to 2ms to reliably detect AT29C020Peter Stuge
Run time is increased a few 100ms but this is needed for reliability. I consider this trivial. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3373 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-20flashrom: Show expected and read byte on verify failure. Trivial.Peter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3372 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-18flashrom: Add support for AMIC Technology A49LF040A and do not probe ↵Jens Kuehnel
W29EE011 anymore Jens sent the first patch that added A49LF040A to flash.h and flashchips.c using _jedec and _49lf040 functions. An issue was found with probe_w29ee011() for the Winbond W29EE011, which caused the A49LF040A to no longer respond to any commands. Ward made a patch to disable probing by default for the W29EE011 following some discussion. Using -c W29EE011 will make flashrom probe for the chip. Peter did some more datasheet diving and found that the Pm49FL00x functions suited this chip quite well because of the block locking registers in A49LF040A, and finally tested PROBE READ ERASE WRITE to work on ALIX.3c3. Ward confirmed that this works on alix.2c3 too. Signed-off-by: Jens Kuehnel <coreboot@jens.kuehnel.org> Signed-off-by: Ward Vandewege <ward@gnu.org> Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3368 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-18flashrom: Force read unknown flash chipsPeter Stuge
When flash chip detection fails, it is still useful and possible to read the flash chip contents. If no flash chip is found in normal probes and the -f -r -c CHIPNAME options are given, a successful probe for the specified chip is forced, and then flashrom reads the flash chip using either the read function for the specified chip, or if there is none, a simple memcpy(). The patch also moves the global variable int force in flashrom.c into main() and passes it as a parameter to layout.c:show_id(), which was the only other function that used the variable. This is needed to avoid confusion with the new parameter int force which is added to flashrom.c:probe_flash() and used to force probe success for the chip named in char *chip_to_probe. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3367 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-13flashrom: Board enable and autodetection for GIGABYTE GA-7VT600Peter Stuge
Uses the VT8237 ISA bridge with mainboard subsystem ID and Realtek 8139 with mainboard subsystem ID for board detection. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Lyos Gemini Norezel <lyos.gemininorezel@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3366 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-11flashrom: Add support for Amic Technology A29040B flash chip.Peter Stuge
PROBE READ tested by Lyos Gemini Norezel on BioStar P4M80-M4. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Lyos Gemini Norezel <lyos.gemininorezel@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3365 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-11flashrom: Board enable and autodetection for BioStar P4M80-M4.Peter Stuge
Thanks to Reinder for clean room reverse engineering and data sheet diving! This board is autodetected because there are some good BioStar subsystem IDs. Matching uses onboard VT6420 SATA RAID with subsystem BioStar 3206 and onboard UniChrome Pro IGP graphics with subsystem BioStar 1202. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Lyos Gemini Norezel <lyos.gemininorezel@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3364 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-08Changes Makefile generation so that recursive "make" calls readPierre Pronchery
"$(MAKE)" instead, as GNU make (or "gmake") is currently necessary to build. Signed-off-by: Pierre Pronchery <khorben@defora.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3363 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-07Add dump support for Winbond (NSC) PC87427. Dumps available from real hardware.Tom Sylla
Signed-off-by: Tom Sylla <tsylla@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3361 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-03Ward writes:Peter Stuge
SST SST49LF160C is confirmed to work for PROBE READ ERASE WRITE, at least on 2 MCP55-based boards (gigabyte m57sli v1 and supermicro h8dmr). On the m57sli board, it only works > 512K when booted into coreboot; the proprietary bios seems to do something weird where it locks rom access down to the first 512K of the chip. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-28abuild: fix gnu getopt detection (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3359 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-27Revert r3357 and fix it as intended to (forgotten header commit instead of typo)Mart Raudsepp
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3358 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-27Fix typo introduced in r3356 that breaks build (trivial).Mart Raudsepp
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3357 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-27flashrom: MX25L4005, S25FL016A, W39V040B, W39V080A, SST49LF008A tests.Peter Stuge
I have tested MX25L4005, S25FL016A and W39V080A myself. Thanks also to the following testers: SST49LF008A Bernhard M. Wiedemann W39V040B Dan Lenski Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3356 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-27not sure why this ever worked. Add --xml / -x to the supported options (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3353 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-27sync latest version of abuild (0.6) (trivial patch)Stefan Reinauer
- parallel building - fix non-gnu-getopt systems - silent mode Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3351 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-27Mark SST49LF004A/B as tested (trivial).Mart Raudsepp
Tested by me on actual hardware (all operations) - Artec Group DBE62 with SST 49LF004B Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-26Mark the following chips as tested (trivial).Uwe Hermann
- AMD Am29F040B - SST SST39SF020A - Winbond W29C020C - Winbond W29EE011 - Winbond W49F002U All of them tested by me on actual hardware (all operations). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3349 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-22A bunch of cosmetic improvements (trivial).Uwe Hermann
- Fix typos and inconsistencies. - Drop duplicate line which tells us the chip name twice. - Also print the chip vendor, not only the name. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3348 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-22Mark more chips as tested (all operations), tested on ASUS P4B266 (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3347 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-22Add support for the ASUS P4B266 board.Uwe Hermann
Tested on actual hardware. This patch add an ich_gpio_raise() function which can be re-used by other board-specific funtions which need to raise GPIOs on ICHx southbridges. This also fixes bug #7, see http://tracker.coreboot.org/trac/coreboot/ticket/7, as it turned out the ICH2 (and other ICHx) code works fine. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3346 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-22Add support for Amic A25L40P SPI flash.Rudolf Marek
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3345 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-22Changes to make flashrom compile (and work) on FreeBSD.Andriy Gapon
This patch addresses different argument order of outX() calls, FreeBSD-specific headers, difference in certain type names and system interface names, and also FreeBSD-specific way of gaining IO port access. Signed-off-by: Andriy Gapon <avg@icyb.net.ua> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-21Myles reported SST49LF080A status -> TESTED_PREWPeter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3341 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-17Initial support for the Intel 82845 (Brookdale) and ICH2 (trivial).Uwe Hermann
Tested on hardware: Intel Northbridge: 8086:1a30 (i845) Intel Southbridge: 8086:2440 (ICH2) Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3333 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-17flashrom: Support Pm49FL004/2 Block Locking RegistersNikolay Petukhov
The PMC chips understand both LPC and FWH flash commands. When in FWH mode (MSR_DIVIL_BALL_OPT(0x51400015) = 0x00000f7d on 5536 boards) the Block Locking Registers by default lock the flash chip for write and erase - in addition to any chipset write protection. This patch adds unlock operations before Pm49FL004/2 write and erase, and it includes an svn mv pm49fl004.c pm49fl00x.c Thanks go to Nikolay for this patch. Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com> Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Bari Ari <bari@onelabs.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3332 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16I looked at the datasheet and erase_sector_39sf020() is totally andCarl-Daniel Hailfinger
completely wrong. It was a straight cut'n'paste from SST 28SF040 code and the person doing the cut'n'paste didn't even bother to check the data sheet. The SST 39SF020 is completely incompatible with the 28SF040. No need for replacement. According to the data sheet, standard JEDEC commands will work and we have those commands in the tree already. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3331 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16ICH8 and ICH9 have an almost identical SPI interface, only the locationCarl-Daniel Hailfinger
of the SPIBAR differs. Add ICH8 support to the ICH9 code. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3327 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16Add support for the Atmel AT25DF321 SPI flash (tested).Dominik Geyer
Change ST M25P32 status to tested. Signed-off-by: Dominik Geyer <dominik.geyer@kontron.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3326 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16Add support for SPI chips on ICH9. This is done by using the generic SPIDominik Geyer
interface. Signed-off-by: Dominik Geyer <dominik.geyer@kontron.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3325 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16Enable IT8716F LPC-to-SPI write cycle translation in flashrom if theCarl-Daniel Hailfinger
IT8716F decodes any address to the attached SPI ROM. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3324 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-15Print detailed status register information for SST25VF series flash.Carl-Daniel Hailfinger
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3323 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-15Lots of new SST flash chip IDs. Only a subset has been added toCarl-Daniel Hailfinger
flashchips.c, but the IDs in flash.h will make lookups easier if anybody wants to add support for them. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3321 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-15Add support for the JEDEC RES (Read Electronic Signature and Resume fromCarl-Daniel Hailfinger
Powerdown) SPI command to flashrom to identify older SPI chips which can't handle JEDEC RDID. Since RES gives a one-byte identifier which is shared among many different vendors and even different sizes, we want to match RES as a last resort if RDID returns 0xff 0xff 0xff. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> This is a heavily reworked version of a patch by Fredrik Tolf, which was Signed-off-by: Fredrik Tolf <fredrik@dolda2000.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14Some NSC Super I/Os can have their config port at 0x15c (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3319 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14Cosmetics, whitespace, coding style, partially ident-aided (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3318 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14add ICH7-M and ICH7 DH to inteltool (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3315 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14Add more infrastructure for flashrom ICH9 support.Carl-Daniel Hailfinger
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3314 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14fix license mentioning in manpage (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3313 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14trivial patch: move maintainable parts to the top and add ICH7-M DH southbridgeStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3312 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14trivial patch to fix options. Thanks to Uwe Hermann for the hint!Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3311 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14Add the Intel 6300ESB as known chipset to the chipset struct enables.Claus Gindhart
Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3310 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14Fix crash caused by division by zero for unknown flash chips.Carl-Daniel Hailfinger
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3309 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14Check the JEDEC vendor ID for correct parity. Flash chips which can beCarl-Daniel Hailfinger
detected by JEDEC probe routines all have vendor IDs with correct parity. Use a parity check as additional hint whether a vendor ID makes sense. Note: Device IDs have no parity requirements whatsoever. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3308 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14Example on how to add other chipsets to inteltool. ICH/ICH0, ICH4(-M) and ICH7Stefan Reinauer
have different register meanings, so they get their own lookup tables. This is a trivial patch. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3307 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14Add lots of ATMEL SPI flash chips to flash.h.Carl-Daniel Hailfinger
Add a few flashchips already mentioned in flash.h to flashchips.c Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3306 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-13flashrom: Move all IT87xx specific SPI routines from spi.c to a separateCarl-Daniel Hailfinger
file it87spi.c. No behavioural changes, but greatly improved SPI abstraction. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3305 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-13Add new revised inteltool that dumps all kinds of chipset information and ↵Stefan Reinauer
drop old gpio_dump utility. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3304 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-13flashrom: Move the SPI #defines from spi.c to spi.hCarl-Daniel Hailfinger
This patch has no code changes. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-13Change the SPI parts of flashrom to prepare for a merge ofCarl-Daniel Hailfinger
ICH9 SPI support. In theory, this patch has no behaviour changes. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3301 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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