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2014-11-23buildgcc: Fix documentationPatrick Georgi
Change-Id: I3983d7a393260238b75e9f52e9451b454c551c30 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/7550 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-21util/cbfstool/cbfs-mkstage.c: Fix build issue on 32-bit x86Francis Rowe
Fixes regression caused by commit 405304ac (cbfstool: Add option to ignore section in add-stage) Change-Id: If9e3eea9ab2c05027f660d0057a635abf981b901 Signed-off-by: Francis Rowe <info@gluglug.org.uk> Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7545 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-11-20crossgcc: Add buildsystem support for aarch64 compilerPatrick Georgi
This adds the crosstools-aarch64 and crossgcc-aarch64 make rules to create a toolchain (with or without gdb) for AArch64 targets. Also adapt xcompile, since it's aarch64-elf. Change-Id: I6fbe09d44ee8b8493d3cd8dbbba869b409e311f7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7527 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-20crossgcc: Update GCC from 4.7.3 to 4.8.3 and update to version 1.25Patrick Georgi
gcc 4.9.2 fails on our tree right now. We should clean that up and test before we make it the reference version. Also, the AMD K8/Fam10 issue we had last year, for which Vladimir provided an "untested" fix (which is in, commit a6c29fe6841ad5e03ddb35803943bed3bc83dfd2), isn't reproducible: I boot-tested an unpublished AMD K8 board with coreboot built with gcc 4.8.3. (Disclaimer: since the old issue depended on compiler decisions on register allocation, any change to code or compiler could mix up things in semi-random ways.) Change-Id: I8f1460a8da2c9e2d581482b22a4824b10b8987fa Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7526 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-11-18kconfig: create files in target directory if requestedPatrick Georgi
Otherwise rename() fails when used across filesystem boundaries. Change-Id: I22a62310f0e46ac9cfee50b7e9eeed93536ed409 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7504 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-14nvidia/cbootimage: update to masterPatrick Georgi
It contains a number of fixes to bugs found by Coverity Scan. Change-Id: I362a069afd37783f59d8831e44ae885e8490819e Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/7392 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-09abuild: pass compiler configuration options to tool building stepPatrick Georgi
This is required to run abuild parallely with clang without the canonical coreboot toolchain installed. Change-Id: Iea56d3f552d50ab6e762afa134091b0d8e38792c Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/7369 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-09inteltool: add more hardware IDs and PCIEXBAR/PXPEPBAR read supportFelix Held
Add IDs of some SNB and Haswell chips; use more descriptive names. Add PCIEXBAR and PXPEPBAR read support for SNB/IVB/Haswell. Change-Id: I16753bf90061fc2065b813b1c2169e7b7bcc89e8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/7360 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Mathias Krause <minipli@googlemail.com>
2014-11-06inteltool: Fix message in case of multiple LPC controllersMathias Krause
If we find multiple LPC controllers, we want to tell the user that we'll ignore all but the first. However, we use 'dev' in the message (the current device found) instead of 'sb' (the one we want to use). Fix the message by using 'sb' and break the loop right away in this case. It's sufficient to tell the user once which LPC controller we'll use. Change-Id: Ibd27e40525fabe8c63b112691ad49fd994c70a48 Signed-off-by: Mathias Krause <minipli@googlemail.com> Reviewed-on: http://review.coreboot.org/7342 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-11-06inteltool: Add support for Sandy Bridge desktop processorsFelix Held
Change-Id: I5e68b89c30d5550e4bce5c3e4c7b0689c38756bc Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/7337 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Mathias Krause <minipli@googlemail.com>
2014-11-05inteltool: Show more info on sandy/ivy.Vladimir Serbinenko
Change-Id: I408614e743ab6f0f447b327c01d8f4dacf787124 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6692 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-04inteltool/sandybridge: Kill mch_registers codepath.Vladimir Serbinenko
It never worked. Change-Id: Ic68614bb8ed481babf54b4f9d8db00635755f4d1 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7324 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-04abuild: fix cross compiler testPatrick Georgi
Actually abort if a cross compiler is missing, but also handle subarchitectures (currently: armv4 and armv7 for arm) properly. Change-Id: Idf37fb029178df6f2ac029466c66aaa2010bdbd2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7297 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-04inteltool: Add support for Haswell ULT and Lynx Point LPDennis Wassenberg
Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com> Change-Id: I2d5a31c831afeb92522b2673fde82922dc4efca5 Reviewed-on: http://review.coreboot.org/7275 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2014-11-04cbfstool: Add option to ignore section in add-stageFurquan Shaikh
Allow add-stage to have an optional parameter for ignoring any section. This is required to ensure proper operation of elf_to_stage in case of loadable segments with zero filesize. Change-Id: I49ad62c2a4260ab9cec173c80c0f16923fc66c79 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/7304 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-04cbfstool: Convert cbfs-mkstage.c into pelfFurquan Shaikh
Change cbfs-mkstage to use parsed elf instead of calling elf_headers. That allows us to have access to the complete elf including the string table. Change-Id: Ie767d28bdf41af38d1df0bce54bc0ada45123136 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/7303 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-02inteltool: refine GPIO and PMBASE/TCO printing on Ibex Peak/5 SeriesStefan Tauner
Nicolas Reinecke was noticing that in my Lenovo T410s logs the GPIO*3 settings were missing. This led to some investigation and this patch, thanks! Change-Id: I7ba28aa00d10f988a7fe81e61d2e216b54a11006 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/7239 Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2014-10-28A tool for IPQ8064 encapsulationVadim Bendebury
This is a copy of the tool provided by the vendor. It adds a header which tells the early stage loader where to load the next phase blob for execution. It is going to be used to encapsulate the bootblock. Usage of this tool is as follows: ipqheader.py <base-addr> <input-file> <output-file> Old-Change-Id: I448c006719f4f3dd5a6716ff2e47f7fc275c805e Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193494 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 201630f8637eb627f0894ecd7bceb31017244ad4) Make ipqheader.py executable Modify the utility to become a Linux executable. While at it, fix the program name reported by error messages. Old-Change-Id: I25061d43fdea72655a696deb9e494e9c7382f670 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193495 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit bbbf69c754aa3b6a1bf17ab3ced1c739c3ee0688) ipq8064: SBL headers must have 4 byte aligned blob sizes It turns out that for SBL3 to load the next phase, the sizes in the MBN header must be 4 byres aligned. This change makes sure that this requirement is enforced. Old-Change-Id: Ia64f04bb281ae772b060d2f7713c98dd348972ba Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/196167 (cherry picked from commit fa6a52a07cb87ecf2538a6b0d47605d79104e4cc) Add proper license to the ipqheader tool This patch adds a vanilla BSD 3-Clause license. Original-Change-Id: I9da7176e670b598808ef5be2461b6105a4c5f6c5 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225783 Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org> Original-Tested-by: Trevor Bourget <tbourget@codeaurora.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit a0c47a8d74f1ac131c91e978b6d68bbcfaa52c37) Squashed 4 commits for the ipqheader util. Change-Id: I144c01947a89e1348a06aa82590e972e2ec31247 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/6976 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-10-28rmodtool: add support for ARMAaron Durbin
Add support for creating ARM rmodules. There are 3 expected relocations for an ARM rmodule: - R_ARM_ABS32 - R_ARM_THM_PC22 - R_ARM_THM_JUMP24 R_ARM_ABS32 is the only type that needs to emitted for relocation as the other 2 are relative relocations. BUG=chrome-os-partner:27094 BRANCH=None TEST=Built vbootstub for ARM device. Original-Change-Id: I0c22d4abca970e82ccd60b33fed700b96e3e52fb Original-Signed-off-by: Aaron Durbin <adurbin@chromuim.org> Original-Reviewed-on: https://chromium-review.googlesource.com/190922 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit a642102ba7ace5c1829abe7732199eda6646950a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib3b3c90ebb672d8d6a537df896b97dc82c6186cc Reviewed-on: http://review.coreboot.org/7204 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-28cbfstool: If compression fails, warn and use the uncompressed data.Gabe Black
The LZMA compression algorithm, currently the only one available, will fail if you ask it to write more data to the output than you've given it space for. The code that calls into LZMA allocates an output buffer the same size as the input, so if compression increases the size of the output the call will fail. The caller(s) were written to assume that the call succeeded and check the returned length to see if the size would have increased, but that will never happen with LZMA. Rather than try to rework the LZMA library to dynamically resize the output buffer or try to guess what the maximal size the data could expand to is, this change makes the caller simply print a warning and disable compression if the call failed for some reason. This may lead to images that are larger than necessary if compression fails for some other reason and the user doesn't notice, but since compression errors were ignored entirely until very recently that will hopefully not be a problem in practice, and we should be guaranteed to at least produce a correct image. Original-Change-Id: I5f59529c2d48e9c4c2e011018b40ec336c4fcca8 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/187365 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit b9f622a554d5fb9a9aff839c64e11acb27785f13) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Change-Id: I5f59529c2d48e9c4c2e011018b40ec336c4fcca8 Reviewed-on: http://review.coreboot.org/6958 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-18util/fletcher: fix debug option parsingPatrick Georgi
sizeof(char[]-type+1) isn't very useful. Since one of the strings is constant, we also don't need to use strncmp that string's length. While at it, str*cmp don't return booleans, so check for value instead of faux bools. Change-Id: Iebb194a60eac454dafeade75f135df92068cf4ab Found-by: Coverity Scan Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6988 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-18abuild: skip boards for which we lack a cross compilerPatrick Georgi
We don't support them, they won't ever pass the build test, so no need to report an error. Change-Id: I2409a79f3c0d66a79b0e065e6b9ebf62d0359b3e Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/7121 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-10-18abuild: don't track architecturePatrick Georgi
This didn't work for a while, and we don't _really_ need it. Change-Id: I952243f30e985e7577cd511f40957066db6dd3c5 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/7120 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-10-18cbfstool: free memoryPatrick Georgi
Change-Id: Ic53127a61154460fa3741a92a3b2de0eba446e9f Found-by: Coverity Scan Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6987 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-18util/cbmem: Fix CBMEM TOC printingPaul Menzel
Since commit c0199078 (cbmem utility: Find actual CBMEM area) [1], at least on the Lenovo X201, X230 and X60, printing the CBMEM table of contents did not work. It still worked on the ASRock E350M1 though. $ sudo /src/coreboot/util/cbmem/cbmem -l --verbose # Lenovo X60t Looking for coreboot table at 0 Mapping 1MB of physical memory at 0x0. Found! coreboot table entry 0x11 Found forwarding entry. Unmapping 1MB of virtual memory at 0xb74dc000. Looking for coreboot table at 7f6c4000 Mapping 1MB of physical memory at 0x7f6c4000. Found! coreboot table entry 0xc8 coreboot table entry 0x01 Found memory map. coreboot table entry 0x03 coreboot table entry 0x04 coreboot table entry 0x05 coreboot table entry 0x06 coreboot table entry 0x07 coreboot table entry 0x08 coreboot table entry 0x09 coreboot table entry 0x0a coreboot table entry 0x16 Found timestamp table. cbmem_addr = 7f7dd000 coreboot table entry 0x17 Found cbmem console. cbmem_addr = 7f7de000 Unmapping 1MB of virtual memory at 0xb74dc000. No coreboot CBMEM area found! The address of the boot info record has to be used for checking, that reading takes place in the bounds of the boot info record. $ sudo ~/src/coreboot/util/cbmem/cbmem -l # Lenovo X60 CBMEM table of contents: ID START LENGTH […] Big thanks to David and Stefan for their help. [1] http://review.coreboot.org/2117 Change-Id: I1eb09a6445d9ea17e1e16b6866dece74315d3c73 Found-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/7093 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-18util/cbmem/cbmem: Remove obsolete commentPaul Menzel
Originally the utility cbmem was just used for reading out the time stamps and was later extented. The removed comment is currently at the wrong place and `cbmem` does much more now, so that the comment is just removed. Change-Id: Ief1d7aef38a4b439e3e224e6e6c65f7aa57f821f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/7091 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-10-16RISCV: add this architecture to cbfstoolRonald G. Minnich
Change-Id: I6d972e595f12585cda08e1a6d2b94b4bf4f212f5 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/7067 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-10-08xcompile: detect and use RISCV binariesRonald G. Minnich
RISCV is a new architecture. This change simply setups up xcompile to detect and use RISCV compilers if they are found. Change-Id: Iad1a88ef2e3c8dd1e601549aeca26fb29b2bc7ae Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/7023 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-10-08mkelfimage: removeRonald G. Minnich
It's not been needed for years, is definitely not needed now that cbfstool parses bzImages, and its presence keeps confusing people. Also, rewrite history. We never mentioned mkelfimage in the documentation. Never, ever, ever. Change-Id: Id96a57906ba6a423b06a8f4140d2efde6f280d55 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/7021 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <gaumless@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-10-07sconfig: add cpu device typeAaron Durbin
In order to enumerate CPU devices that are non-x86 (read: no lapic) provide a generic 'cpu' device. Change-Id: Ifeafdad8076935c3448784e6958117002509acbf Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/6824 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-10-02nvidia/cbootimage: avoid upstream's build systemPatrick Georgi
It brings in useless dependencies, a weird autotools configuration, and tons of pain everywhere. Instead just build things ourselves. Change-Id: I67f06e711cb9dcd594363bc1a4f99d3273074549 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6986 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-25cbfstool: Propogate compression errors back to the caller.Gabe Black
When compression fails for whatever reason, the caller should know about it rather than blindly assuming it worked correctly. That can prevent half compressed data from ending up in the image. This is currently happening for a segment of depthcharge which is triggering a failure in LZMA. The size of the "compressed" data is never set and is recorded as zero, and that segment effectively isn't loaded during boot. Change-Id: Idbff01f5413d030bbf5382712780bbd0b9e83bc7 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/187364 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit be48f3e41eaf0eaf6686c61c439095fc56883cec) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6960 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-09-23cbfstool: Add AARCH64 reloc types to elf.hFurquan Shaikh
Change-Id: Ifd4726491e01c3acebd3dfc326c1be994b0aefb8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/214328 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/6955 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2014-09-23mkelfimage: Add EM_AARCH64 as elf image type for arm64Furquan Shaikh
Change-Id: I5510a4fe5085430b767161133113578b7cffa237 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/214327 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/6954 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2014-09-23rmodtool: Allow rmodules with 0 relocationsFurquan Shaikh
Currently, rmodules with 0 relocations are not allowed. Fix this by skipping addition of .rmodules section on 0 relocs. Change-Id: I7a39cf409a5f2bc808967d2b5334a15891c4748e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/6774 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2014-09-23coreboot arm64: Add support for arm64 into coreboot frameworkFurquan Shaikh
Add support for enabling different coreboot stages (bootblock, romstage and ramstage) to have arm64 architecture. Most of the files have been copied over from arm/ or arm64-generic work. Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/197397 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 033ba96516805502673ac7404bc97e6ce4e2a934) This patch is essentially a squash of aarch64 changes made by these patches: d955885 coreboot: Rename coreboot_ram stage to ramstage a492761 cbmem console: Locate the preram console with a symbol instead of a sect 96e7f0e aarch64: Enable early icache and migrate SCTLR from EL3 3f854dc aarch64: Pass coreboot table in jmp_to_elf_entry ab3ecaf aarch64/foundation-armv8: Set up RAM area and enter ramstage 25fd2e9 aarch64: Remove CAR definitions from early_variables.h 65bf77d aarch64/foundation-armv8: Enable DYNAMIC_CBMEM 9484873 aarch64: Change default exception level to EL2 7a152c3 aarch64: Fix formatting of exception registers dump 6946464 aarch64: Implement basic exception handling c732a9d aarch64/foundation-armv8: Basic bootblock implementation 3bc412c aarch64: Comment out some parts of code to allow build ab5be71 Add initial aarch64 support The ramstage support is the only portion that has been tested on actual hardware. Bootblock and romstage support may require modifications to run on hardware. Change-Id: Icd59bec55c963a471a50e30972a8092e4c9d2fb2 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6915 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2014-09-15cbfstool: add aarch64 as a nameRonald G. Minnich
The aarch64 is not really an arm variant, it's sufficiently different that it can be considered (for purposes of cbfs, certainly) to be a new architecture. Add a constant in cbfs.h and strings to correspond to it. Note that with the new cbfstool support that we added earlier, the actual use of aarch64 ELF files actually "just works" (at least when tested earlier). Change-Id: Ib4900900d99c9aae6eef858d8ee097709368c4d4 Reviewed-on: https://chromium-review.googlesource.com/180221 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit f836e14695827b2667804bc1058e08ec7b297921) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6896 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-13to-wiki: Add IVYBRIDGE_NATIVE to the list of ivybridge names.Vladimir Serbinenko
Change-Id: I6e63abd9491a76e362347b7616e00104305827ee Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6691 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-13towiki.sh: Rename GM45 slot and cpu to correct ones.Vladimir Serbinenko
Change-Id: Idc8135911549ac39c28932065897ca6643c13656 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6690 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-12cbfstool: Fix architecture check when adding payloadStefan Reinauer
In the process of rewriting cbfstool for ARM and using a new internal API a regression was introduced that would silently let you add an ARM payload into an x86 CBFS image and the other way around. This patch fixes cbfstool to produce an error in that case again. Change-Id: I37ee65a467d9658d0846c2cf43b582e285f1a8f8 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/176711 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 8f74f3f5227e440ae46b59f8fd692f679f3ada2d) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6879 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-09-09exynos: Install the BL1 and set the checksum in the Makefile.Gabe Black
Install the BL1 and set up the checksum in the Makefile instead of relying on post processing. Import the exynos checksum script, split it in two and simplify it significantly. Stop putting the CBFS header in the midst of the bootblock so that it can be checksummed before CBFS is put together. Stop saving space for it and leaving an anchor in the bootblock which nobody looks for. Change-Id: Icbb5a5914ece60b2827433b6dc29d80db996ea6c Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/179229 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit aa3a416705517c0a6ddfdeb19905ac8cafb33df1) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6834 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-08ARM: Generalize armv7 as arm.Gabe Black
There are ARM systems which are essentially heterogeneous multicores where some cores implement a different ARM architecture version than other cores. A specific example is the tegra124 which boots on an ARMv4 coprocessor while most code, including most of the firmware, runs on the main ARMv7 core. To support SOCs like this, the plan is to generalize the ARM architecture so that all versions are available, and an SOC/CPU can then select what architecture variant should be used for each component of the firmware; bootblock, romstage, and ramstage. Old-Change-Id: I22e048c3bc72bd56371e14200942e436c1e312c2 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171338 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 8423a41529da0ff67fb9873be1e2beb30b09ae2d) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> ARM: Split out ARMv7 code and make it possible to have other arch versions. We don't always want to use ARMv7 code when building for ARM, so we should separate out the ARMv7 code so it can be excluded, and also make it possible to include code for some other version of the architecture instead, all per build component for cases where we need more than one architecture version at a time. The tegra124 bootblock will ultimately need to be ARMv4, but until we have some ARMv4 code to switch over to we can leave it set to ARMv7. Old-Change-Id: Ia982c91057fac9c252397b7c866224f103761cc7 Reviewed-on: https://chromium-review.googlesource.com/171400 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 799514e6060aa97acdcf081b5c48f965be134483) Squashed two related patches for splitting ARM support into general ARM support and ARMv7 specific pieces. Change-Id: Ic6511507953a2223c87c55f90252c4a4e1dd6010 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6782 Tested-by: build bot (Jenkins)
2014-09-08nvidia-cbootimage: add submoduleIsaac Christensen
Change-Id: I3ad8eed42255db426987065190c197baead40673 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6836 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-06romcc: avoid use-after-freePatrick Georgi
Windows bugchecks on this for a while, so we ifndef'd the free() call out. Now some Linuxes (depending on their glibc) also fail on it, so just remove the call altogether at the cost of some leaked memory (couple hundred kilobytes) because tracking down the precise fix is too hard. In case someone wants to fix it, valgrind sees the issues, so revert this change and work on romcc's memory management until valgrind is happy. To get a fix in, provide a good explanation why your change is actually the right way to fix it - for silencing valgrind, this change will do. Change-Id: Iae3f847e09a0d7bcb8bb4f50983a1b0727570b23 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6846 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-09-04cbfstool:linux_trampoline: config CS and DS segment descriptorsCurt Brune
The Linux trampoline code does not set up the segment descriptors for __BOOT_CS and __BOOT_DS as described in the Linux kernel documentation: ... a GDT must be loaded with the descriptors for selectors __BOOT_CS(0x10) and __BOOT_DS(0x18); both descriptors must be 4G flat segment; __BOOT_CS must have execute/read permission, and __BOOT_DS must have read/write permission; This is not a problem when launching a Linux payload from coreboot, as coreboot configures the segment descriptors at selectors 0x10 and 0x18. Coreboot configures these selectors in the ramstage to match what the Linux kernel expects (see coreboot/src/arch/x86/lib/c_start.S). When the cbfs payload is launched in other environments, SeaBIOS for example, the segment descriptors are configured differently and the cbfs Linux payload does not work. If the cbfs Linux payload is to be used in multiple environments should the trampoline needs to take care of the descriptors that Linux requires. This patch updates the Linux trampoline code to configure the 4G flat descriptors that Linux expects. The configuration is borrowed from the descriptor configs in coreboot/src/arch/x86/lib/c_start.S for selectors 0x10 and 0x18. The linux_trampoline code is slightly refractored by defining the trampoline entry address, 0x40000, as TRAMPOLINE_ENTRY_LOC. This definition is moved into a separate header file, linux_trampoline.h. This header file is now included by both the trampoline assembly language code and the trampoline loader C code. The trampoline assembly language code can now use TRAMPOLINE_ENTRY_LOC as scratch space for the sgdt CPU instruction. Testing Done: Verified the Linux payload is booted correctly in the following environments: 1. Coreboot -> Linux Payload 2. Coreboot -> SeaBIOS -> Linux Payload: (previously did not work) Change-Id: I888f74ff43073a6b7318f6713a8d4ecb804c0162 Signed-off-by: Curt Brune <curt@cumulusnetworks.com> Reviewed-on: http://review.coreboot.org/6796 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-03lint: simplify board-status checkPatrick Georgi
git can do lots of things by itself, no need to parse its output and redo that. Change-Id: Id2cdd2ea8d34c1ba2b0abddc88e1f3260d74f47d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6798 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-30AMD Steppe Eagle: Add 32-bit Fletcher's Checksum computationBruce Griffith
The AMD Platform Security Processor (PSP) requires a Fletcher's Checksum at the end of the PSP directory. This code implements a Fletcher's Checksum by reading bytes from stdin and writes the bytes back to stdout with a checksum inserted into the byte stream at the appropriate offset. This utility is used on PSP binaries during coreboot build. Include a runtime debug option such that the command: fletcher --print <file.bin >file_with_cksum.bin will print out the computed checksum value for debugging. The compile-time debug option is retained that allows -DDEBUG to be added to the compilation line. This option has the same effect as "--print". Change-Id: I506a479d8204ca4f8267d53aa152ac4b473dbc75 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/6676 Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com>
2014-08-27rmodtool: correct final memory size calculationAaron Durbin
Apparently when I originally wrote this I confused myself to no end. The code/data of an rmodule has a set memory size which is associated with the .payload section. The relocation entries may increase the overall footprint of the memory size if the rmodule has no bss but a lot of relocations. Therefore, just compare relocation entries size plus the file size of the .payload section with the memory size of the paylod section. The .empty section is added only when we have not met the final target size. Change-Id: I5521dff048ae64a9b6e3c8f84a390eba37c7d0f5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/6767 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2014-08-26util/inteltool: fix typoIdwer Vollering
Change-Id: I8c30742f6cd759dce4c9641edad107d9e3154975 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/6766 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-25xcompile: always use -march=i686Aaron Durbin
When compiling coreboot for x86 on gcc the compiler is free to pick whatever defaults it is using at the time of gcc's compile/configuration when no -march is specified. Not properly specifying -march then opens up the use of SSE instructions for compilation units it should not be used such as the SMM module as this module doesn't save/restore SSE registers. Change-Id: I64d4a6c5fa9fadb4b35bc7097458e992a094dcba Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172640 Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit d49358f7959bb52c3e7ff67d37c21a1b294adf72) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6716 Tested-by: build bot (Jenkins)
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