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2008-03-16check whether SST FWH chip was successfully erased on flashchip -E, tooStefan Reinauer
(trivial) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3153 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-16Sort list of flash chips alphabetically, add comment (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3152 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-15remove nasty warning that happened due to our vendor detectionStefan Reinauer
mechanism. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3151 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-15fix typoStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-14Re-add code erroneously removed in r3140.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3146 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-14Changes M50FW080 to use 82802ab.c instead of jedec.c. This fixes the problem ↵Joseph Smith
of not being able to erase the chip. Signed-off-by: Joseph Smith <joe@smittys.pointclark.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3145 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-14Prepare for ICH7/ICH8 SPI support by adding some debugging for allCarl-Daniel Hailfinger
ICH* chipsets. Functionality (except printing) should be unchanged. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Ward says: This code detects the ICH8 chipset on my laptop, and it appears to use SPI. Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3144 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-14Fix broken flashrom build.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3142 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-14Fix up one forgotten revert in r3140.Carl-Daniel Hailfinger
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3141 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-14Revert the delete of 82802ab.c in r3137.Carl-Daniel Hailfinger
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3140 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-13Also print the chip vendor name in --list-supported output (trivial).Uwe Hermann
Cosmetic changes in some files, partly bending the 80-characters-per-line rule in this special case, as the 80-character-limited version looks equally crappy even in an 80x25 console/xterm, so let's make it at least look good in a high-resolution xterm. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3139 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-13Also print the required -m option in --list-supported output (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3138 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-13Drop 82802ab.c as it is identical to sharplhf00l04.c.Carl-Daniel Hailfinger
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3137 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-12Drop the useless rom.layout file. It's just an example, likely neverUwe Hermann
been used in the last few years, and the contents are available in the README already anyway. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3134 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-12Add --list-supported option to flashrom which lists the supportedUwe Hermann
ROM chips, chipsets, and mainboards (Closes #90). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3133 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-10Add GPIO dumping utility for Intel ICH series southbridges.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Signed-off-by: Joseph Smith <joe@smittys.pointclark.net> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3132 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-04Drop some duplicate documentation from the README. The manpage andUwe Hermann
'superiotool --help' already provide the same information (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3127 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-04Add missing license header to layout.c. The file was written byUwe Hermann
Stefan Reinauer for coresystems GmbH in 2005, as confirmed on IRC. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3126 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-01Rename lxbios to nvramtool, step 3 (rename directory).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3124 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-01Rename lxbios to nvramtool, step 2 (rename files).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3123 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-01Rename lxbios to nvramtool.Uwe Hermann
This is step 1 in a three-step commit: 1. Apply patch, commit. 2. Rename some files: $ svn mv lxbios.c nvramtool.c $ svn mv lxbios.1 nvramtool.c $ svn mv lxbios.spec nvramtool.spec $ svn ci 3. Rename lxbios directory: $ svn mv lxbios/ nvramtool/ $ svn ci Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3122 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-01Small coding style fixes and documentation updates (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3121 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-25This patch adds support to dump other registers than the primaryRonald Hoogenboom
pnp-style configuration registers, using the new option -e/--extra-dump. This patch only adds dumping of the Environmental Controller configuration registers for the IT8716f chip. Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl> I (Carl-Daniel) checked the data sheets of the whole IT87[012] series and although the environment controller is sometimes called fan controller, the location of the register is the same for all models. Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3117 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-20flashrom: Add board_enable for Artec Group DBE61 and DBE62Mart Raudsepp
Also add a comment about NULL subsystem IDs leaving the board entry out of auto-detection logic. Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Acked-by: Luc Verhaegen <libv@skynet.be> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3110 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-18Should be part of changeset 3106.Rudolf Marek
This patch introduces virtual LDNs changes for W83627EHF driver. Not only LDN 7 and 9 are changed, but also a SPI flash interface which has enable on bit1 and not bit0. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3108 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-15Importing mkelfimage fromStefan Reinauer
ftp://ftp.lnxi.com/pub/mkelfImage/mkelfImage-2.7.tar.gz Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3103 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-14With this small change it is possible to build flashrom again whenClark Rawlins
specifying custom CFLAGS/LDFLAGS from the make command line like: make CFLAGS="..." LDFLAGS="..." I need to do this when building flashrom in a cross compiler environment like buildroot for a foreign target. Signed-off-by: Clark Rawlins <clark@bit63.org> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3102 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-11flashrom: further cleanups to enable_flash_cs5536Mart Raudsepp
- Remove the "enable write to flash" message, as the caller appears to already report that. - Move the 'modprobe msr' suggestions to the first lseek64 error handling, as we get an error there already. - Rename a perror string from "read" to "read msr", as we use the latter already in this function for another read. Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3101 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-09Flashrom: Add board enable for VIA EPIA SP.Luc Verhaegen
Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-08Improve error handling and make RCONF_DEFAULT_MSR address be a constant.Mart Raudsepp
Also, move a big code comment to the top of enable_flash_cs5536(). Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3098 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-08This implements support for devices using AMD Geode companion chipMart Raudsepp
CS5536 that have the Boot ROM on NOR flash that is directly connected to FLASH_CS3 (Boot Flash Chip Select). We need to write enable it in the NORF_CTL MSR register for flashrom to be able to write to it, including JEDEC probe commands. This patch allows us to stop using AMD gx_utils.ko for BIOS flashing on the DBE61. Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-06Handle JEDEC JEP106W continuation codes in SPI RDID. Some vendors likeCarl-Daniel Hailfinger
Programmable Micro Corp (PMC) need this. Both the serial and parallel flash JEDEC detection routines would benefit from a parity/sanity check of the vendor ID. Will do this later. Add support for the PMC Pm25LV family of SPI flash chips. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Chris Lingard <chris@stockwith.co.uk> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3091 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-28Fix mptable util so the output will compileJon Dufresne
Signed-off-by: Jon Dufresne <jon.dufresne@gmail.com> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3084 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-27Make the vendor name optional in the -m flashrom parameter when there's onlyPeter Stuge
one board name that matches. The full syntax still works, and is required when two vendors have boards with the same names. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-27Forgot to add Spansion S25FL016A to README, trivial.Peter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-26Correctly disable the ROM area Write Protect bit in the Geode LX.Marc Jones
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Peter Stuge <peter@stuge.se> Tested on the pcengines alix1c and works fine. Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3078 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-25Various small fixes and updates for lxbios (trivial).Uwe Hermann
- Update website URL to http://coreboot.org/Lxbios. - Use svn:keywords property to actually expand the $Id$ entries. - Update COPYING to the latest version from http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3075 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-25Add ids and chip entry for Spansion S25FL016A to flashrom, tested,Peter Stuge
working. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3074 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-22Here is just a little and simple patch to get the MX25L3205D working.Harald Gutmann
I've tested and verified the chip myself, and it seems to work everything like supposted, since Carl-Daniel has patched flashrom to use the read funktion on verifying. "benchvice flashrom # ./flashrom -m gigabyte:m57sli -v test.4mb Calibrating delay loop... OK. No coreboot table found. Found chipset "NVIDIA MCP55", enabling flash write... OK. Found board "GIGABYTE GA-M57SLI-S4": enabling flash write... Serial flash segment 0xfffe0000-0xffffffff enabled Serial flash segment 0x000e0000-0x000fffff enabled Serial flash segment 0xffee0000-0xffefffff disabled Serial flash segment 0xfff80000-0xfffeffff enabled LPC write to serial flash enabled serial flash pin 29 OK. MX25L3205 found at physical address 0xffc00000. Flash part is MX25L3205 (4096 KB). Flash image seems to be a legacy BIOS. Disabling checks. Verifying flash... VERIFIED. benchvice flashrom # ls -l test.4mb -rw-r--r-- 1 root root 4194304 22. Jan 16:27 test.4mb Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3072 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-22Flashrom did not use the read function for verifying, it used direct memoryCarl-Daniel Hailfinger
access instead. That fails if the flash chip is not mapped completely. If the read function is set in struct flashchip, use it for verification as well. This fixes verification of all SPI flash chips >512 kByte behind an IT8716F flash translation chip. "MX25L8005 found at physical address 0xfff00000. Flash part is MX25L8005 (1024 KB). Flash image seems to be a legacy BIOS. Disabling checks. Verifying flash... VERIFIED." Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Harald Gutmann <harald.gutmann@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3070 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-22Make sure we delay writing the next byte long enough in SPI byteCarl-Daniel Hailfinger
programming. Minor formatting changes. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Harald Gutmann <harald.gutmann@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3069 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-21Omitting the wait for SPI ready when there is no data to be read, e.g.Ronald Hoogenboom
readcnt==0 saves 10 seconds with the unconditional 10us delay, reducing programming time for SST25VF016B to 40-45 secs. Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-21This patch adds version information to flashrom. Because 'v' and 'V'Bernhard Walle
are already in use, the patch uses 'R' (for release) and, of course, '--version'. Signed-off-by: Bernhard Walle <bernhard.walle@gmx.de> Acked-by: Ulf Jordan <jordan@chalmers.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-19Add Bingxun Shi <bingxunshi@gmail.com> to the list of contributors (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3064 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-19Small superiotool fix to detect more Winbond W83627EHF chips. TheUwe Hermann
patch is tested on actual hardware. As per datasheet the ID should be 0x886? for those chips. Not mentioned in the datasheet, but sensors-detect says 0x8853 is also possible. Also, the ASUS A8V-E Deluxe (W83627EHF) has an ID of 0x8854 (verified on actual hardware). So assume all 0x88?? IDs to mean W83627EHF/EF/EHG/EG. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3063 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-19This patch is for winbond w83627DHG superio support in superiotool.Bingxun Shi
I have test that on my board, it works ;) Signed-off-by: Bingxun Shi <bingxunshi@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3062 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-19Support SPI flash chips bigger than 512 kByte sitting behind IT8716FRonald Hoogenboom
Super I/O performing LPC-to-SPI flash translation. Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3061 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18Document the --list-supported option. Various small fixes (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3060 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18Minor documentation improvements/fixes in the README and manpage (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3059 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18rename linuxbios_* files in utils repository.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3058 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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