summaryrefslogtreecommitdiff
path: root/util
AgeCommit message (Collapse)Author
2019-06-09autoport: Generate a libgfxinit template when IGD is detectedIru Cai
Change-Id: I213628e525cc11c502de7d538bd60f49f3a930b9 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-07ifdtool: Enable GbE/PDR/EC region access only if they existDuncan Laurie
Instead of assuming GbE/PDR/EC regions may exist or not, check if there is a valid region defined in the descriptor and set the region access permissions based on that. The net effect change is to enable the use of the PDR region on the sarien platform, which also uses the GbE and EC regions. This results in the following example changes: mb/google/sarien (GbE, PDR, EC) . DESC BIOS ME GbE PDR EC -BIOS r rw rw r ------------------------------- +BIOS r rw rw rw r mb/google/eve: (no GbE, no PDR, no EC) . DESC BIOS ME GbE PDR EC -BIOS r rw rw r -ME r rw r -GbE r rw -EC r rw ------------------------------- +BIOS r rw +ME r rw +GbE +EC BUG=b:134703987 Change-Id: I7aeffc8f8194638c6012340b43aea8f8460d268a Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33273 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-04util/lint: Make usage of IS_ENABLED() an errorNico Huber
As long as we keep the IS_ENABLED() definition in libpayload for compatibility, we should check that IS_ENABLED() usage doesn't sneak back in. Also remove all other IS_ENABLED() checks. Change-Id: Id30ffa0089cec6c24fc3dbbb10a1be35f63b3d89 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-06-03qcs405: util/qualcomm: Add T32 debug scriptsNitheesh Sekar
Add T32 scripts that allow debug of any coreboot stage on qcs405. Change-Id: I4e792a2806e5ebd3b4075c7bb69c43587920deae Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29951 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-29xcompile: Remove --rtlib switch from clang CFLAGSDamien Zammit
Fix the following error from clang invoking gcc linker with wrong arg: i386-elf-gcc: error: unrecognized command line option '--rtlib=libgcc'; did you mean '-static-libgcc'? clang-4.0: error: linker (via gcc) command failed with exit code 1 Just remove --rtlib switch from CFLAGS relating to clang Change-Id: Ife7ef6b6b47a04598fc67b40751bc59eed93b4af Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/21354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-29util/autoport: Add info about rank 1 mirroringEvgeny Zinoviev
inteltool can't detect whether address mapping is normal or mirrored, which in turn may be cause RAM initialization to fail when using spd.bin generated by inteltool. Mention this in readme as it may help someone. Change-Id: I8d24e4d9332bdcf484987581dd6941e2bf9c4f87 Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-05-28util/xcompile/xcompile: apply -march to clang as well as gccAlan Green
For x64 and x86_32 configurations, apply the -march flag to both GCC and Clang flags. This solves the problem of Clang-compiled coreboot failing due to Clang emitting SSE instructions for code that is executed while SSE is not enabled. This patch takes functionality targeted for GCC configurations and moves it down a few lines, modifying CFLAGS instead of GCC_CFLAGS in order that it applies to both GCC and Clang. This is an alternate patch to CB:32887. Signed-off-by: Alan Green <avg@google.com> Change-Id: I6a6a6136b01a64d46f730ed19ebbeaadaf2183df Reviewed-on: https://review.coreboot.org/c/coreboot/+/32923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-23util/romcc: Add extra null pointer checkJacob Garber
It is possible that 'lnode->val' is set to 0 on a previous iteration of the loop, so check that it is non-null here before dereferencing it. Change-Id: I9827dd5623eaf11240df605a8b50ff9e27a5fce0 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1129149 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-23util/romcc: Fix memory leakJacob Garber
The 'new_type' function already allocates memory, so it is only necessary to clone the existing type if this function is not called. Change-Id: I47065204c5f4b6bab022bd7ccf19838c3ce1f86e Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity Scan CID 1129106 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-23util/romcc: Add null check for filenameJacob Garber
It is possible that 'filename' is still null in this if statement, so we add an extra check to prevent a null dereference in strcmp. Change-Id: Iaba95b63a4d552051e0c56445522de7274dfd0b3 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1395330 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-23util/romcc: Add extra NULL checks for memberJacob Garber
In each of these cases it is possible that 'member' is NULL at the beginning, which will skip the earlier while loops entirely and cause a NULL dereference later on. Add extra error checks to prevent this. Change-Id: Ib5873c0830b71397ef661976d387fc6ce33c5cd1 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1129147, 1129152, 1129153, 1129154 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-23util/autoport: Mention i2c-i801 module in readme.mdEvgeny Zinoviev
SMBus adapter will not appear if i2c-i801 module is not loaded. Added it to the readme. Change-Id: I3de0e02f13178d78b8cc02a74a745ad66e929070 Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-22util/sconfig: Move 'static' at beginning of declarationElyes HAOUAS
When using -Werror=old-style-declaration, gcc reports an error: "'static' is not at beginning of declaration" Tested on 945G-M4 board. Change-Id: I7216a4fab2d5878066c871166e6a481d1f201a9d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-05-22util/romcc: Prevent out-of-bounds readJacob Garber
If 'class > LAST_REGC', then there will be an out-of-bounds read when accessing 'regcm_bound'. Prevent this by skipping to the next iteration of the loop. Note that this should not generally happen anyway, since 'result' represents a bitset for the indices of 'regcm_bound', and so iterations where 'class > LAST_REGC' should already be skipped by the previous continue statement (since those bits of 'result' should all be zero). Found-by: Covericy CID 1129122 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: Id5f5adb0a292763251054aeecf2a5b87a11297b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-05-21util/romcc: Fix parsing of empty string literalJacob Garber
The corner case of an empty string literal was causing romcc to segfault. This checks if the literal is empty, and if so allocates a size one buffer for the terminating null character. A test case for this is added to ensure it doesn't happen again. Found-by: Coverity CID 1129099 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I067160a3b9998184f44e4878ef6269f372fe68bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/32852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-21util/romcc: Free variable after it is usedJacob Garber
Free 'arg_type' after it is used to prevent a memory leak. Found-by: Coverity Scan CID 1129114 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I5e8661547bb7623463ed23fc45269049ffb8c50e Reviewed-on: https://review.coreboot.org/c/coreboot/+/32841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-21util/romcc: Use 64 bit integers when shiftingJacob Garber
'used_indices' is 64 bits wide, so use a fixed-width type to make that clear. As such, 'index' can have a value of up to 63, so use a 64 bit integer when doing the shifts to prevent overflow. Found-by: Coverity Scan CID 1287090 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: Ibd089df6be60c8ea46da11e5e83cd58b2e2c54d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32854 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-20util: Fix typo on plural form of indexElyes HAOUAS
Change-Id: Idc165f8eafacf3130a29b701bc3610c1a67f69d5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-05-20util/scripts: update references to cross-repo-cherrypickJett Rink
It appears that the rebase.sh script was renamed to cross-repo-cherrypick and changed directories. Update comments to reflect that change. Change-Id: I863df48378feb48c9b195b1778dcaf1972a4f105 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-15util/lint/check-style: Don't hardcode clang-format pathAlex James
Signed-off-by: Alex James <theracermaster@gmail.com> Change-Id: I688cb60c98370bf74aa8554bab43594ff84c4e24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-15autoport: Remove unneeded include <arch/io.h>Elyes HAOUAS
Change-Id: I7cb4b47e2fd893274303bb20dc7fa895830b4493 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-15util/inteltool: Add Kabylake E3-1200 SupportChristian Walter
Change-Id: I5c55102d7ce15dbb708e9433500ebd1ed53179ad Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13crossgcc: Upgrade acpica to version 20190509Elyes HAOUAS
Changes: https://acpica.org/node/170 Change-Id: I6779a20005ffc0d4781bb60de3ba48759ef67d40 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-05-13util/inteltool: Use appropriate channel for printing timingsJacob Garber
At least one channel must be present, so print an error if there is not. However, we cannot always assume it will be the first channel, so make the appropriate selection when printing the timings. Found-by: Coverity Scan #1370{584,585,588,589,590-596,600} Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I6b59989242e498474782876302e0850e3e4cf2d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13util/kconfig: Use snprintf to avoid buffer overflowJacob Garber
'name' and 'env' are supposed to be file system paths, but could overflow the buffer if configured incorrectly. Let's avoid that entirely. Found-by: Coverity Scan #1362515 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I1aef36819d49ebcbde1c51995dc0961c85e74150 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-13util/intelvbttool: Add error checking for memory allocationJacob Garber
It is possible that 'malloc_fo_sub' and 'remalloc_fo' can fail, so add appropriate error checks for those cases. This incidentally fixes a possible memory leak when 'malloc_fo_sub' succeeds but 'remalloc_fo' does not. Found-by: Coverity Scan #1396050 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I944b67f5cdcfd7a687e81d8bb01a209c9dc9b0b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13util/intelvbttool: Free file object on error pathJacob Garber
Prevents a memory leak. Found-by: Coverity Scan #1396047 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I4c72a17351d8afbe23302edfeeba74b17608aef2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13util/ifdtool: Add find_fd null checkJacob Garber
As the previous comment indicated, this null check is currently superfluous, but adding it in makes Coverity happy, and future-proofs the code in case someone changes the internals of 'find_fcba' later and forgets/doesn't know to update this error check. Found-by: Coverity Scan #1395066 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I594cd0098f5b36cef5b3efc4c904710d3ba9b815 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-12nb/intel/snb: Drop NORTHBRIDGE_INTEL_IVYBRIDGENico Huber
We keep the support, though. Just now that `libgfxinit` is fixed, we don't need the distinction anymore. Causally, we also don't need CPU_INTEL_MODEL_306AX any more. TEST=Played tint on kontron/ktqm77. Score 606 Change-Id: Id1e33c77f44a66baacba375cbb2aeb71effb7b76 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-05-09vboot: include vb2_sha.h when requiredJoel Kitching
Should include vb2_sha.h header when SHA library functions or constants are required. This replaces NEED_VB2_SHA_LIBRARY. BUG=b:124141368, chromium:956474 TEST=make clean && make test-abuild BRANCH=none Change-Id: I9f32174dbf3de05fbe5279cb8017888757abf368 Signed-off-by: Joel Kitching <kitching@google.com> Cq-Depend: chromium:1583820 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-07{src,util}: Remove duplicated includesElyes HAOUAS
Change-Id: Id09cec6b2aae58b131b208e96fec539d068ff68a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-07sconfig: Add SMBIOS type 9 entriesPatrick Rudolph
Add the new field 'smbios_slot_desc', which takes 2 to 4 arguments. The field is valid for PCI devices and only compiled if SMBIOS table generation is enabled. smbios_slot_desc arguments: 1. slot type 2. slot lenth 3. slot designation (optional) 4. slot data width (optional) Example: device pci 1c.1 on smbios_slot_desc "21" "3" "MINI-PCI-FULL" "8" end # PCIe Port #2 Integrated Wireless LAN Tested on Lenovo T520. Change-Id: If95aae3c322d3da47637613b9a872ba1f7af9080 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-05-06inteltool: Add Sunrise Point-LP Skylake PCH IDsFelix Singer
Sunrise Point-LP is used on Skylake and KabyLake platforms, but the PCH IDs differ. This commit adds the PCH IDs for Skylake mobile platforms and renames the Kabylake macros to distinguish them. Used Intel documents: - 332995-001EN (I/O datasheet vol. 1) - 332996-002EN (I/O datasheet vol. 2) Change-Id: Id46224fcc44b06c91cbcd6c74a55c95e1de65ec6 Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-03sdm845: Combine BB with QC-Sec for ROM bootT Michael Turney
TEST=build & run Change-Id: I222a56f1c9b74856a1e1ff8132bab5e041672c5d Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25207 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-24util/sconfig: Throw an error if override tree has no devicesFurquan Shaikh
If override tree does not have any device, then the chip info structure in it cannot be associated with the correct device and ends up being added as a standalone chip info structure without any device actually using it. This change prevents this condition by throwing an error during compilation. BUG=b:130342895 Change-Id: I7b8bb6b3228030a465976ca32ce8ef63f41365dd Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-04-23cbfstool: Fix cbfs_file_next_attrPatrick Rudolph
The last attribute was never returned. Fix size compare to retrieve all attributes. Manually tested and seen all attributes, including the last one. Change-Id: I08df073158a0f285f96048c92aa8066fa4f57e6f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-23crossgcc: Update acpica to version 20190215Elyes HAOUAS
Support for ACPI specification version 6.3: Add PCC operation region support for the AML interpreter. This adds PCC operation region support in the AML interpreter and a default handler for acpiexec. The change also renames the PCC region address space keyword to PlatformCommChannel. Support for new predefined methods _NBS, _NCH, _NIC, _NIH, and _NIG. These methods provide OSPM with health information and device boot status. PDTT: Add TriggerOrder to the PCC Identifier structure. The field value defines if the trigger needs to be invoked by OSPM before or at the end of kernel crash dump processing/handling operation. SRAT: Add Generic Affinity Structure subtable. This subtable in the SRAT is used for describing devices such as heterogeneous processors, accelerators, GPUs, and IO devices with integrated compute or DMA engines. MADT: Add support for statistical profiling in GICC. Statistical profiling extension (SPE) is an architecture-specific feature for ARM. MADT: Add online capable flag. If this bit is set, system hardware supports enabling this processor during OS runtime. New Error Disconnect Recover Notification value. There are a number of scenarios where system Firmware in collaboration with hardware may disconnect one or more devices from the rest of the system for purposes of error containment. Firmware can use this new notification value to alert OSPM of such a removal. PPTT: New additional fields in Processor Structure Flags. These flags provide more information about processor topology. NFIT/Disassembler: Change a field name from "Address Range" to "Region Type". HMAT updates: make several existing fields to be reserved as well as rename subtable 0 to "memory proximity domain attributes". GTDT: Add support for new GTDT Revision 3. This revision adds information for the EL2 timer. iASL: Update the HMAT example template for new fields. iASL: Add support for the new revision of the GTDT (Rev 3). More changes in this version at https://acpica.org/node/166 Change-Id: I3a825f568423c3a703ad1c13da976af322ed9de2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-23crossgcc: Update CMake to version 3.14.2Elyes HAOUAS
Release Note : https://cmake.org/cmake/help/v3.14/release/3.14.html "The FindFontconfig module added by 3.14.0 accidentally used uppercase FONTCONFIG_* variable names that do not match our conventions. 3.14.1 revises the module to use Fontconfig_* variable names. This is incompatible with 3.14.0 but since the module is new in the 3.14 series usage should not yet be widespread" Change-Id: Ief7f5e8309597093f061789926bd3bd2ed3aec2d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-04-23crossgcc: Upgrade GCC to version 8.3.0Elyes HAOUAS
Change-Id: I135fd62619fc33bbc3fd29e93eeafcf695700c9a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-04-23Klocwork: Fix the Null pointer derefernce found by klocworkThejaswani Putta
Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com> Change-Id: I15973ac28e9645826986cf63d2160eedb83024e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32290 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23util/intelmetool: Add Intel Cannon Lake PCH HECI Controller to supported PCI ↵Robin Broda
devices Signed-off-by: Robin Broda <robin@broda.me> Change-Id: I0f9e83b3bdf35e3e3e119ffcb93b092121a67666 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-19src/mb/Kconfig: Fix PCI subsystem IDsElyes HAOUAS
References to MAINBOARD_PCI_SUBSYSTEM_{DEVICE_ID,VENDOR_ID} were removed in commits dbd3132 sb/intel/{i82801g/i/j,bd82x6x}: Make use of generic set_subsystem() 00bb441 sb/intel/lynxpoint: Remove PCI bridge function Change-Id: I72bba8406eea4a264e36cc9bcf467cf5cfbed379 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32107 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-17util/docker: Update JRE in coreboot-jenkins-node DockerfileMartin Roth
openjdk-8-jre-headless is no longer available in the debian image we're basing the coreboot-sdk off of. Update it to 'default-jre-headless'. Change-Id: I60f6ecbaedccc0da61f96e0bce4122406ba4bd91 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-04-15util/genbuild_h: Prefer iasl from .xcompile over a hard codePatrick Georgi
build.h provides iasl's version but right now assumes that it's kept in util/crossgcc/xgcc/bin. Often true, but not always, so use the one found in .xcompile to query the version as that's the version that is used in coreboot builds. Change-Id: Iaeedc22e0e14fa96b4f2a68127f405c7f0c9d5cc Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-12util/genbuild_h: Allow operation with older git versionsPatrick Georgi
if git log --no-show-signature is not supported, retry without. Change-Id: I9ee1f8e887cde5e4d6c5e6958f269c62572cdd53 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32299 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-11util/genbuild_h: Do not print PGP verification results in `git log` outputSergey Alirzaev
Signed-off-by: Sergey Alirzaev <zl29ah@gmail.com> Change-Id: I102ecc79bb649a67661c3d22988453dc7741acda Reviewed-on: https://review.coreboot.org/c/coreboot/+/32129 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-11util/inteltool: Swap conditions to prevent uninit readsJacob Garber
Both values in each array are only initialized if `two_channels` is true, so we need to check that first. Found-by: Coverity Scan #1370{584,585,588,589,590-596,600} Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I592bc6ae00f834f74a61668d7a3919014ec635f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-11Documentation: Explain FMAP and FMDHung-Te Lin
The Flashmap (FMAP) was not clearly documented. The new flashmap.md explains where to find more details about that and how / why it was used in coreboot. Also explained what is FMD and how to use it (based on original README.fmaptool). BUG=None TEST=None (only documentation) Change-Id: Ia389e56c632096d7c905ed221fd4f140dec382e6 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-11kconfig_lint: Make uses of CONFIG() on an unknown option an errorJulius Werner
This check had very few false positives which were all easily resolved, and it's unlikely that further false positives will become problematic in the future. On the other hand, it does detect a very severe bug (when you think you're using a Kconfig but you aren't due to a typo), so since warnings are currently not very visible, let's turn this into an error because the pros clearly outweigh the cons for that. Change-Id: I897b5e13d3242fb77b69f0bd3585baa7476aa726 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32257 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-09util/docker: Update coreboot-sdk Dockerfile for new debian imageMartin Roth
libssl1.0-dev is no longer available: - Update to libssl-dev - Add libcrypto++-dev to provide additional crypto libraries not available in libssl-dev. Change-Id: Ie10e14ebf7ae849301302008ee6ffeec1f40ccab Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 12:11:50 +0000