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2012-11-27build system: Split linking into multiple stepsPatrick Georgi
After collecting dependencies for ramstage, add an intermediate step in which object files are linked per directory. The results are then linked into the final binary. This reduces the maximum command line length and might also help with future use of LTO linking. Also adapt the lint test for build dir handling, since printall doesn't provide individual object files for ramstage anymore. Change-Id: Ie40febd8c1eaf4609944eedeab46d870639e53df Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1911 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-27Provide weak empty declarations of all chip_ops used on a boardPatrick Georgi
sconfig creates empty defaults for all chip_ops, which can be overridden by drivers simply by providing a concrete implementation. Change-Id: Ib37515f0b0747bdbf4da780d28690a1e719944b2 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1567 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-27abuild: only rebuild boards if requested or after a broken buildPatrick Georgi
That used to be the behaviour, and it's quite useful to incrementally fix bugs across the tree. Change-Id: I3e30cbdcf01631bc29f892054caa3babb0969beb Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1888 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-27xcompile: Add missing XGCCPATHZheng Bao
XGCCPATH is missing in new xcompile. Change-Id: I177f54189be445404a4a61419064d3c414b8a30c Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1921 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-27 Make xcompile support multiple architecturesRonald G. Minnich
With this change the the xcompile script now creates environment variables for more than one architecture. Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Change-Id: I349a1fd1d865ef16979f1dfd6aeca12b1ee2eed6 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1915 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-11-24crossgcc: update to acpica-20121114Idwer Vollering
Update acpica to release 20121114 and update patches/ to build with this version of acpica. Correct the creation of crossgcc-build.log Bump CROSSGCC_VERSION. Change-Id: I269454ebc3c78b5852e4a67e55bb5642edad191d Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/1861 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-22crossgcc: properly test for flexPatrick Georgi
This is no GNU tool, so testing for "GNU" in the version string is bound to fail. We now accept everything that returns success on "flex --version" and then hope for the best. I tested both cases Change-Id: If325f613fde1648847b998b7e8e5782d0f22b484 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1884 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-17Cleanup sconfigKyösti Mälkki
Fix side-effects of name translation, treat original name as const. Change-Id: Iae26be8cefe7db11eeb8e62fce6f3b8bc9c1f4ed Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/799 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-16buildgcc: Print error if flex is missingStefan Reinauer
flex is needed by acpica. This patch makes the build fail early instead of after gcc has been compiled, if flex is not there. Change-Id: Idfd71bdf704ab25de655f1a72c266c5220b15048 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1860 Reviewed-by: Idwer Vollering <vidwer@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-14nvramtool: fsync for mingw.Zheng Bao
Change-Id: Ifdec69ca46ba8cbd3eb154d8f4af4b3cafa8019d Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1805 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-12cbfstool: Rework to use getopt style parametersStefan Reinauer
- Adding more and more optional and non-optional parameters bloated cbfstool and made the code hard to read with a lot of parsing in the actual cbfs handling functions. This change switches over to use getopt style options for everything but command and cbfs file name. - This allows us to simplify the coreboot Makefiles a bit - Also, add guards to include files - Fix some 80+ character lines - Add more detailed error reporting - Free memory we're allocating Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ia9137942deb8d26bbb30068e6de72466afe9b0a7 Reviewed-on: http://review.coreboot.org/1800 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12cbfstool: Update LZMA encoder to LZMA SDK 9.12Stefan Reinauer
This removes almost all C++ code (except the wrapper) Change-Id: I0f84070e3b6dc57c98d49a53150a140479b3221f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1799 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12cbmem compilation needs to use the hardened toolchainVadim Bendebury
The appropriate compiler (provided by the build system) is used to ensure proper toolchain options are used. cbmem.c is being modified to suppress pointer to integer typecast warnings. Change-Id: Ibab2faacbd7bdfcf617ce9ea4296ebe7d7b64562 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1791 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12ifdtool: Dump more registers from FDStefan Reinauer
Only thing not decoded now are the PCH straps ifdtool -d path/to/image.bin File path/to/image.bin is 4096 bytes Found Flash Descriptor signature at 0x00000010 FLMAP0: 0x02040003 NR: 2 FRBA: 0x40 NC: 1 FCBA: 0x30 FLMAP1: 0x12100206 ISL: 0x12 FPSBA: 0x100 NM: 2 FMBA: 0x60 FLMAP2: 0x00210120 PSL: 0x2101 FMSBA: 0x200 FLUMAP1: 0x000004df Intel ME VSCC Table Length (VTL): 4 Intel ME VSCC Table Base Address (VTBA): 0x000df0 ME VSCC table: JID0: 0x001740ef SPI Componend Device ID 1: 0x17 SPI Componend Device ID 0: 0x40 SPI Componend Vendor ID: 0xef VSCC0: 0x20052005 Lower Erase Opcode: 0x20 Lower Write Enable on Write Status: 0x50 Lower Write Status Required: No Lower Write Granularity: 64 bytes Lower Block / Sector Erase Size: 4KB Upper Erase Opcode: 0x20 Upper Write Enable on Write Status: 0x50 Upper Write Status Required: No Upper Write Granularity: 64 bytes Upper Block / Sector Erase Size: 4KB JID1: 0x001720c2 SPI Componend Device ID 1: 0x17 SPI Componend Device ID 0: 0x20 SPI Componend Vendor ID: 0xc2 VSCC1: 0x20052005 Lower Erase Opcode: 0x20 Lower Write Enable on Write Status: 0x50 Lower Write Status Required: No Lower Write Granularity: 64 bytes Lower Block / Sector Erase Size: 4KB Upper Erase Opcode: 0x20 Upper Write Enable on Write Status: 0x50 Upper Write Status Required: No Upper Write Granularity: 64 bytes Upper Block / Sector Erase Size: 4KB OEM Section: 00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff Found Region Section FLREG0: 0x00000000 Flash Region 0 (Flash Descriptor): 00000000 - 00000fff FLREG1: 0x07ff0180 Flash Region 1 (BIOS): 00180000 - 007fffff FLREG2: 0x017f0001 Flash Region 2 (Intel ME): 00001000 - 0017ffff FLREG3: 0x00001fff Flash Region 3 (GbE): 00fff000 - 00000fff (unused) FLREG4: 0x00001fff Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused) Found Component Section FLCOMP 0x64900024 Dual Output Fast Read Support: supported Read ID/Read Status Clock Frequency: 50MHz Write/Erase Clock Frequency: 50MHz Fast Read Clock Frequency: 50MHz Fast Read Support: supported Read Clock Frequency: 20MHz Component 2 Density: 8MB Component 1 Density: 8MB FLILL 0x000060c7 Invalid Instruction 3: 0x00 Invalid Instruction 2: 0x00 Invalid Instruction 1: 0x60 Invalid Instruction 0: 0xc7 FLPB 0x00000000 Flash Partition Boundary Address: 0x000000 Found PCH Strap Section PCHSTRP0: 0x0820d602 PCHSTRP1: 0x0000010f PCHSTRP2: 0x00560000 PCHSTRP3: 0x00000000 PCHSTRP4: 0x00c8e000 PCHSTRP5: 0x00000000 PCHSTRP6: 0x00000000 PCHSTRP7: 0xc0001ae0 PCHSTRP8: 0x00000000 PCHSTRP9: 0x30000580 PCHSTRP10: 0x00410044 PCHSTRP11: 0x99000097 PCHSTRP12: 0x00000000 PCHSTRP13: 0x00000000 PCHSTRP14: 0x00000000 PCHSTRP15: 0x0000033e PCHSTRP16: 0x00000000 PCHSTRP17: 0x00000002 Found Master Section FLMSTR1: 0x0a0b0000 (Host CPU/BIOS) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: disabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: disabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0000 FLMSTR2: 0x0c0d0000 (Intel ME) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: disabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: disabled Flash Descriptor Read Access: enabled Requester ID: 0x0000 FLMSTR3: 0x08080118 (GbE) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: disabled Host CPU/BIOS Region Write Access: disabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: disabled Host CPU/BIOS Region Read Access: disabled Flash Descriptor Read Access: disabled Requester ID: 0x0118 Found Processor Strap Section ????: 0x00000000 ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff Change-Id: I68a613df2fd80e097cdea46fbad104d7c73ac9ad Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1756 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-12Utility to dump boot timing tableVadim Bendebury
Coreboot and u-boot create a table of timestamps which allows to see the boot process performance. The util/cbmem/cbmem.py script allows to access the table after ChromeOS boots up and display its contents on the console. The problem is that shipping images do not include Python interpreter, so there is no way to access the table on a production machine. This change introduces a utility which is a Linux app displaying the timestamp table. Conceivably the output of this utility might be included in one of the ChromeOS :/system sections, so it was attempted to write this procedure 'fail safe', namely reporting errors and not continuing processing if something goes wrong. Including of coreboot/src .h files will allow to keep the firmware timestamp implementation and this utility in sync in the future. Test: . build the utility (run 'make' while in chroot in util/cbmem) . copy `cbmem' and 'cbmem.py' to the target . run both utilities (limiting cbmem.py output to 25 lines or so) . observe that the generated tables are identical (modulo rounding up of int division, resulting in 1 ns discrepancies in some cases) localhost var # ./cbmem 18 entries total: 1:62,080 2:64,569 (2,489) 3:82,520 (17,951) 4:82,695 (174) 8:84,384 (1,688) 9:131,731 (47,347) 10:131,821 (89) 30:131,849 (27) 40:132,618 (769) 50:134,594 (1,975) 60:134,729 (134) 70:363,440 (228,710) 75:363,453 (13) 80:368,165 (4,711) 90:370,018 (1,852) 99:488,217 (118,199) 1000:491,324 (3,107) 1100:760,475 (269,150) localhost var # ./cbmem.py | head -25 time base 4249800, total entries 18 1:62,080 2:64,569 (2,489) 3:82,520 (17,951) 4:82,695 (174) 8:84,384 (1,688) 9:131,731 (47,347) 10:131,821 (89) 30:131,849 (27) 40:132,618 (769) 50:134,594 (1,975) 60:134,729 (134) 70:363,440 (228,710) 75:363,453 (13) 80:368,165 (4,711) 90:370,018 (1,852) 99:488,217 (118,199) 1000:491,324 (3,107) 1100:760,475 (269,150) Change-Id: I013e594d4afe323106d88e7938dd40b17760621c Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1759 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-12cbfstool: Remove unused cmd_tStefan Reinauer
Change-Id: Ib1c05828258b9dc7107920ae6cb25bc92ffa86d1 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1795 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-12cbfstool: add add-flat-binary command to add raw executablesStefan Reinauer
Example: cbfstool image-link.bin add-flat-binary u-boot.bin fallback/payload \ 0x100000 0x100020 will add u-boot.bin as fallback/payload with a load address of 0x100000 and an entry-point of 0x10002. Change-Id: I6cd04a65eee9f66162f822e168b0e96dbf75a2a7 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1792 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-09ifdtool: Add locking/unlocking and dumping of access permissionsStefan Reinauer
ifdtool will now dump access permissions of system comonents to certain IFD sections: Found Master Section FLMSTR1: 0xffff0000 (Host CPU/BIOS) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0000 FLMSTR2: 0x0c0d0000 (Intel ME) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: disabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: disabled Flash Descriptor Read Access: enabled Requester ID: 0x0000 FLMSTR3: 0x08080118 (GbE) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: disabled Host CPU/BIOS Region Write Access: disabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: disabled Host CPU/BIOS Region Read Access: disabled Flash Descriptor Read Access: disabled Requester ID: 0x0118 Also, ifdtool -u /path/to/image will unlock the host's access to the firmware descriptor and ME region. ifdtool -l /path/to/image will lock down the host's access to the firmware descriptor and ME region. Change-Id: I3e081b80a9bcb398772416f143b794bf307b1c36 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1755 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-11-09Fix abuild output in JenkinsStefan Reinauer
Ignore the harmless broken pipe messages from "yes" Building amd/pistachio; i386: ok, using i386-elf-gcc Using payload /srv/jenkins/payloads/seabios/bios.bin.elf Creating config file... (blobs, ccache) yes: standard output: Broken pipe yes: write error ok; Compiling image on 4 cpus in parallel .. ok. (took 10s) Change-Id: Ic53e246aac3ab6d7ea7a006a8dfac1c3f85797bc Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1813 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-09Fix Segmentation Fault in ifdtoolStefan Reinauer
If a section is bigger than the FD file it is injected into, and the FD lies about the size of the FD file, ifdtool would crash because reading in the section writes beyound the FD file in memory. Change-Id: Idcfac2b1e2b5907fad34799e44a8abfd89190fcc Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1754 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-08Add utility for parsing/modifying DTD arrayVadim Bendebury
Detailed timing descriptor (DTD) is an 18 byte array describing video mode (screen resolution, display properties, etc.) in Intel Option ROM. Option ROM can support multiple video modes, specific mode is picked by the BIOS through the appropriate Option ROM callback function. The new utility allows to interpret the 18 byte hex DTD dump, and/or modify certain values, and generate a new DTD. To parse the DTD contents just pass the 18 bytes to the utility in the command line. To modify the existing contents and generate a new dump precede the 18 bytes with '-m' and follow prompts. Change-Id: Ib00bdaf42c350b98b5a48d08e6bb347b5ec25a8b Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1711 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-08Get more informative output from cbmem.pyVadim Bendebury
This is a cosmetic change which formats timestamp information retrieved by cbmem.py. Instead of printing timestamps in a single line, print them one per line and add time (in us) elapsed since the previous timestamp. time base 4149594, total entries 18 1:56,928 2:58,851 (1,923) 3:175,230 (116,378) 4:175,340 (109) 8:177,199 (1,859) 9:214,368 (37,168) 10:214,450 (81) 30:214,462 (11) 40:215,205 (743) 50:217,180 (1,974) 60:217,312 (132) 70:436,984 (219,671) 75:436,993 (8) 80:441,424 (4,431) 90:442,487 (1,062) 99:553,777 (111,289) 1000:556,513 (2,736) 1100:824,621 (268,107) Change-Id: I0d25cafe766c10377017697e6b206276e1a92992 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1716 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-08Fix cbmem to work on 64 bit platformsVadim Bendebury
For some reason which I fail to understand, specifying endiannes using '@' (which means 'native' and should be the same as '<' on x86 platforms) causes cbmem.py to crash the machine on 64 bit systems. What happens is that the addresses read from various table headers' struct representations do not make sense, when bogus address gets passed to get_phys_mem, the crash happens while that function is executed. dlaurie@ found out that replacing "@" with "<" in fact fixes the issue. After some investigation I am just submitting this fix without much understanding of the root cause. Change-Id: Iaba9bc72a3f6b1d0407a5f1e3b459ccf5063969d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1715 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-08cbfstool: add offset parameter to create commandStefan Reinauer
CBFS allows coreboot rom images that are only partially covered by the filesystem itself. The intention of this feature was to allow EC / ME / IMC firmware to be inserted easily at the beginning of the image. However, this was never implemented in cbfstool. This patch implements an additional parameter for cbfstool. If you call cbfstool like this: cbfstool coreboot.rom create 8192K bootblock.bin 64 0x700000 it will now create an 8M image with CBFS covering the last 1M of that image. Test: cbfstool coreboot.rom create 8192K bootblock.bin 64 0x700000 creates an 8M image that is 7M of 0xff and 1M of CBFS. Change-Id: I5c016b4bf32433f160b43f4df2dd768276f4c70b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1708 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-07cbfstool: respect dependencies when building locallyStefan Reinauer
cbfstool was not looking at any dependencies when building by running make in util/cbfstool. By fixing this it's not required to make clean every time you edit a file in there. Change-Id: I544fd54d4b9dd3b277996c21ade56dc086b84800 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1707 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-06Drop redundant CHIP_NAME in mainboard.cKyösti Mälkki
Compose the name from Kconfig strings instead. As the field is for debug print use only, a minor change in the output should do no harm. The strings no longer include word "Mainboard". Change-Id: Ifd24f408271eb5a5d1a08a317512ef00cb537ee2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1635 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-02crossgcc: build expat and python in silenceIdwer Vollering
Don't let expat and/or python show the compile process on stdout. Instead direct this output to crossgcc-build.log. Fix the logfile path for python. Change-Id: I431dabf6955d7eef3e54c96d0fb11b92d1cee96d Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/1667 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-27inteltool: Add output of 64bit registers in PMBASENico Huber
Output values of 64bit registers and fix settings for GPE0_EN for ICH9/10. Change-Id: I8ca6b32500331707670972b38466345f581844cd Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1625 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-27crossgcc: update to Python 2.7.3Idwer Vollering
Change-Id: I9db10e8c7dcd693cc4ab935c587da02dd7eb2bc5 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/1621 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-27crossgcc: update to expat 2.1.0Idwer Vollering
Change-Id: Id0b736d402b33138e27b18c74e5ed8ffab0bcccb Signed-off-by: Idwer Vollering <vidwer@gmail.com> Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/1620 Tested-by: build bot (Jenkins)
2012-10-26crossgcc: update mingw w32api's download URLIdwer Vollering
Correct the download URL of mingw's w32api. Change-Id: I98fb43c121399c23f6693ade5cd3b42bc9463724 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/1619 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-26buildgcc: redirect error output to /dev/nullZheng Bao
Change-Id: I7cd63248eb8abb711cecce41e3f8a282b34aa126 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1548 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-10-26crossgcc: update to mingwrt 3.20-2Idwer Vollering
This patch updates crossgcc to download and compile mingwrt 3.20-2 Change-Id: Ic5ed2df4c3643e469a62c51643d3fc756eb3e615 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/1617 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2012-10-25crossgcc: update to binutils 2.23Idwer Vollering
This patch updates crossgcc to download and compile binutils 2.23 Change-Id: I75a24ce6fb9f6ac7ae53671314c410b9b0d80aa8 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/1615 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-25crossgcc: update to MPC 1.0.1Idwer Vollering
This patch updates crossgcc to download and compile MPC 1.0.1 Change-Id: I7a2a21afc8c26e4fb7b6553c7fd98cc054d01570 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/1614 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-25crossgcc: update to MPFR 3.1.1Idwer Vollering
This patch updates crossgcc to download and compile MPFR 3.1.1 Change-Id: I6c479db5d6d632dcc2201c3771b43e2b663877e1 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/1613 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-25crossgcc: update to GDB 7.5Idwer Vollering
This patch updates crossgcc to download and build GDB 7.5 Change-Id: I38fc3591396f072ead399b22f516ec765480ea40 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/1612 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-25crossgcc: update to gcc 4.7.2Idwer Vollering
Update crossgcc to use gcc 4.7.2. This requires a minor change to util/crossgcc/buildgcc as well. Tested on hardware with asus/p2b and lenovo/x60. Change-Id: Ia3921844670ca99741e5715def14dd969f305ab7 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/1609 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-25crossgcc: fix compilation of acpicaIdwer Vollering
Compilation of acpica-20120420 is broken (and old, but I'll take care of that in a future patch), let's fix that ("Building IASL 20120420 ... failed"). Change-Id: If5fd5cd93d748f78b7c059323f9f810666e32cc7 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/1607 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-23kconfig: Some terms or curses libraries treat backspace as 0x08Zheng Bao
Change-Id: Ie4e4a2f0d68643a8f46d24ee7bd1b953e9fe14a5 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1605 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-22build: build coreboot on mingw.Zheng Bao
regex, pdcurses, wsock(for itohl) are seperated libraries. mmap and unmmap are ported from git. Issues: 1. The length of command line is limited. That makes the Thather can not be built because too many obj.o need to be built. Change-Id: I1d60ec5c7720c1e712e246c4cd12e4b718fed05f Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1604 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-10-22cbfstool: Add -mno-ms-bitfields on (mingw)Zheng Bao
The default gcc on mingw will process the __attribute__ ((packed)) in a different way other than non-win system. Change-Id: Iac9f4476c922472d0b447f1c3ef60e8e13bd902f Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1603 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-10-19inteltool: improve the libpci test in the MakefileStefan Tauner
Use the verbatim variable method to define and export test code and the actual libpci test from flashrom. This improves readability and will work with stricter compiler (settings). Change-Id: Iace7d53b0b992c4fde596ce1d606ad715d6dfc2a Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/1575 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-19inteltool: add support for 946GZ and 946PLStefan Tauner
Change-Id: Ied0ff16c16d8c2f04b55fe6b0a6ee38966d3c424 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/1576 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-10-19inteltool: new definitions and cleanupStefan Tauner
- Separate host bridges/DRAM controllers from LPC controllers in supported_chips_list[]. - Refine some names and macros. - Clean up some whitespace errors. - Add IDs and names of 5, 6 and 7 Series southbridges and the three latest Core CPU families with integrated memory controllers but do not implement any pretty printing routines for them yet. The first generation Core family is already supported, although it was wrongly named after the PCH and used the wrong ID. Also, the BAR values have been mangled to 32b instead of 64b. Both errors have been fixed and most basic support for the other two generations was added. Change-Id: Ief81e57f7c065cafac52e48b6364b57c72fcdf95 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/1574 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-10-14inteltool: remove bashism from MakefileStefan Tauner
&> is a bashism to redirect both outward streams (stdout and stderr), but with other shells this introduces a race condition with the rm command after it, because the compiler execution is done in the background/ in parallel. Found and tested with dash. Change-Id: I08516494828c9f7af168f954f2df027372657867 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/1573 Tested-by: build bot (Jenkins) Reviewed-by: Bernhard Urban <lewurm@gmail.com> Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-14crossgcc: Allow the non-gnu tar and patch work on XxxBSDZheng Bao
For BSD, patch and tar are not default GNU. Add a work around to let the non-gun patch and tar work. Change-Id: I0a9d0bb0e535aa5e0dde146db330c3c8d7b4d8cb Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1502 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-14abuild: allow building with no payloadPatrick Georgi
Change-Id: I167f0bb57bb40f0426182c0abe868bdad58eb120 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1563 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-08Every chip must have chip_operationsKyösti Mälkki
Forcing this rule, chip_ops can be added in the static devicetree regardless of the existence of the chip.h files. Change-Id: Iec1c23484e85cab3f80a34f2b082088f38ac4de9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1472 Tested-by: build bot (Jenkins)
2012-10-05lint: Get absolute path in compare_outputZheng Bao
The classes in $(top)/Makefile uses $(abspath) to get the path. The $(abspath) can not resolve symlink. If the coreboot is located in a symlink directory, the run_printall produces the absolute path while the $PWD just produces the path with symlink. Use `pwd -P` to get the abs path. Change-Id: Icf6b364d030c14a9c78991767b17dafc701baf3c Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1551 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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