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2020-08-28util: volteer/dedede: move generic SPDs to common locationNick Vaccaro
Now that generic SPD files have the memory type prepended to the filename, they can be stored in the same location. This CL moves the generic SPDs to the new location. Change the ddr4 gen_part_id.go and gen_spd.go tools to use "ddr4_spd_manifest.generated" instead of "spd_manifest.generated". Change the lpddr4x gen_part_id.go and gen_spd.go tools to use "lp4x_spd_manifest.generated" instead of "spd_manifest.generated". Move TGL DDR4 and LPDDR4x generic SPDs into a common location. Move JSL DDR4 and LPDDR4x generic SPDs into a common location. Change the volteer/spd/Makefile.inc to use the new path for the spds. Change the dedede/spd/Makefile.inc to use the new path for the spds. BUG=b:165854055 TEST="emerge-volteer coreboot" and verify all variants build correctly. Change-Id: I83b088cb718d15ffd3012c84a12b5231ae84a3e4 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44648 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-27util: Add check for duplicate entries in mem parts jsonRob Barnes
Check for duplicate entries in mem parts json file. BUG=b:162939176 TEST=Verified that tool throws error when there is a duplicate. Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I7c638c7938958727cfc832e7b4556acbc04b0ca4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44478 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-27util: Add Picasso and Pollock platforms to spd_toolsRob Barnes
PCO = Picasso PLK = Pollock BUG=b:162939176 Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I43b74f68871062112f53fbbef8a170db53734b3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/44477 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-27util/spd_tools: Support comments in jsonRob Barnes
Allow comments in json file for better documentation. Comments must be on seperate line. BUG=none TEST=Injest global_ddr4_mem_parts.json.txt with comments Change-Id: I51295408d4f916708e4ed5bc42d5468ccdc68a6b Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-27util/spd_tools: Remove intel subfolderRob Barnes
Move ddr4 and lp4x to spd_tools root folder. The tool now applies to non intel platforms. BUG=b:162939176 TEST=Run tool Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I0941ea036d760ee27eb34f259f4506a4b7584bee Reviewed-on: https://review.coreboot.org/c/coreboot/+/44844 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-25util: update lp4x gen_part_id tool to include memory typeNick Vaccaro
Add "MEMORY_TYPE = lp4x" to the generated Makefile.inc to indicate this is lpddr4x memory and to use the generic SPDs from the lpddr4x respository of SPDs. BUG=b:160157545 TEST=run gen_part_id for volteer and verify that it adds the line "MEMORY_TYPE = lp4x" to the makefile produced. Change-Id: I416690ae8aff8052474b16ef0d3e940e72e6a2fb Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-25util: Add spd_tools to generate DDR4 SPDs for TGL boardsNick Vaccaro
Serial Presence Detect (SPD) data for memory modules is used by Memory Reference Code (MRC) for training the memory. This SPD data is typically obtained from part vendors but has to be massaged to format it correctly as per JEDEC and MRC expectations. There have been numerous times in the past where the SPD data used is not always correct. In order to reduce the manual effort of creating SPDs and generating DRAM IDs, this change adds tools for generating SPD files for DDR4 memory used in memory down configurations on Intel Tiger Lake (TGL) based platforms. These tools generate SPDs following JESD79-4C and Jedec "4.1.2.L-5 R29 v103" specification. Two tools are provided: * gen_spd.go: Generates de-duplicated SPD files using a global memory part list provided by the mainboard in JSON format. Additionally, generates a SPD manifest file (in CSV format) with information about what memory part from the global list uses which of the generated SPD files. * gen_part_id.go: Allocates DRAM strap IDs for different DDR4 memory parts used by the board. Takes as input list of memory parts used by the board (with one memory part on each line) and the SPD manifest file generated by gen_spd.go. Generates Makefile.inc for integrating the generated SPD files in the coreboot build. BUG=b:160157545 Change-Id: I263f936b332520753a6791c8d892fc148cb6f103 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-24crossgcc: Upgrade MPC to version 1.2.0Elyes HAOUAS
Change-Id: I8b754c2bbb18e38d2f8619f6ac8e1544702836ee Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44551 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24util/abuild: Don't pass kconfig output through headPatrick Georgi
Closing stdout early seems to have a detrimental effect on kconfig on a system under high load (e.g. when doing lots of builds in parallel). Change-Id: I6987f1deac596124c7b397bf7bc5a78d691cc538 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-08-24util/abuild: Delete temporary config in failure casePatrick Georgi
Change-Id: I9b6e6b6dcfbf2b1f43c98027acae8d9af61bd6d8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44624 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-21util/amdfwtool: Refactor APOB_NV requirementsMartin Roth
amdfwtool currently assumes that we MUST have an apob_nv area if we have an aopb. This is not required, so if neither the apob_nv size or base are specified, just move on. BUG=b:158363448 TEST=Build an image with no APOB_NV region. Dump regions to show that it's not there. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ibaeacd3dcdfd73f690df61c2a19d39bbb9dcc838 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44045 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-19util/abuild: Avoid another git submodule invocationPatrick Georgi
.xcompile is generated before the submodules handling, but there's no need for the submodules to be around, so skip here, too. Change-Id: I60205f65b124a09067de5ae50f066b5cf64733f2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-08-18crossgcc: Upgrade LLVM to version 10.0.1Elyes HAOUAS
Change-Id: I1d96654fd66a5972c6c5cc24311ca2d889866331 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39921 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-18crossgcc: Upgrade CMake to version 3.18.1Elyes HAOUAS
Release Notes: https://cmake.org/cmake/help/v3.18/release/3.18.html Change-Id: I20b75b7c29be838c3c168547bcab25ea5c1af462 Signed-off-by: Griffin98 <griffin98@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-08-18util/intelp2m: Add support for Cannonlake-LP SoCsMatt DeVillier
Add support for Cannonlake-LP SoCs (Whiskeylake-U, Coffeelake-U, Cometlake-U) as a separate parsing profile, copying the existing 'Sunrise' profile and adjusting for differences in reset mapping and GPIO macro generation Test: convert inteltool GPIO log dump into coreboot macros for an out-of-tree CML-U board. Change-Id: I86296697ee892af7aa0818fb608b6d68fad2f307 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-08-17crossgcc: Enable GCC to get asan shadow offset at runtimeHarshit Sharma
Unlike Linux kernel which has a static shadow region layout, we have multiple stages in coreboot and thus require a different shadow offset address. Unfortunately, GCC currently only supports adding a static shadow offset at compile time using -fasan-shadow-offset flag. For this reason, we enable GCC to determine asan shadow offset address at runtime using a callback function named __asan_shadow_offset(). This supersedes the need to specify this address at compile time. GCC then makes use of this shadow offset to protect stack buffers by inserting red zones around them. Some other benefits of having this GCC patch are: a. We can place the shadow region in a separate linker section with all its advantages like automatic fit insurance. This ensures if a platform doesn't have enough memory space to hold shadow region, the build will fail. (However, if we use a fixed shadow offset on a platform that actually doesn't have enough memory, it may still build without any errors.) b. We don't modify the memory layout compared to the current one, as we are placing the shadow region at the end of the space already occupied by the program. c. We can be much more flexible later if needed (thinking of other stages like bootblock). d. Since we are appending the shadow buffer to the region already occupied, we make efficient use of the limited memory available which is highly beneficial when using cache as ram. Further, we have made sure that if you compile you tree with ASan enabled but missed this patch, it will end up in the following compilation error: "invalid --param name 'asan-use-shadow-offset-callback'" So, you cannot accidentally enable the feature without having your compiler patched. Change-Id: I401631938532a406a6d41e77c6c9716b6b2bf48d Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-08-17crossgcc: Upgrade IASL to version 20200717Elyes HAOUAS
Summary of changes: https://acpica.org/node/183 Change-Id: Ib325fa5c37c32702c572ab56c99e1f8f785cbe53 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-08-17crossgcc: Upgrade Python to version 3.8.5Elyes HAOUAS
Change-Id: I660994ece28f04d97de2fe3a074ebcf93fb4d2f4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39148 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17crossgcc: Upgrade nasm to version 2.15.03Elyes HAOUAS
Change-Id: I4b38595cef72053f82216df43f3667abed4c1989 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42855 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17crossgcc: Upgrade binutils to version 2.35Elyes HAOUAS
Using "MAKEINFO = @MAKEINFO@", it fails to compile, so binutils-2.35_no-makeinfo.patch will change that to "MAKEINFO = true" Change-Id: I0ad01e5da34c96fee6a9b1a63897a9fb28471c75 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38666 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17crossgcc: Update MPFR to version 4.1.0Elyes HAOUAS
Changes: https://www.mpfr.org/mpfr-current/#changes Change-Id: I1df2c952229056b44d4c618cebe774ea27b55bd1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43360 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17crossgcc: Upgrade GMP to v6.2.0Elyes HAOUAS
gmp_freebsd-configure.patch is integrated in upstream so we don't need it anymore. Changes: https://gmplib.org/gmp6.2 Change-Id: I8404872f1b65e9173c1fcbd24d7da7bdd7937503 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38465 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-01util/ifdtool: Add Alderlake platform support under IFDv2Subrata Banik
Change-Id: Ief8ab6ad280d8a2625404c19d57cd2a24f23cf13 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39533 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-01util/ifdtool: Make JSL platform entry for lock_descriptorSubrata Banik
Change-Id: Ia2ddb4eceab29810b22766a0f241ba4b11e79538 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44057 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-29util/apcb: Strip SPD manufacturer informationRob Barnes
Strip manufacturer information from SPDs before injecting into APCB. This allows more flexibility around changing DRAM modules in the future. BUG=b:162098961 TEST=Boot, dump memory info Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I1bbc81a858f381f62dbd38bb57b3df0e6707d647 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-28util/intelp2m: Add Intel Pad to Macro utilityMaxim Polyakov
This patch adds a new utility for converting a pad configuration from the inteltool dump to the PAD_CFG_*() macros [1] for coreboot and GPIO config data structures for FSP/sdk2-platforms/slimbootloader [2,3]. Mirror: https://github.com/maxpoliak/pch-pads-parser.git [1] src/soc/intel/common/block/include/intelblocks/gpio_defs.h [2] https://slimbootloader.github.io/tools/index.html#gpio-tool [3] 3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Include/GpioSampleDef.h Change-Id: If3e3b523c4f63dc2f91e9ccd16934e3a1b6e21fa Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35643 Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28intelvbttool: Fix some typos in error messagesPeter Lemenkov
Change-Id: Id6298883c39c21179b13696dab630818b81026ff Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43905 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-27util/lint/Kconfig_lint: Update Naked BOOL reference to errorMartin Roth
The lint-stable makefile target only watches for errors in the Kconfig file, so has not protected additional "Naked" references to BOOL type Kconfig symbols from entering the tree. Update it to an error so that they can't continue coming into the codebase. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Icce2a9a627c4fbcaa220df18474cb8bfea8b2a8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/43826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26util/inteltool/gpio_names: Make group and community titles consistentBenjamin Doron
Consistency is good for scripting and automation. The lowercase "group" in Sunrise Point-LP, for example, was breaking pattern matching used in intelp2m. Change-Id: Iffa8a8ac9c17c5cbd8d7b838d9c703cae6a858b5 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43068 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26mb/lenovo: Prepend EC event number with 0x to denote hex notationPaul Menzel
Currently, the message below is printed, suggesting it’s decimal notation: coreboot-4.12-1530-g7acbd5fc45 Sun Jul 19 07:47:58 UTC 2020 smm starting (log level: 7)... EC event 48 GPI (mask 1000) Prepend 0x, so it’s clear it’s hexadecimal notation. EC event 0x48 Use the command below change all places: git grep -l 'EC event %02x' | xargs sed -i 's/EC event %02x/EC event %#02x/' Change-Id: I8d1e6434a0e550c5a19576f9f7fea05e7a812e49 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26util: Remove extra newlines in log messagesRob Barnes
Print adds a newline implicitly. Simply remove the extra newlines. BUG=None TEST=Build zork, observe build log Change-Id: Idb150c12c90719ba1465e7e7fe45c26d456e2a1c Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43786 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26autoport: Don't initialize already initialized fields in acpi_tablesPeter Lemenkov
Don't initialize fields with zeroes since gnvs structs were zeroed out in southbridge already. Also add some comments. See also these commits: * Commit a76cf28 with Change-Id I2ccf4699ba3ed3f5b9402c0340153d4a5bf82682 ("mb/lenovo/*/acpi_tables: Don't initialize already initialized fields"). * Commit 0c52638 with Change-Id I71f092ed7582b4931122d72f41d0b42a7569b96e ("mb/lenovo: Remove thermal.h header"). Change-Id: I1a0042bc93a2b30babcb896b3df23faf37998f3c Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40479 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26util/lint: Add lint and checkpatch coverage for tests/ dirJan Dabros
Signed-off-by: Jan Dabros <jsd@semihalf.com> Change-Id: I8018b75844e630c9ed46c8bc48f2aa1634bf3369 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-07-26util/amdfwtool: Add support for EFS SPI values for F17h and F15hMatt Papageorge
The Embedded Firmware Structure contains various SPI parameters for the PSP to program. This change adds support to amdfwtool for populating these values as well specifying SOC Family and Model. BUG=b:158755102 TEST=Read EFS values at appropriate offsets using a hex editor. Boot test on Tremblye and Morphius. Change-Id: I87c4d44183ca65a5570de5e0c7f9b44aa6dd82f9 Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42566 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26*/mb/google/volteer/**/gpio.h: Fix up license headerAngel Pons
There's a `GPL-2.0-or-later` version of this file in volteer2, so use it in place of these weirdly-licensed files. Change-Id: Icde2f6539d9c726d6967350f74e7bc015e01e7b5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-07-25autoport/bd82x6x.go: Remove generated extra lineElyes HAOUAS
Change-Id: I48125b7efd599b6a6718d7353156217df874d490 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-24util/mb/google/volteer: Delete dptf.aslTim Wawrzynczak
Since we are not using raw ASL files anymore for DPTF, delete the template file too, so that it does not keep getting added for new board variants. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia128989c64b8c02759c326431b4ee30fd2b483e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-21inteltool/gpio: Add support for new Lewisburg chipsetsMaxim Polyakov
- Add SKUs and Super SKUs of new Lewisburg series chipsets: C621A, C627A, C629A [1]. - These changes allow the utility to generate the GPIO config registers dump. [1] https://review.coreboot.org/c/coreboot/+/40395 Change-Id: I9b63c0a3860a901e58af0c0d5184361661bab5e3 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43534 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21util/inteltool: add missing L0 and L1 pads for LewisburgMaxim Polyakov
The description for L0 and L1 was missed in the datasheet, however, configuration registers for these pads are present. In addition, the chipset contains the "GPP_L0/CSME_INTR_IN" and "GPP_L1/CSME_INTR_OUT" pads in a circuit diagram. Use all available information to add a description for the missed pads. Change-Id: I7a0488c26b3df9de1adc037d94ae290837d65dd8 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40044 Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15util/mb/google: add template files for dalboz and trembylePaul Fagerburg
Now that Zork is using upstream coreboot, we need the template files in the main branch. BUG=b:157570490 TEST=n/a Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Change-Id: I6cab4ab0b414473e0a759dce81df9872a40d3f26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43419 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15util/board-status: Reject logs with unknown timestampsPaul Menzel
Check the output of `cbmem -t` for unknown timestamps. If present, ask the user to rebuild `cbmem`. Change-Id: Ief7aa1a698f10d9721964ad1bee057fcd9f4aa40 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-15util/intelmetool: Fix error messageEvgeny Zinoviev
Add a missing space to the message. Change-Id: I7d4042ebb587af8558294fb4961100b43910fd4a Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-07-09util/inteltool: add PCI ID for ICH10DOIdwer Vollering
Change-Id: I3561679ef50f4c094d2503539074c957f759ecef Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43321 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08util/xcompile: Look for the host compiler in XGCCPATH, too (and first)Patrick Georgi
If there's a host compiler in XGCCPATH, it's likely the same relatively-current version we use for coreboot, and it's a well-known quantity, so let's prefer that over alternatives by default. In addition, look for the C++ host compiler as well. Change-Id: If50341df169a476899b5a5ffd4c4fb6d21c3f4ac Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43144 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07util/crossgcc: Always bootstrap for gcc < 4.9Patrick Georgi
Building cbfstool requires at least 4.9 due to optimizer bugs in gcc 3.x to 4.8.x, so let's not work around ancient compilers in our tree but ensure that users get a newer compiler. Closes: https://ticket.coreboot.org/issues/240 Change-Id: I4e0f80e2790514e6a1b5d5de1a373f365df1569c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43143 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07util/inteltool: Support dumping more BARs on Skylake mobile SoCsBenjamin Doron
Support dumping MCHBAR, EPBAR, DMIBAR and PCIEXBAR on SKL-U/Y. These chipsets are similar to others supported by the tool. Working on SKL-U. Change-Id: Ic43d54ef189d500701872a56e67781a744990328 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-07lp4x: Add new memory parts and generate SPDsDavid Wu
This change adds the following memory parts to LP4x global list and generates SPDs using gen_spd.go for TGL: 1. MT53E512M64D4NW-046 WT:E 2. MT53E1G64D8NW-046 WT:E BUG=b:159195585,b:152936481,b:156435028 TEST=build. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: If69087e5e189b3e0f70e5f1afbfe3f884173d3b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-07-06pgtblgen: Update comment to match what the code doesPatrick Rudolph
Change-Id: Ib87c804b139a96a4173a6f392f0f99a77d32fc01 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-07-06devicetree: Remove weak declarations for opsKyösti Mälkki
Make it compulsory to build with all the drivers that are visible in the board devicetree.cb file. Change-Id: Ifb783e2f733d5c65c615e5c1879e3e4c7a83e049 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-03util/tmpl/puff: Allow USB2/3 wakeups to (un)plug eventsEdward O'Callaghan
BUG=b:159187889 BRANCH=none TEST=none Change-Id: Ib59108ec42955b5414f76b591cce5073f7dad1a9 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42990 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-31 12:20:58 +0000