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2013-07-08msrtool: Fix verbose ignored by cpuid().Benoît Legat
This is a trivial patch moving cpuid() call after reading argv so that verbose is set. Change-Id: Ic621191ef650495614a041413c1a0f707d4469e6 Signed-off-by: Benoît Legat <benoit.legat@gmail.com> Reviewed-on: http://review.coreboot.org/3627 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-01cbmem: Fix makefileStefan Tauner
The .dependencies rule did not use the CPPFLAGS variable which led to funny behavior: a spurious termination message the first time (after checkout/make distclean) one executes make. Afterwards the (wrongly) empty .dependencies file hides the problem and the binary is created anyway. $ make cbmem.c:37:34: fatal error: boot/coreboot_tables.h: No such file or directory compilation terminated. cc -O2 -Wall -Werror -iquote ../../src/include -iquote ../../src/src/arch/x86 -c -o cbmem.o cbmem.c cc cbmem.o -o cbmem $ make make: Nothing to be done for `all'. $ make clean rm -f cbmem *.o *~ $ make cc -O2 -Wall -Werror -iquote ../../src/include -iquote ../../src/src/arch/x86 -c -o cbmem.o cbmem.c cc cbmem.o -o cbmem $ make distclean rm -f cbmem *.o *~ rm -f .dependencies $ make cbmem.c:37:34: fatal error: boot/coreboot_tables.h: No such file or directory compilation terminated. cc -O2 -Wall -Werror -iquote ../../src/include -iquote ../../src/src/arch/x86 -c -o cbmem.o cbmem.c cc cbmem.o -o cbmem I fixed that by adding the CPPFLAGS variable to the .dependencies recipe, just like Stefan Reinauer did in Chromium (Ia9d2e10a3ef122f30d681d16c2291eb108ead835), hence the split sign-off for this tiny change. :) Change-Id: Icd11b146ad762cbdf9774630b950f70e1253a072 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/3548 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-06-25abuild: Add xgcc tools to the pathMarc Jones
abuild checks the path for toolchains prior to building a mainboard. It didn't check xgcc/, which would be picked up by the coreboot make, and fail to build when it shouldn't. Change-Id: If0ca4238e8c57a6b015fdad623ccdbf237ef1ba6 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/3350 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-24ifdfake - Create an IFD with just a section layoutNico Huber
This new tool called `ifdfake` just creates an empty Intel Firmware Descriptor (IFD) and writes the IFD signature plus the section layout given on the command line. usage: ifdfake [(-b|-m|-g|-p) <start>:<end>]... <output file> -b | --bios <start>:<end> BIOS region -m | --me <start>:<end> Intel ME region -g | --gbe <start>:<end> Gigabit Ethernet region -p | --platform <start>:<end> Platform Data region -h | --help print this help <start> and <end> bounds are given in Bytes, the <end> bound is inclusive. All regions must be multiples of 4K in size and 4K aligned. The descriptor region always resides in the first 4K. An IFD created with ifdfake won't work as a replacement for a real IFD. Never try to flash such an IFD to your board! The output of ifdfake can be utilized to build an image with just the later added sections (like coreboot itself) being valid. The resulting image can then be partially written to a machines flash ROM to just update coreboot (i.e. the BIOS section). Change-Id: I925b47cab5c6d490a79d684bdd7a7a45ac442640 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3523 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-24AMD: Drop empty root_complexKyösti Mälkki
There are no files to build left under AMD nortbridge/x/root_complex directories. For some cases, even the Kconfig file was no longer sourced. Remove all such references and empty files. For devicetree.cb treat component paths with "/root_complex" in them valid even when the directory does not exists. This is because AMD boards us this dummy chip component as the root node in their devicetree.cb. The generated devicetree file static.c remains unchanged. Change-Id: I9278ebb50a83cebbf149b06afb5669899a8e4d0b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3434 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-23inteltool: add initial support for NehalemStefan Tauner
Also, add pretty printing of Westmere's DMI registers (tested on my t410s by staring at non-zero output values :) Apparently Nehalem does not have a MEMBAR? But there are some documented memory controller control registers in PCI configuration space... left out for now. The PCIEXBAR is not documented publicly AFAICT, but there is a similar register on a device on bus 0xFF. phcoder might know more... Change-Id: I5faadb6e4f701728f5290276c02809b4993bd86d Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/3505 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-13util/inteltool: Add support for other 5 chipsetsStefan Tauner
e4e8e090fa36cb3a098e1ddf0ea44c796c140572 does add support for QM57, but there are many more that should work with that code(?). Does not explode on... CPU: Processor Type: 0, Family 6, Model 25, Stepping 2 Northbridge: 8086:0044 (1st generation (Westmere family) Core Processor) Southbridge: 8086:3b0f (QS57) Change-Id: I85e15ba45678a5bd635415a7a8d69c05bff8f7ef Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/3321 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-06-12Add spkmodem receiverVladimir Serbinenko
This is spkmodem receiver counterpart. Change-Id: Id27d32608502029fb6fcc8154f508811bf5ca77b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/3411 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-09buildgcc: Re-add some break statementsPatrick Georgi
While some of the case .. break statement actually weren't needed, too are, since otherwise the option parsing loop hangs. Exit conditions for that endless loop: "--" or no more arguments, in line with GNU command line parsing rules. Change-Id: I0dbc35e530fb8c93a0f7de05ac47f325555ad4a4 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/3418 Tested-by: build bot (Jenkins) Reviewed-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
2013-06-06Intel Atom cpu support to msrtoolOlivier Langlois
Added support for Intel Atom cpu to msrtool Fixed a cut&paste error in nehalem msr bits definition It has been tested with a N455 cpu and msrtool output can be review at: http://www.trillion01.com/coreboot/msrtool_atom.txt Change-Id: I0ecf455b559185e2d16fa1a655bf021efc2ef537 Signed-off-by: Olivier Langlois <olivier@olivierlanglois.net> Reviewed-on: http://review.coreboot.org/3351 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-04viatool: Add utility to read various configuration bits on VIA systemsAlexandru Gagniuc
viatool is a utility for extracting useful for extracting certain configuration bits on VIA chipsets and CPUs. It is a fork of inteltool. viatool is currently focused on "quirks". Quirks are device configurations that cannot be accessed directly. They are implemented as hierarchical configurations in the PCI or memory address spaces (index/data register pairs). Such configurations refer to hardware parameters that are board specific. Those parameters would otherwise be difficult to extract from a system running the vendor's firmware. viatool also preserves inteltool's MSR dumps. VIA CPU and Intel CPU MSRs are nearly identical. Change-Id: Icbd39eaf7c7da5568732d77dbf2aed135f835754 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/1430 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04superiotool: Add dump facility for HWM of W83627DHG-PNico Huber
Change-Id: I9355996a8cf1b7cb91cc415ec04f5108a1cc42a5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3358 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-04superiotool: Add dump facility for ITE IT8516 + I/O 0x20e/fNico Huber
Change-Id: Iaea08b7eb5aac9ff1e0756f1400a82641bb45b14 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3359 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-04crossgcc/buildgcc: Remove unneeded 'break' statementsDavid Hubbard
Bash case statements are terminated with ';;'. Unlike C, bash case statements will not continue to the next case. No 'break' is needed. Change-Id: I62e7e91f3223ac4052728a1ca12a4681af0dc036 Signed-off-by: David Hubbard <david.c.hubbard+coreboot@gmail.com> Reviewed-on: http://review.coreboot.org/3330 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-03util/cbmem: Fix format string in cbmem.cNico Huber
Use PRIx64 to print a u64 instead of "llx". Fixes the following error: cbmem.c: In function 'parse_cbtable': cbmem.c:135:2: error: format '%llx' expects argument of type 'long long unsigned int', but argument 2 has type 'u64' [-Werror=format=] Change-Id: Ibc2bf8597cb86db5b2e71fba77ec837a08c5e3d4 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3301 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-27util/inteltool: Add support for mobile 5 chipsetVladimir Serbinenko
Dump registers on mobile 5. Successfully tested on X201. Change-Id: I606371801d3ae6c96d3d404c9775c254bd0ffbc9 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/2993 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-05-26Get buildgcc to behave reasonably with the -p choice.Ronald G. Minnich
buildgcc has many wrong choices, and two right ones, but you would never guess that. It's even more frustrating when it spends lots of time building a full tool chain and you find out it's not the one you wanted and, still worse, you've forgotten what it does want and, even worse, it won't f-ing tell you what the two right choices are!. Have it tell you when you've done something wrong, and have it make reasonable decisions when you say things like -p arm instead of -p armv7a-eabi This change lowers my blood pressure 10 points. Change-Id: I44a59d7cb7a6260894d8bcb692a693ed25681ff8 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3292 Tested-by: build bot (Jenkins)
2013-05-26kconfig: fix choice dependency checkRoman Zippel
Properly check the dependency of choices as a group. Also fix that sym_check_deps() correctly terminates the dependency loop error check (otherwise it would continue printing the dependency chain). Signed-off-by: Roman Zippel <zippel@linux-m68k.org> Signed-off-by: Sam Ravnborg <sam@ravnborg.org> ======= Cherry-picked from the Linux kernel. Change-Id: I0c98760dd0f55cf2ff70c53e0b014288b59574c8 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3290 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-26kconfig: reversed borderlines in inputboxRoel Kluin
Fix reversal of dlg.border.atr and dlg.dialog.atr for draw_box() Makes the inputbox look like expected Signed-off-by: Roel Kluin <12o3l@tiscali.nl> Signed-off-by: Sam Ravnborg <sam@ravnborg.org> ======= Cherry-picked from the Linux kernel. Change-Id: I596915aab0204ef0e392fefa56fad8e25204e207 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3289 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-26kconfig: add named choice groupRoman Zippel
As choice dependency are now fully checked, it's quite easy to add support for named choices. This lifts the restriction that a choice value can only appear once, although it still has to be within the same group, but multiple choices can be joined by giving them a name. While at it I cleaned up a little the choice type logic to simplify it a bit. Signed-off-by: Roman Zippel <zippel@linux-m68k.org> Signed-off-by: Sam Ravnborg <sam@ravnborg.org> ======= Cherry-picked from the Linux kernel. Change-Id: If0f00d1783907d606220cda5307b8960d3bfc38d Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3291 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-10romcc: support attribute((packed))Stefan Reinauer
right now this is just a fake option to get rid of ifdefs in coreboot's code. Change-Id: I59233f3c1d266b4e716a5921e9db298c7f96751d Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3225 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-05-10Get rid of MAXIMUM_CONSOLE_LOGLEVEL; compile all messages into the coreboot ↵Ronald G. Minnich
binary This option has never had much if any use. It solved a problem over 10 years ago that resulted from an argument over the value or lack thereof of including all the debug strings in a coreboot image. The answer is in: it's a good idea to maintain the capability to print all messages, for many reasons. This option is also misleading people, as in a recent discussion, to believe that log messges are controlled at build time in a way they are not. For the record, from this day forward, we can print messages at all log levels and the default log level is set at boot time, as directed by DEFAULT_CONSOLE_LOGLEVEL. You can set the default to 0 at build time and if you are having trouble override it in CMOS and get more messages. Besides, a quick glance shows it's always set to max (9 in this case) in the very few cases (1) in which it is set. Change-Id: I60c4cdaf4dcd318b841a6d6c70546417c5626f21 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3188 Tested-by: build bot (Jenkins)
2013-05-04nvramtool: Use CMOS_SIZE for cmos sizePatrick Georgi
We write CMOS data to 128 byte files, which is a problem when using them later-on (eg. as part of a coreboot image) where nvramtool assumes them to be 256 byte, and so data corruption occurs. Change-Id: Ibc919c95f6d522866b21fd313ceb023e73d09fb9 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/3186 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-03crossgcc: update to gcc 4.7.3Idwer Vollering
Update crossgcc to use gcc 4.7.3 The resulting coreboot.rom is not runtime tested (any volunteers?). Drop the texinfo patch, rename the armv7a patch. Some Linux distributions have moved on to gcc 4.8, under certain circumstances this version can't (cross-)compile gcc 4.7.2 Bug report: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56927 Change-Id: Id8ce5f86c34e1a0900d44dc6ae4e81cb9548ecc2 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/3112 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-22superiotool: add CR dump for W83627UHG = NCT6627UDFrank Rysanek
This commit adds "register dump capability" to superiotool for a specific chip by Winbond/Nuvoton: the W83627UHG AKA NCT6627UD (same chip, different package). In other words, it fills in the "CR map" definitions in winbond.c, which so far have been void for this chip. - superiotool r4.0-3976-g190011e Found Winbond W83627UHG = NCT6627UD (id=0xa2, rev=0x32) at 0x2e Register dump: idx 02 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f val ff a2 32 ff f0 44 00 00 ff 00 00 00 00 03 00 00 ff def 00 a2 NA ff f0 MM 00 MM RR 00 00 00 00 02 00 00 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 f2 f4 f5 val 00 00 00 00 02 8e 00 ff 00 00 def 01 03 f0 06 02 8e 00 ff 00 00 LDN 0x01 (Parallel port) idx 30 60 61 70 74 f0 val 00 03 78 0c 04 3f def 01 03 78 07 04 3f LDN 0x02 (UART A) idx 30 60 61 70 f0 val 01 03 f8 04 00 def 01 03 f8 04 00 LDN 0x03 (UART B) idx 30 60 61 70 f0 f1 val 01 02 f8 03 00 44 def 01 02 f8 03 00 00 LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 72 f0 val 01 00 60 00 64 01 0c 82 def 01 00 60 00 64 01 0c 83 LDN 0x06 (UART C) idx 30 60 61 70 f0 val 01 03 e8 05 80 def 01 03 e0 04 00 LDN 0x07 (GPIO 3, GPIO 4) idx 30 e0 e1 e2 e3 e4 e5 e6 e7 val 04 ff ff ff ff ff ff ff ff def 00 ff 00 00 00 ff 00 00 00 LDN 0x08 (WDTO#, PLED, GPIO 5,6 & GPIO Base Address) idx 30 60 61 e0 e1 e2 e3 e4 e5 e6 e7 f5 f6 f7 val 01 00 00 ff ff ff ff ff ff ff ff 02 00 00 def 02 00 00 ff 00 00 00 ff 1f 00 00 00 00 00 LDN 0x09 (GPIO 1, GPIO 2 and SUSLED) idx 30 e0 e1 e2 e3 e4 e5 e6 e7 f3 val 02 ff ff ff ff 00 ff 00 00 00 def 00 ff 00 00 00 ff 00 00 00 00 LDN 0x0a (ACPI) idx 30 70 e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 f2 f3 f4 f6 f7 fe val 01 00 01 00 0a 00 00 00 0c 00 09 00 01 00 00 00 00 00 def 00 00 01 00 ff 08 00 00 1c 00 RR RR 3e 00 00 00 00 00 LDN 0x0b (Hardware monitor) idx 30 60 61 70 f0 f1 f2 val 01 02 48 00 81 ff 81 def 00 00 00 00 RR RR 00 LDN 0x0c (PECI, SST) idx e0 e1 e2 e3 e4 e5 e6 e7 e8 f1 f2 f3 fe ff val 00 48 48 48 48 00 00 00 00 4c 50 10 23 5a def 00 48 48 48 48 00 RR RR 00 48 50 10 23 5a LDN 0x0d (UART D) idx 30 60 61 70 f0 val 00 00 00 00 00 def 00 02 e0 03 00 LDN 0x0e (UART E) idx 30 60 61 70 f0 val 00 00 00 00 80 def 00 03 e8 04 00 LDN 0x0f (UART F) idx 30 60 61 70 f0 val 01 02 38 0a 00 def 00 02 e8 03 00 Change-Id: I834f8767b29f3148f353004edb22cfd7db5ddd56 Signed-off-by: Frank Rysanek <Frantisek.Rysanek@post.cz> Reviewed-on: http://review.coreboot.org/3027 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-04-16cbmem: map_memory: Use length modifier `j` and cast for an `off_t` argumentPaul Menzel
cbmem currently fails to build due to `-Werror` and the following warning. $ make cc -O2 -Wall -Werror -iquote ../../src/include -iquote ../../src/src/arch/x86 -c -o cbmem.o cbmem.c cbmem.c: In function ‘map_memory’: cbmem.c:87:2: error: format ‘%zx’ expects argument of type ‘size_t’, but argument 2 has type ‘off_t’ [-Werror=format] […] Casting the argument of type `off_t` to `intmax_t` and using the length modifier `j` $ man 3 printf […] j A following integer conversion corresponds to an intmax_t or uintmax_t argument. […] instead of `z` as suggested in [1] and confirmed by stefanct and segher in #coreboot on <irc.freenode.net>, gets rid of this warning and should work an 32-bit and 64-bit systems, as an `off_t` fits into `intmax_t`. [1] http://www.pixelbeat.org/programming/gcc/int_types/ Change-Id: I1360abbc47aa1662e1edfbe337cf7911695c532f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3083 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-15inteltool: pcie.c: Use `0xffULL` instead of `0xff` to avoid shift overflowPaul Menzel
When building inteltool with Clang, it warns about the following. $ clang --version Debian clang version 3.2-1~exp6 (tags/RELEASE_32/final) (based on LLVM 3.2) Target: i386-pc-linux-gnu Thread model: posix $ CC=clang make […] clang -O2 -g -Wall -W -c -o pcie.o pcie.c pcie.c:297:40: warning: signed shift result (0xFF0000000) requires 37 bits to represent, but 'int' only has 32 bits [-Wshift-overflow] pciexbar_phys = pciexbar_reg & (0xff << 28); ~~~~ ^ ~~ pcie.c:301:41: warning: signed shift result (0xFF8000000) requires 37 bits to represent, but 'int' only has 32 bits [-Wshift-overflow] pciexbar_phys = pciexbar_reg & (0x1ff << 27); ~~~~~ ^ ~~ pcie.c:305:41: warning: signed shift result (0xFFC000000) requires 37 bits to represent, but 'int' only has 32 bits [-Wshift-overflow] pciexbar_phys = pciexbar_reg & (0x3ff << 26); ~~~~~ ^ ~~ 3 warnings generated. […] Specifying the length by using the suffix `0xffULL` fixes these issues as now enough bits are available. These issues were introduced in commit 1162f25a [1]. commit 1162f25a49e8f39822123d664cda10fef466b351 Author: Stefan Reinauer <stepan@coresystems.de> Date: Thu Dec 4 15:18:20 2008 +0000 Patch to util/inteltool: * PMBASE dumping now knows the registers. * Add support for i965, i975, ICH8M * Add support for Darwin OS using DirectIO [1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=1162f25a49e8f39822123d664cda10fef466b351 Change-Id: I7b9a15b04ef3bcae64e06266667597d0f9f07b79 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3015 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.huber@secunet.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-15cbmem: Makefile: Allow to override `CC` variablePaul Menzel
Now users can use a different compiler from GCC like Clang by for example doing `CC=clang make`. Change-Id: I664a36df79f7496a56d89bdb61948b2eda33a6b4 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3082 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-14inteltool: Use portable type `uint64_t` instead of `u64`Paul Menzel
In [1] Idwer Vollering noted, that the type `u64` is not portable so on his FreeBSD system, the following warning is shown. $ clang -O2 -Wall -W -I/usr/local/include -c -o amb.o amb.c amb.c:441:22: error: use of undeclared identifier 'u64' ambconfig_phys = ((u64)pci_read_long(dev16, 0x4c) << 32) | The type `uint64_t` seems to be defined also on FreeBSD, so using this fixes the warning. Note, this warning is not reproducable with Debian Sid/unstable for example. I have no idea why though. [1] http://review.coreboot.org/#/c/3015/ Change-Id: Ic22f4371114b68ae8221d84a01fef6888d43f365 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3086 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-14cbmem: parse_cbtable: Use length modifier `ll` `u64` argumentPaul Menzel
Currently on a 32-bit system cbmem fails to build due to `-Werror` and the following warning. $ make cc -O2 -Wall -Werror -iquote ../../src/include -iquote ../../src/src/arch/x86 -c -o cbmem.o cbmem.c […] cbmem.c: In function ‘parse_cbtable’: cbmem.c:135:2: error: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 2 has type ‘u64’ [-Werror=format] cc1: all warnings being treated as errors […] Using the length modifier `ll` instead of `l` gets rid of this warning. Change-Id: Ib2656e27594c7aaa687aa84bf07042933f840e46 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3084 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-12cbfstool: cbfs-mkstage.c: Free `buffer` on error pathPaul Menzel
Cppcheck warns about a memory leak, present since adding romtool, which was renamed to cbfstool, in commit 5d01ec0f. $ cppcheck --version Cppcheck 1.59 […] [cbfs-mkstage.c:170]: (error) Memory leak: buffer […] Indeed the memory pointed to by `buffer` is not freed on the error path, so add `free(buffer)` to fix this. Change-Id: I6cbf82479027747c800c5fe847f20b779e261ef4 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3069 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-12acpica: update URLIdwer Vollering
The URL to acpica-unix-20121114 has changed, update the URL. Change-Id: I1c8c228094f19455af3682f36f1990586fe3934c Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/3070 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-09util/cbmem: Don't output trailing garbage for cbmemcVladimir Serbinenko
Current code outputs the whole cbmemc buffer even if only part of it is really used. Fix it to output only the used part and notify the user if the buffer was too small for the required data. Change-Id: I68c1970cf84d49b2d7d6007dae0679d7a7a0cb99 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/2991 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-08cbfstool: completely initialize input and output streamsStefan Reinauer
The LZMA glue code in cbfstool was recently rewritten from C++ to plain C code in: commit aa3f7ba36ebe3a933aa664f826382f60b31e86f1 Author: Stefan Reinauer <reinauer@chromium.org> Date: Thu Mar 28 16:51:45 2013 -0700 cbfstool: Replace C++ code with C code Reviewed-on: http://review.coreboot.org/3010 In the progress of doing so, the stream position for the input stream and output stream was not reset properly. This would cause LZMA producing corrupt data when running the compression function multiple times. Change-Id: I096e08f263aaa1931517885be4610bbd1de8331e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3040 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-08inteltool: remove unused file descriptor variable and ifdefsStefan Tauner
Change-Id: I6a119b1f362f481914377e8d14c713159f895130 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/3030 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-05inteltool: use inttypes for prints in memory.cStefan Tauner
This fixes at least one warning on my machine where "llx" is replaced by PRIx64. Change-Id: Iee3e5027d327d4d5f8e6d8b2d53d051f74bfc354 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/3024 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-05inteltool: cpu.c: Use conversion specifier `u` for unsigned integersPaul Menzel
Cppcheck [1], a static code analysis tool, warns about the following. $ cppcheck --version Cppcheck 1.59 $ cppcheck --enable=all . […] Checking cpu.c... [cpu.c:951]: (warning) %d in format string (no. 1) requires a signed integer given in the argument list. [cpu.c:962]: (warning) %d in format string (no. 1) requires a signed integer given in the argument list. […] And indeed, `core` is an unsigned integer and `man 3 printf` tells the following about conversion specifiers. d, i The int argument is converted to signed decimal notation. […] o, u, x, X The unsigned int argument is converted to unsigned octal (o), unsigned decimal (u), or unsigned hexadecimal (x and X) notation. So use `u` and Cppcheck does not complain anymore. [1] http://cppcheck.sourceforge.net/ Change-Id: If8dd8d0efe75fcb4af2502ae5100e3f2062649e4 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3026 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-04libpayload, superiotool: README: Prepend `coreboot/` to path of change ↵Paul Menzel
directory line Nico Huber spotted [1], that commit (4d6ab4e2) [1] updating superiotools’s `README` with the Git command line superiotool: Update README with Git repository URL and directory location missed, that after `git clone` one sitll has to change into the cloned directory. So prepend the path with `coreboot/` to fix that. The same error happened in the commit (e1ea5151) for libpayload [2] libpayload: Update README with Git repository URL and directory location and is fixed in this patch too. [1] http://review.coreboot.org/#/c/3019/ [2] http://review.coreboot.org/2228 Change-Id: Ib6e8b678af6276556a40ccfd52ae35ca7e674455 Reported-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3021 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-04-04inteltool: Cast to `intptr_t` instead of `uint64_t`Paul Menzel
When building inteltool under x86-32, the following warnings are shown. $ gcc --version gcc-4.7.real (Debian 4.7.2-15) 4.7.2 Copyright (C) 2012 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. $ make […] amb.c: In function ‘amb_read_config32’: amb.c:31:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] amb.c:31:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] amb.c: In function ‘amb_read_config16’: amb.c:45:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] amb.c:45:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] amb.c: In function ‘amb_read_config8’: amb.c:60:22: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] amb.c:60:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] […] Nico Huber commented the following [1]. I don't see those warnings because I build for x86-64. I guess they could be fixed by casting to `ptrdiff_t` (from stddef.h) instead of `uint64_t`. And indeed, using `ptrdiff_t` fixes the warning. But as Stefan Reinauer commented in [2], `intptr_t` is more appropriate as this is just a pointer and no pointer difference. So `intptr_t` is taken, which fixes these issues warned about too. These warnings were introduced in commit »inteltool: Add support for dumping AMB registers« (4b7b320f) [3]. [1] http://review.coreboot.org/#/c/2996/1//COMMIT_MSG [2] http://review.coreboot.org/#/c/3002/1/util/inteltool/amb.c [3] http://review.coreboot.org/525 Change-Id: I2ea1a31dc1e3db129e767d6a9e0433fd75a77d0f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3002 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-04-04superiotool: Update README with Git repository URL and directory locationPaul Menzel
Change-Id: I36d980cea5ca9cc67262dba809441091757e1fb5 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3019 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-04-03inteltool: Use `ll` instead of `l` as the length modifier for `uint64_t`Paul Menzel
When buidling inteltool with GCC, the following warning is printed. $ make […] gcc -O2 -g -Wall -W -c -o memory.o memory.c memory.c: In function ‘print_mchbar’: memory.c:287:7: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 3 has type ‘uint64_t’ [-Wformat] […] This was introduced in commit »inteltool: Add support for H65 Express chipset« (c7fc4422) [1]. Address this warning, by using `%llx` instead of `%lx`. [1] http://review.coreboot.org/1258 Change-Id: I4f714edce7e8b405e1a7a417d02fa498322c88a8 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2994 Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Tested-by: build bot (Jenkins)
2013-04-03cbfstool: Replace C++ code with C codeStefan Reinauer
cbfstool was using a C++ wrapper around the C written LZMA functions. And a C wrapper around those C++ functions. Drop the mess and rewrite the functions to be all C. Change-Id: Ieb6645a42f19efcc857be323ed8bdfcd9f48ee7c Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3010 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-02cbfstool: fix --machineStefan Reinauer
The help text says --machine, but the code actually checked for --arch. Fix it! Change-Id: Ib9bbf758b82ef070550348e897419513495f154b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3009 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-01inteltool: Allow to override Makefile variablesPaul Menzel
Allow to override the variables `CC`, `INSTALL`, `PREFIX`, `CFLAGS` and `LDFLAGS`. Though append `-lpci -lz` to `LDFLAGS`. This way for example a different compiler can easily be used. CC=clang make As a side note, Clang in contrast to GCC does *not* issue the following warnings. $ clang --version Debian clang version 3.2-1~exp6 (tags/RELEASE_32/final) (based on LLVM 3.2) Target: i386-pc-linux-gnu Thread model: posix $ gcc --version gcc-4.7.real (Debian 4.7.2-15) 4.7.2 Copyright (C) 2012 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. $ make […] amb.c: In function ‘amb_read_config32’: amb.c:31:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] amb.c:31:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] amb.c: In function ‘amb_read_config16’: amb.c:45:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] amb.c:45:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] amb.c: In function ‘amb_read_config8’: amb.c:60:22: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] amb.c:60:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] […] These are only shown under 32-bit and not 64-bit $ uname -m i686 and are going to be fixed in a separate patch. Change-Id: Id75dea081ecb35390f283520a7e5dce520f4c98d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2996 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-01inteltool: Add Cougar/Panther Point GPIO defaultsNico Huber
This adds default values for the GPIO setup on Intel's Cougar Point and Panther Point platform controller hubs (PCH). Values are taken from [1] and [2], respectively. I've tested this with an H77 PCH. See below for the output. [1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet Document-Number: 324645-006 [2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) - Datasheet Document-Number: 326776-003 $ ./inteltool -G CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9 Northbridge: 8086:0150 (unknown) Southbridge: 8086:1e4a (H77) ========== GPIO DIFFS =========== GPIOBASE = 0x0500 (IO) gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL) gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL) gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF gpiobase+0x000c: 0xe1f17f7e (GP_LVL) gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF gpiobase+0x002c: 0x00002000 (GPI_INV) gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2) gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2) gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF gpiobase+0x0038: 0xb65e7f4f (GP_LVL2) gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3) gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3) gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF gpiobase+0x0048: 0x00000dfc (GPIO_LVL3) gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF gpiobase+0x0060: 0x00000000 (GP_RST_SEL1) gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF $ ./inteltool -gG CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9 Northbridge: 8086:0150 (unknown) Southbridge: 8086:1e4a (H77) ============= GPIOS ============= GPIOBASE = 0x0500 (IO) gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL) gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL) gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF gpiobase+0x0008: 0x00000000 (RESERVED) gpiobase+0x000c: 0xe1f17f7e (GP_LVL) gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF gpiobase+0x0010: 0x00000000 (RESERVED) gpiobase+0x0014: 0x00000000 (RESERVED) gpiobase+0x0018: 0x00040000 (GPO_BLINK) gpiobase+0x001c: 0x00000000 (GP_SER_BLINK) gpiobase+0x0020: 0x00080000 (GP_SB_CMDSTS) gpiobase+0x0024: 0x00000000 (GP_SB_DATA) gpiobase+0x0028: 0x0000 (GPI_NMI_EN) gpiobase+0x002a: 0x0000 (GPI_NMI_STS) gpiobase+0x002c: 0x00002000 (GPI_INV) gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2) gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2) gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF gpiobase+0x0038: 0xb65e7f4f (GP_LVL2) gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF gpiobase+0x003c: 0x00000000 (RESERVED) gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3) gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3) gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF gpiobase+0x0048: 0x00000dfc (GPIO_LVL3) gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF gpiobase+0x004c: 0x00000000 (RESERVED) gpiobase+0x0050: 0x00000000 (RESERVED) gpiobase+0x0054: 0x00000000 (RESERVED) gpiobase+0x0058: 0x00000000 (RESERVED) gpiobase+0x005c: 0x00000000 (RESERVED) gpiobase+0x0060: 0x00000000 (GP_RST_SEL1) gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF gpiobase+0x0064: 0x00000000 (GP_RST_SEL2) gpiobase+0x0068: 0x00000000 (GP_RST_SEL3) gpiobase+0x006c: 0x00000000 (RESERVED) gpiobase+0x0070: 0x00000000 (RESERVED) gpiobase+0x0074: 0x00000000 (RESERVED) gpiobase+0x0078: 0x00000000 (RESERVED) gpiobase+0x007c: 0x00000000 (RESERVED) Change-Id: If99cf8d5c93e34ad28f52080fff64e01c220eb27 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/3001 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-01inteltool: Add option to show differences in GPIO setupNico Huber
This adds an option -G, --gpio-diffs to inteltool, which shows GPIO settings that differ from platform defaults. For differing registers, the current, the default, and an xor of the default and the current value is printed. A follow-up commit will add defaults for the Cougar/Panther Point platform controller hubs. If you specify both, -g and -G on the command line, all GPIO registers will be printed interleaved with the diff. Here's a preview: $ ./inteltool -G CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9 Northbridge: 8086:0150 (unknown) Southbridge: 8086:1e4a (H77) ========== GPIO DIFFS =========== GPIOBASE = 0x0500 (IO) gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL) gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL) gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF gpiobase+0x000c: 0xe1f17f7e (GP_LVL) gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF gpiobase+0x002c: 0x00002000 (GPI_INV) gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2) gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2) gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF gpiobase+0x0038: 0xb65e7f4f (GP_LVL2) gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3) gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3) gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF gpiobase+0x0048: 0x00000dfc (GPIO_LVL3) gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF gpiobase+0x0060: 0x00000000 (GP_RST_SEL1) gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF $ ./inteltool -gG CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9 Northbridge: 8086:0150 (unknown) Southbridge: 8086:1e4a (H77) ============= GPIOS ============= GPIOBASE = 0x0500 (IO) gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL) gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL) gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF gpiobase+0x0008: 0x00000000 (RESERVED) gpiobase+0x000c: 0xe1f17f7e (GP_LVL) gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF gpiobase+0x0010: 0x00000000 (RESERVED) gpiobase+0x0014: 0x00000000 (RESERVED) gpiobase+0x0018: 0x00040000 (GPO_BLINK) gpiobase+0x001c: 0x00000000 (GP_SER_BLINK) gpiobase+0x0020: 0x00080000 (GP_SB_CMDSTS) gpiobase+0x0024: 0x00000000 (GP_SB_DATA) gpiobase+0x0028: 0x0000 (GPI_NMI_EN) gpiobase+0x002a: 0x0000 (GPI_NMI_STS) gpiobase+0x002c: 0x00002000 (GPI_INV) gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2) gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2) gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF gpiobase+0x0038: 0xb65e7f4f (GP_LVL2) gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF gpiobase+0x003c: 0x00000000 (RESERVED) gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3) gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3) gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF gpiobase+0x0048: 0x00000dfc (GPIO_LVL3) gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF gpiobase+0x004c: 0x00000000 (RESERVED) gpiobase+0x0050: 0x00000000 (RESERVED) gpiobase+0x0054: 0x00000000 (RESERVED) gpiobase+0x0058: 0x00000000 (RESERVED) gpiobase+0x005c: 0x00000000 (RESERVED) gpiobase+0x0060: 0x00000000 (GP_RST_SEL1) gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF gpiobase+0x0064: 0x00000000 (GP_RST_SEL2) gpiobase+0x0068: 0x00000000 (GP_RST_SEL3) gpiobase+0x006c: 0x00000000 (RESERVED) gpiobase+0x0070: 0x00000000 (RESERVED) gpiobase+0x0074: 0x00000000 (RESERVED) gpiobase+0x0078: 0x00000000 (RESERVED) gpiobase+0x007c: 0x00000000 (RESERVED) Change-Id: Ic77474c4bc0871e95103ddecd9f6a9406c8f016d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/3000 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-01inteltool: Support PM registers on Cougar/Panther PointNico Huber
This adds the power management register definitions for Intel's Cougar Point and Panther Point platform controller hubs (PCH). The definitions are actually a subset of the older ICH10R registers: I've added just those that are mentioned in the public specifications in [1] and [2]. I've tested dumping with an H77 PCH. NM70 is missing in [1]. Therefore, I didn't add it here. [1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet Document-Number: 324645-006 [2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) - Datasheet Document-Number: 326776-003 Change-Id: Ia6945fe96cd96b568ed5191e91dbba5556e1ee95 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/2985 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-30inteltool: Add Cougar/Panther Point IDs to rootcmplx.cNico Huber
This adds the PCI IDs of Intel's Cougar Point and Panther Point platform controller hubs (PCH) to the dumping of the root complex configuration under the root complex base address (RCBA). Those PCHs are handled exactly as the older ICHs which can be seen in [1] and [2]. I've tested dumping with an H77 PCH. NM70 is missing in [1]. Therefore, I didn't add it here. [1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet Document-Number: 324645-006 [2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) - Datasheet Document-Number: 326776-003 Change-Id: I2296caae57e614171300362d41715deecec77762 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/2986 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-03-29superiotool: Allow to override Makefile variables `CC`, `INSTALL` and `PREFIX`Paul Menzel
This way for example a different compiler can easily be used. CC=clang make Change-Id: I50b83554fd4826d00d87e60a30eb1f6a88834397 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2935 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-29inteltool: Support GPIO registers on Cougar/Panther PointNico Huber
This adds the GPIO register definitions for Intel's Cougar Point and Panther Point platform controller hubs (PCH). All information is taken from the public specifications in [1] and [2]. I've tested it with an H77 PCH. NM70 is missing in [1]. Therefore, I didn't add it here. [1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet Document-Number: 324645-006 [2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) - Datasheet Document-Number: 326776-003 Change-Id: I31711e24f852e68b3c113e3bd9243dc7e89ac197 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/2961 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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