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2018-07-24util/crosgcc: Fix most shellcheck errors in buildgccMartin Roth
This fixes most of the simpler shellcheck errors in shellcheck 0.4.6. There are still a few warnings left that weren't simple to fix or would have required more testing before I was confident in them. Change-Id: I79ab3614cc1d69d3dfe1e0374e930313f2011cbf Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/27598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-24util/crosgcc/patches: update make-4.2.1 patchesMartin Roth
- Add the Do-not-assume-glibc-glob-internals patch to fix segfaults. - Update glob_interface_v2 patch to the patch directly from the make git repository instead of translating it. This gives better attributution to the original author. Change-Id: Ibc936fc00925a4ca2170a6f5dca7c2b8d8d62f02 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/27591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-24Build system: Add fixes for scanbuildMartin Roth
- Exclude build flags that generate warnings when scanbuild is running - Add the SCANBUILD_ARGS variable to abuild so we can pass in arguments to scanbuild. - Set the default scanbuild argument to -k (--keep-going) so that even if an error occurs it continues with the scan. This is similar to what we do with coverity runs. Change-Id: I82e7c13d7fd7432b43c17a31834ec82fca158a07 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/27595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-24util/docker: Update Makefile to improve shell accessMartin Roth
- Create a new target, docker-jenkins-attach, to access the running jenkins server - Update docker-shell target to set term & size. Change-Id: Ifa67afb62d4a216281ebece405e9b26fd4d14622 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/27494 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-20util/cbfstool: fix build with clangPatrick Georgi
Without the second set of braces it fails (due to -Werror) with "suggest braces around initialization of subobject" Change-Id: I63cb01dd26412599551ee921c3215a4aa69f4e17 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/27551 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-19util/gitconfig: Make checkpatch non fatal in pre-commit hookMartin Roth
We don't block commits for failing checkpatch in gerrit, and we shouldn't block them here. This allows checkpatch to still run, so users can see the issues, but won't prevent the commit. Adds a delay if checkpatch fails so that the issues can be seen. Change-Id: Ibd4e8bb74e0b02825dcdf16e233a061c4bb43f50 Signed-off-by: Martin Roth <martin@coreboot.org> Reviewed-on: https://review.coreboot.org/27534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-07-19cbfstool/add-payload: initialize segment headers to 0Joel Kitching
Some types of payload segment headers do not use all fields. If these unused fields are not initialized to 0, they can cause problems in other software which consumes payloads. For example, PAYLOAD_SEGMENT_ENTRY does not use the compression field. If it happens to be a non-existent compression type, the 'cbfstool extract' command fails. BUG=https://ticket.coreboot.org/issues/170 TEST=cbfstool tianocore.cbfs create -s 2097152 -m x86 cbfstool tianocore.cbfs add-payload -f UEFIPAYLOAD.fd -n payload -c lzma -v xxd tianocore.cbfs | head # visually inspect compression field for 0 Change-Id: I359ed117ab4154438bac7172aebf608f7a022552 Signed-off-by: kitching@google.com Reviewed-on: https://review.coreboot.org/27540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-18linux_trampoline: use trampoline RAM for the GDTRonald G. Minnich
The linux trampoline was modifying the existing GDT to add the 0x10 and 0x18 descriptors for Linux. This will not work when the existing GDT is in ROM. Change the code to set up a new GDT in what we know to be RAM. Tested by booting a linux payload. The main reason this works is that Linux almost immediately loads its own GDT and then segment registers. This GDT is a very temporary bridge. Note that none of this change used to be necessary; the coreboot GDT was originally compatible with Linux (ca 2000); then Linux changed. Change-Id: I13990052fbfd6a500adab8a2db8f7aead1d24fa6 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/27529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-18what-jenkins-does: Pass V=1 through to abuildMartin Roth
Even though we were setting V=1 in the build, this wasn't getting passed to abuild, so the builds there didn't have additional debug information. That made it difficult to debug issues on the builder. This sets the verbose flag for abuild if V=1 is set. Change-Id: Id9ec50add9693a6c36ffdb5c78d148d0fc012549 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/27492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-17util/docker: Update coreboot-jenkins-node dockerfileMartin Roth
Because earlier versions of debian set /dev as a standard tmpfs filesystem, that was a simple place to build. Now, this has been changed and /dev isn't a standard tmpfs that will grow to 50% of memory. It's a fixed, very small size, and can no longer even be resized. Because of this, create a new directory to build in and add it to /etc/fstab. Mount it when the container is started. As long as we're at it, make the other build directories (ccache and slave-root/workspace) tmpfs as well. The builders we're using now have plenty of memory, so don't write any of the files to disk. Update the Makefile to get rid of all references to ccache directory. Change-Id: I21fd2c4395d7ffb9428172f035991338658cd907 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/27470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-13cbfstool: Show current FMAP region in printPatrick Rudolph
In case multiple FMAP regions are specified, print the FMAP name. Useful if VBOOT is enabled and multiple CBFS are printed. Change-Id: Id6f29ebeda8a9bde6dfe39362e0f2a5e33c86b26 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26862 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-09util/cavium: Add tool to convert devicetree blobsPatrick Rudolph
Convert Cavium's BDK devicetree blob to a static C file. The resulting file must be included in mainboard folder to provide board specific configuration values to BDK functions. Example call: python devicetree_convert.py --in sff8104.dtb --out bdk_devicetree.c Change-Id: I76a5588aefe4f680228eca46a0e4dba7e695931c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26228 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-06util/lint: Update lint-stable-000-license-headers linterMartin Roth
- Update stable directories - Remove duplicated directories There are currently 220 files that still need to have headers added or be excluded from the lint-000-license-headers test. Change-Id: I40046a2fb7359262b130f6813eda1f2c30916b46 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-06util/cbfstool/compiler: __attribute redefinitionFrans Hendriks
In Windows Cygwin enviroment, compiler reports redefinition error at cbfstool/ifwitool.c on _packed and __aligned. Skip new defines when vales are already defined. Change-Id: I3af3c6b8fc57eee345afcef2f871b897138f78ce Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/27357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-30cbfstool: fix FIT entry checksum type value for ucode entriesMatt DeVillier
commit c1072f2 [cbfstool: Update FIT entries in the second bootblock] incorrectly changed the value of type_checksum_valid for microcode entries from FIT_TYPE_MICROCODE to 0, breaking microcode loading on Skylake/FSP1.1 devices (and others?). Correct this by reverting to the previous value. Test: build/boot google/chell, observe FspTempRamInit no longer fails, device boots as expected. Change-Id: Ib2a90137c7d4acf6ecd9f06cb6f856bd7e783676 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27266 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-28util/crossgcc: update to gcc 8.1.0 and binutils 2.30Patrick Georgi
Also update patches as necessary. Change-Id: I1e8074954d5d7a4eff590abb7439e9be7d3762aa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/25997 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-28crosgcc/patches: Add make patch for GLIBC glob interface v2Martin Roth
Copied from the GNU make repository author Paul Smith <psmith@gnu.org> commit 48c8a116 configure.ac: Support GLIBC glob interface version 2 Change-Id: Id70a2b98dad6349ee56985d8dd6d4f0d87b470e6 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/26939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-26util/crossgcc: Allow building a new gcc against new binutils with -DPatrick Georgi
With -D, the newly built toolchain isn't installed into $prefix/... but into $DESTDIR/$prefix/... while being built for $prefix alone. This is useful for distributions, but it breaks down when the build host already has the toolchain installed in $prefix without proper build isolation (cf. gentoo): In such cases libgcc etc are built using the new compiler (as gcc's build system is smart enough to state the path explicitly), but that compiler then uses its regular algorithm to determine the path to as, ld, ... That makes it use the tools from $prefix, which might differ in formats (assembly, certain object file flags, ...): nds32le-elf in particular has rather unstable formats still, and so new compilers can't work with old binutils. The approach to deal with this is to take an unused path that's specified by gcc's build system ($out/gcc/$arch/$version) and symlink it to the new toolchain - these explicitly given directories take precedence over the default search path, and so the new binutils are used. Change-Id: Ia9a262e73f56cd486a2ae07422b598c205a03aed Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/27241 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-26cbfstool: Update FIT entries in the second bootblockRizwan Qureshi
Once a second bootblock has been added using topswap (-j) option, Update the entries in second FIT using -j option with update-fit command. Additionally add a -q option which allows to insert the address of a FMAP region (which should hold a microcode) as the first entry in the second FIT. BUG=None BRANCH=None TEST= Create ROM images with -j options and update FIT using -q option. example: ./build/util/cbfstool/cbfstool coreboot.tmp create \ -M build/fmap.fmap -r COREBOOT,FW_MAIN_A,FW_MAIN_B,RW_LEGACY build/util/cbfstool/cbfstool coreboot.tmp add \ -f build/cbfs/fallback/bootblock.bin -n bootblock -t \ bootblock -b -49152 -j 0x10000 build/util/cbfstool/cbfstool coreboot.tmp add-master-header -j 0x10000 build/util/cbfstool/cbfstool coreboot.tmp add -f build/cpu_microcode_blob.bin \ -n cpu_microcode_blob.bin -t microcode -r COREBOOT -a 16 build/util/cbfstool/cbfstool coreboot.tmp. update-fit \ -n cpu_microcode_blob.bin -x 4 -j 0x10000 -q FW_MAIN_A Also try the failure scenarion by providing invalid topswap size. Change-Id: I9a417031c279038903cdf1761a791f2da0fe8644 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/26836 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-26cbfstool: add an option for creating a topswap bootblockRizwan Qureshi
Add an option '-j' which takes the size of topswap boundary. This option serves both as a bool and a size for creating a second bootblock to be used with topswap feature in Intel CPUs. '-j' is also used in conjunction with add-master-header to update the location of cbfs master header in the second bootblock. BUG=None BRANHC=None TEST=add bootblock entry to the image with -j option specifying different topswap sizes and also use the -j option for add-master-header. Change-Id: I3e455dc8b7f54e55f2229491695cf4218d9cfef8 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/22537 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-25util/abuild: Enable abuild to compile a single variantFurquan Shaikh
There are many boards in coreboot which support multiple variants. When abuild is used to compile a single target, it builds all its variants. If a target has 5 variants, then abuild takes nearly 10x the time to compile all variants of the target. This change adds an option -b/--board-variant to enable abuild to compile only a single variant of the target. TEST=Verified: 1. abuild builds all variants of the target if -b option is not provided. 2. abuild builds a single variant if -b option is provided. 3. abuild prints appropriate error message if invalid variant name is provided. Change-Id: I3781568c6409c5ec2610a8386a21d86037428e7f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27215 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-25util/sconfig: Get rid of ops from struct deviceFurquan Shaikh
"ops" field was used in device structure only to add default_dev_ops_root for root device. It was always set to NULL for all other devices. This change gets rid of ops field from struct device and instead hardcodes default_dev_ops_root in pass1 for root device. BUG=b:80081934 TEST=Verified that static.c generated with and without this change is exactly the same. Change-Id: I0848788610c2ed27274daf4920de3068a9784d4c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27209 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-25util/sconfig: Add support for overriding base tree properties/nodeFurquan Shaikh
This change adds support to allow variants to override the devices and properties in base device tree by providing an override device tree. It works as follows: 1. Both base and override device trees are parsed from provided input files. 2. Walk through the trees in lockstep fashion using depth-first traversal checking if a node in override tree has a matching node in base tree. - If matching node is found, then update the properties of base node using the override node. Continue walking the children of the nodes. - If matching node is not found, then copy the entire override subtree of the node under the current base parent. In addition to that, chip instance pointers of the nodes in override tree need to be updated if they were pointing to the override parents chip instance. Since chip always expects a device to be present, it leads to a side-effect that overriding chip registers requires that a device is always provided for the chip in the override tree as well. BUG=b:80081934 Change-Id: I6604e4f8abe3fc48240e942fea32da96031e1e46 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27206 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-25util/sconfig: Enable parsing of override device treeFurquan Shaikh
This change allows sconfig utility to accept an extra optional parameter to specify override device tree that can be used to override the properties or add new devices in addition to that provided by base device tree. This is helpful for variants that share most of the devicetree but have to override certain registers or add some devices which might not be applicable to base devicetree. In order to support the override devicetree, following changes are made in this CL: 1. override_root_dev and override_root_bus are provided. 2. main() function is updated to accept an optional argument. 3. If override device file is provided, then parse_devicetree is called for override_devtree as well. This change in itself does not provide the override feature. It is only a small step towards the final goal. The override devicetree parsed by sconfig is currently unused. BUG=b:80081934 Change-Id: I477e038c8922ae1a9ed5d8bf22a5f927a19a69c7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-25util/lint/checkpatch_json: Fix checkpatch output keyword match stringNaresh G Solanki
From checkpatch output, look for keywords starting with 'ERROR:' & 'WARNING:' . Also check for keywork ': FILE:' instead of the same without the colon (:). BUG=None BRANCH=None TEST=Check if patch https://review.coreboot.org/#/c/coreboot/+/22537/21 is processed & json output is generated properly. Change-Id: Ib690ab34a1ffabc4f83642634fd34beea16a64dc Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/27170 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-25sb/intel/common/firmware: Enable me_cleaner for NehalemNicola Corna
Recent patches in coreboot have fixed the freeze issues related to the use of me_cleaner on Nehalem. However, at least on the Lenovo X201, with me_cleaner some PCIe devices (like the SATA and USB controllers) disappear. In particular, setting the AltMeDisable bit ("-S" or "-s" flag) makes them disappear completely, while unsetting it makes them disappear only during cold boots. This kind of behaviour was already observed by Youness Alaoui on the Purism Librem laptops ([1]), and it seems related to some required board-specific PCIe configuration in the ME's MFS partition. For this reason, on the Lenovo X201, "-w EFFS" has been added to the me_cleaner arguments, which whitelists the MFS-equivalent partition for ME generation 2. This fixes all the issues, and the PCIe devices work as expected. [1] https://puri.sm/posts/deep-dive-into-intel-me-disablement/ Change-Id: Ie77a80d2cb4945cf1c984bdb0fb1cc2f18e82ebc Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/27178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-22cbfstool/fit.c: Fix for older CPUs without total_size in mcu_headerArthur Heymans
Some older CPUs have a fixed size of 2048 bytes for microcode total size. Change-Id: Ia50c087af41b0df14b607ce3c3b4eabc602e8738 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27090 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21inteltool: Add PCI IDs for the C220 PCH seriesqeed
Adds missing PCI IDs to allow tool to dump the C220 PCH (8 series) southbridge. Intel Document 328904 is the datasheet for this PCH. Change-Id: I07a8f2e9cb0ee8677c8fe2c51881147ed81c1a35 Signed-off-by: Quan Tran <qeed.quan@gmail.com> Reviewed-on: https://review.coreboot.org/27168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-21util/abuild: Fix building when not in coreboot root dirArthur Heymans
Change-Id: Ibe54096f275a05bda745ae2cc76c0109281c0c4b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-19payloads: Add LinuxBoot payload in u-root modePhilipp Deppenwiese
* Add LinuxBoot support * Add u-root mode * Download kernel and u-root from upstream sources. * Add customization options * Clean kernel only if directory exists Change-Id: I3a25ff6812e046acc688cbbb203cf262ad751659 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/23071 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-18cbfstool: Use endian.h and functions from commonlibWerner Zeh
The endian conversion function be32toh() is defined in src/include/endian.h, however this file is not used for cbfstool compilation. Currently the one provided by the host is used and if the host does not provide this endian.h file, the build will fail. However, we do have endian conversion functions in commonlib/endian.h which is available for cbfstool compilation. Switch from be32toh() to read_be32() in order to avoid relying on a host provided include file. We use functions from commonlib/endian.h already in cbfstool. Change-Id: I106274cf9c69e1849f848920d96a61188f895b36 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/27116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-15util/cbfstool: Support FIT payloadsPatrick Rudolph
In order to support booting a GNU/Linux payload on non x86, the FIT format should be used, as it is the defacto standard on ARM. Due to greater complexity of FIT it is not converted to simple ELF format. Add support for autodecting FIT payloads and add them as new CBFS_TYPE 'fit'. The payload is included as is, with no special header. The code can determine the type at runtime using the CBFS_TYPE field. Support for parsing FIT payloads in coreboot is added in a follow on commit. Compression of FIT payloads is not supported, as the FIT sections might be compressed itself. Starting at this point a CBFS payload/ can be either of type FIT or SELF. Tested on Cavium SoC. Change-Id: Ic5fc30cd5419eb76c4eb50cca3449caea60270de Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-06-14src: Get rid of unneeded whitespaceElyes HAOUAS
Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14src: Get rid of device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: I6adc0429ae9ecc8f726d6167a6458d9333dc515f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14util/docker/coreboot.org-status: collect report generatorsPatrick Georgi
Move generators for the board status report and the kconfig options report into a common directory and wrap them in a docker container. Also rework to emit HTML not wiki syntax. Change-Id: If42e1dd312c5fa4e32f519865e3b551bc471bc72 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/26977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-14util/lint: Run lint-extended-007-final-newlines checks in parallelMartin Roth
Instead of checking each directory in series, kick off the checks in parallel and then wait for them to finish. Failures print out with file information, so mixing output isn't a problem. This reduces the time it takes to run on lumberingbuilder by 60%. This could probably be sped up even more by splitting up src/mainboard into smaller sections. This method does skip a few control files at the top level - .gitignore, .checkpatch.conf, gnat.adc, etc. These could be added to the list of files to check, but I didn't think it was needed. Change-Id: I171977e713a9956cf4142cfc0a199e10040abb35 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/27011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-13util/sconfig: Prepare sconfig to allow parsing multiple treesFurquan Shaikh
In preparation to allow devicetree overrides, it will be necessary to use the same parsing functions to prepare two separate parse trees. This change does the following things: 1. Updates root device and bus names to add base_ prefix. 2. Adds a function parse_devicetree that sets the root_parent and linenum before calling yyparse(). 3. Updates all uses of root_dev to refer to the next base_root_dev. BUG=b:80081934 TEST=Verified that static.c generated for all boards built using abuild is the same with and without this change. Change-Id: I403a90c1ebf07ac66115ddfe137daf0980dc1a18 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-06-12util/lint: Run lint-extended-007-checkpatch checks in parallelMartin Roth
Instead of checking each directory in series, kick off all the checks in parallel and then wait for them to finish. Failures print out with file information, so mixing output isn't a problem. This reduces the time it takes to run on lumberingbuilder from 31 seconds to 6. Change-Id: I1252a68a723370389d399f3d1a2aff3fad64c365 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/26995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-12kconfig: add script to manipulate .config files on the command linePaul Menzel
Copy the script `scripts/config` from Linux (commit 427fbe89 (Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux)) into the newly created directory `scripts`. Here is the original commit message from 2009. > commit 8e54701ea85b0ab0971637825a628f5aa2b678a4 > Author: Andi Kleen <andi@firstfloor.org> > Date: Sat Jan 3 03:21:41 2009 +0100 > > kconfig: add script to manipulate .config files on the command line > > I often change single options in .config files. Instead of using > an editor or one of the frontends it's convenient to do this from > the command line. It's also useful to do from automated build scripts > when building different variants from a base config file. > > I extracted most of the CONFIG manipulation code from one of my > build scripts into a new shell script scripts/config > > The script is not integrated with the normal Kconfig machinery > and doesn't do any checking against Kconfig files, but just manipulates > that text format. This is always done at make time anyways. > > I believe this script would be a useful standard addition for scripts/* > > Sample usage: > > ./scripts/config --disable smp > Disable SMP in .config file > > ./scripts/config --file otherdir/.config --module e1000e > Enable E1000E as module in otherdir/.config > > ./scripts/config --state smp > y > Check state of config option CONFIG_SMP > > After merging into git please make scripts/config executable > > Signed-off-by: Andi Kleen <ak@linux.intel.com> > Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Change-Id: Ie32a4459398df8694956dd644f38692017a26388 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/26243 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-11util/optionlist: show location of a commentPatrick Georgi
Change-Id: Ib417f435011f0331a1b0228734874ef0a62fb587 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/26945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-11util/optionlist: move kconfig2wiki to kconfig2html and adapt to htmlPatrick Georgi
This also removes a "chapters mode" that we never used. Change-Id: Ib301e2f4db0b9678081fa987a5dcc7108bb103a4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/26944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-11inteltool: Add dumping of full PCR portsYouness Alaoui
SoCs from Skylake on have many settings as so called private con- figuration registers (PCRs). These are organized as 256 ports with a 64KiB space each. We use the Primary to Sideband (P2SB) bridge's BAR to access them. Change-Id: Iede4ac601355e2be377bc986d62d20098980ec35 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19593 Reviewed-by: Youness Alaoui <snifikino@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-11mediatek/mt8183: Add a stub implementation of the MT8183 SOCTristan Shieh
Most things still need to be filled in, but this will allow us to build boards which use this SOC. BUG=b:80501386 BRANCH=none TEST=timer and uart work fine Change-Id: Ie81fa56ffce85188e1f9e979f9b0e64b764c2627 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/26659 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-11{src,util}: Use NULL instead of 0 for pointerElyes HAOUAS
Change-Id: I75fa4577055f25dde0a8b1044c005bba72cabd92 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-11crossgcc: Update to clang 6.0 & cmake 3.11.3Martin Roth
Change-Id: I1a0db60b527c2f7ffe77743c0d75b78a7c8bc4cc Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/26877 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-08util/sconfig: Get rid of rescnt in struct deviceFurquan Shaikh
This change gets rid of rescnt member in struct device since it is redundant. "res" member can be used to determine if resource list is present or not. BUG=b:80081934 TEST=Verified that static.c generated with and without this CL is exactly the same for all boards built using abuild. Change-Id: I73a2361686ad1130716a7d29576f2d02b9ed33c1 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-08util/sconfig: Re-factor device structure in parse treeFurquan Shaikh
This change re-factors the device structure in parse tree to be able to support multidev devices just like non-multidev devices. With this change, every device has a bus under it which is the parent of all devices that fall on the bus. If there are duplicate entries in the devicetree, then there will be multiple buses under the device and each bus will have its own set of children. The tree starts out with a root device which has a root bus under it. This is a special device which is created statically and its parent is its own root bus. When parsing the device tree file, devices get added under the root bus as children. Since this change re-organizes the way devicetree is represented, it gets rid of latestchild and next_sibling pointers from struct device. Also, the tree traversal to generate static.c is changed to breadth-first walk instead of using the next_sibling. BUG=b:80081934 TEST=Verified using abuild that all boards compile successfully. Change-Id: Ic8c8a73a247e8e992ab6b1b2cc3131e06fa2e5a1 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-08util/sconfig: Make queue handling more generic within main.cFurquan Shaikh
This change updates queue handling routines to be more generic so that it can be used by more than just chip queue. Additionally, it provides functions to dequeue element from head and peek head of a queue which will be used in a follow-up commit. BUG=b:80081934 TEST=Verified that abuild compiles successfully for all boards. Change-Id: Ibd2de85b48c5d4e2790bf974ea3bb1bd387f66ee Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-08sconfig/main.c: Fix number of arguments in fprintfMaulik V Vaghela
During compilation sconfig/main.c gives an error regarding number of arguments passed in fprintf. BUG=none BRANCH=none TEST=check if compilation warning has been fixed Change-Id: Ia769cc606a1e3f7e1188cd82235442493d37f664 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/26972 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-08util/sconfig: Get rid of unused parameter to walk_device_treeFurquan Shaikh
This change gets rid of unused 3rd parameter chips to the function walk_device_tree. BUG=b:80081934 TEST=Verified that abuild compiles successfully for all boards. Change-Id: I255ff030562073b16310fc22a0981808bf2c062f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 12:41:05 +0000