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2020-06-30ACPI: Drop typedef global_nvs_tKyösti Mälkki
Bring all GNVS related initialisation function to global scope to force identical signatures. Followup work is likely to remove some as duplicates. Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30Add qc_blobs repositoryJulius Werner
This patch adds a separate blobs repository for Qualcomm blobs, analogous to the existing AMD blobs. Qualcomm's binary licenses allow files to be redistributed and used by anyone, but they explicitly require the user to agree to the license terms when just *downloading* the binary (even if they're not using them to build any firmware). Some community members do not like to have to agree to licenses for files they're not actually using, so we are keeping these files separate from the main blobs repository and adding an extra Kconfig to make sure the user is aware of and must explicitly agree to this before downloading these files. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I247746c1b633343064c9f32ef1556000475d6c4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/42548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-26Fix up Docker paths to match jenkins nomenclatureStefan Reinauer
Jenkins is calling its build nodes "agent". Reflect that in the path names we use in configuration. Change-Id: I88a4d3d32a565ade768e3de6428f46d355bedfb2 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42819 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25util/abuild: Only update submodules oncePatrick Georgi
Without this, each build will try to update the submodules. Not necessarily a problem but git locks repos, creating spurious error messages. Change-Id: Iba20677d4b5f9365c92f7ed247ca56acb7d33b27 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-24util/mainboard/google/volteer: Add dptf.asl to the templateZhuohao Lee
The dptf.asl is needed when creating a new volteer variant, otherwise, it will make the variant build failed. The error could be found from this link: https://review.coreboot.org/c/coreboot/+/42709 BUG=b:158797761 TEST=Generate the Delbin correctly Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Change-Id: Ib4059df9e08d6a1dba88f0299bb39c8c6ae406ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/42715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-06-23util/mb/google/tmpl/puff: Fix overridetree.cb to swap USB portsEdward O'Callaghan
Switch USB2 port1 and port3 due to circuit change from rev0. BUG=b:154071868,b:154585046,b:156429564 BRANCH=none TEST=none Change-Id: I5b9a20bd657ed587ec891e52f66629d554df6166 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-06-23util/mb/google/tmpl/puff: Import overridetree.cb copyEdward O'Callaghan
BUG=b:154071868 BRANCH=none TEST=none Change-Id: I40faa5f80e78cd73ba5ef977574f7f662c0ab8a1 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-06-23util/mb/google/tmpl/puff: Generate correct gpio muxingEdward O'Callaghan
BUG=b:154071868 BRANCH=none TEST=none Change-Id: Iae4fe48b6a3df730b2334cb1f32b35addc90bec0 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-06-23util/mb/google/tmpl/puff: Fix include paths for gen boardEdward O'Callaghan
BUG=b:154071868 BRANCH=none TEST=none Change-Id: Ifa5cd021ae37d61ddb9eb9bf6a970a931058e33c Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-06-22src/mainboard: Remove unused include 'sandybridge.h'Elyes HAOUAS
Change-Id: I9356a56c34d1c6746cf8acfe931386ffed58ba74 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-18lint: convert checkpatch_json.py to python 3Stefan Reinauer
Align all coreboot scripts on one python version. Tested by running the original suggested test: $ nice -n 20 git diff HEAD~ | util/lint/checkpatch.pl \ --no-signoff -q - | tee checkpatch.txt $ util/lint/checkpatch_json.py checkpatch.txt \ comment.json checkpatch.txt Change-Id: Iec2bb0be23b27a3eaf92f293c962a8e6bfb03af0 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-06-17crossgcc: Upgrade GDB to version 9.2Elyes HAOUAS
Change-Id: I30dae356ec3b373ac036c7eced7d6e89ddd08246 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38787 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17crossgcc: Remove "Make"Elyes HAOUAS
In its current state, it draws more dependencies in than it solves which makes it useless. Change-Id: I08f592731c3da2ac19e1f93682256f559a067fc4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-06-17ifdtool: Improve PCH strap handlingPatrick Rudolph
Read the PCH Strap Length field in FLMAP1 as described in the "SPI Programming Guide" and print the number of fields specified there. This code dumps the following straps: * Intel GM45: 8 straps * Intel C216: 72 straps * Intel C240: 360 straps Add a new function to easily set PCH straps, which is useful for debugging. Change-Id: Ieb7891b214d82c984379794de9b3fe1a6d0d3466 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-15sandybridge boards: Factor out MAX_CPUSAngel Pons
Also update autoport accordingly. Change-Id: I12481363cf0e7afc54e2e339504f70632e8d72e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41839 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15util/cbfstool: Add option --pow2pageKyösti Mälkki
For add-stage command, --pow2page is equivalent of passing -P log2ceil(sizeof stage). The sizeof stage can be hard to determine in Makefile to be passed on the commandline. Change-Id: If4b5329c1df5afe49d27ab10220095d747024ad6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-06-14util/board_status: Also check remotely retrieved coreboot console logPaul Menzel
Currently, the logs are only checked, if retrieved locally. Moving it after the if statement, now logs retrieved remotely are also checked. The change in behavior is, that now all commands are executed first, so before hitting this error, other errors might occur unrelated to the console log. Change-Id: I016bbde66c58a654042ad880c6007ddc1d143691 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-14util/intelmetool: Add support for Intel Cannon Point LP HECI ControllerMatt DeVillier
Tested on Intel NUC 8i5BEH (CFL) and Purism Librem Mini (WHL) Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: I1054455fff2dcae8d17afe2adf3329eb44aa862a Reviewed-on: https://review.coreboot.org/c/coreboot/+/42233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-13util/cbfstool: Drop IS_TOP_ALIGNED_ADDRESS() check in cbfstool_convert_fspFurquan Shaikh
This change drops the check for IS_TOP_ALIGNED_ADDRESS() before setting offset to 0 in cbfstool_convert_fsp(). If the user provides a baseaddress to relocate the FSP to, then the offset should be set to 0 since there is no requirement on where the file ends up in cbfs. This allows the user to relocate the FSP to an address in lower DRAM. BUG=b:155322763 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ibeadbf06881f7659b2ac7d62d2152636c853fb9f Reviewed-on: https://review.coreboot.org/c/coreboot/+/42263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-10Revert "util/abuild: Have abuild generate the .xcompile if it doesn't exist"Nico Huber
This reverts commit 9ff4029db9b1053b44e4fc487243017a099a49c5. Pulling the toplevel Makefile into a tiny one has all sorts of side effects. For instance, the toplevel (random) .config is also included so the results depend on the board that is selected there. What finally broke it is a line that is unconditionally printed for AMD Picasso boards resulting in lots of lines like this: skipping LENOVO_W520 because we're missing compilers for \ (Adding PSP c7ce61492157d3237f679c4a40a08b79 \ .../coreboot/3rdparty/amd_blobs/picasso/PSP/PspBootLoader_prod_RV.sbin) While both issues, the random .config and amd/picasso, could be worked around easily, it seems hard to predict what other pitfalls are lurking in the Makefile inclusion. Also, the problem solved by its inclusion can be fixed by a much simpler `make .xcompile`. Change-Id: I2ff70f561d717eb30e5f3c06c83e83468e174ec5 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-10util/abuild: Ensure .xcompile existsNico Huber
abuild requires the `.xcompile` file to be present already before it runs any actual `make` builds that would generate it. Change-Id: Ib485e7741b7700fa241c192e60900ae5f1d977f5 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-10templates: remove Dedede and Volteer Makefile.incPaul Fagerburg
SPD sources for Dedede and Volteer are being auto-generated by SPD tools now, and so we can remove SPD_SOURCES from Makefile.inc for those templates. That makes Makefile.inc empty for those reference boards, so remove Makefile.inc from the templates. BUG=b:158492307 BRANCH=None TEST=Create new variant of volteer, waddledee, and waddledoo, and verify that we can still build the coreboot image. Signed-off-by: Paul Fagerburg <pfagerburg@google.com> Change-Id: Iba5264384302300cc8d2256a6b43f3353770154a Reviewed-on: https://review.coreboot.org/c/coreboot/+/42204 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10crossgcc: Backport GNAT exception handler v1 patchIru Cai
The GCC 10 GNAT toolchain uses a new exception handler ABI, so older GNAT cannot be built with GCC 10. This patch backports the new exception handler in libgnat to make GNAT able to be built. The libgnat patch doesn't remove the old exception handler, so it can still be built with older compilers. The cross toolchain can now be built with GCC 10.1.0 in Arch Linux (with the latest IASL in CB:38907 that can be built in Arch), and the toolchain can build a working coreboot image with libgfxinit for HP EliteBook 2560p. The original and patched crossgcc built with Debian 10.4 GCC 8.3.0, and the patched crossgcc built with Arch GCC 10.1.0 generate identical coreboot images with `make BUILD_TIMELESS=1`. Change-Id: I757158056bf4698d3c68715e026c226615bc70a1 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42158 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-08util/amdfwtool: Add option for setting PSP/FW shared memory locationMartin Roth
This tells the PSP where in main memory to copy the vboot workbuf. BUG=b:152576063 TEST=Build sharedmem destination into AMDFW, verify shared memory gets placed at that location. Signed-off-by: Martin Roth <martin@coreboot.org> Original-Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Change-Id: Ie1e955e22632ca5cf146ac6eec0407091e81f519 Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2148830 Original-Reviewed-by: Simon Glass <sjg@chromium.org> Change-Id: Id324403afa6d5a5a65ce4709be31e7f16e038da0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42044 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-08util/amdfwtool: update to allow building in any locationMartin Roth
For the verstage-on-PSP implementation, we need 2 additional copies of the AMD firmware tables at non-standard locations. These are for RW-A & RW-B fmap regions. This change allows us to build the AMD firmware tables into those regions. BUG=b:148767300 TEST=boot with psp_verstage, verify boot location Signed-off-by: Martin Roth <martin@coreboot.org> Original-Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Change-Id: I2b591b50e9b179fdfaead46ff93722fa2a155e9c Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2144534 Original-Reviewed-by: Simon Glass <sjg@chromium.org> Change-Id: I7f841db8617b953dc671a9c12576145f85263581 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-08spd/lp4x: Set manufacturer part name to blank (0x20)Furquan Shaikh
As per JEDEC spec, manufacturer part name should be set to blank (0x20). This change updates gen_spd.go to set bytes 329-348 as 0x20 and regenerates SPDs for TGL and JSL. Change-Id: I6af18d89afd7264cec7e54b38e95df83d55aa058 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42023 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06lp4x: Add new memory parts and generate SPDsFurquan Shaikh
This change adds the following memory parts to LP4x global list and generates SPDs using gen_spd.go for TGL and JSL: 1. MT53E512M32D2NP-046 WT:E 2. K4U6E3S4AA-MGCR 3. H9HCNNNCPMMLXR-NEE 4. K4UBE3D4AA-MGCR BUG=b:157862308, b:157732528 Change-Id: Ib7538247d39dfe5faab277d646f87f09103d6969 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41989 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06util/spd_tools/intel/lp4x: Add a global list of LP4x memory partsFurquan Shaikh
This change adds a JSON file (`global_lp4x_mem_parts.json.txt`) containing global list of LP4x memory parts to live along with the spd tools since the part information is not really any SoC or mainboard dependent and comes directly from the part datasheet. It can be shared by mainboards based on different platforms supported by the tools. BUG=b:155239397,b:147321551 Change-Id: I9e2f98fc9c1c8a7f73c9a1bfab22c996de222a32 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41874 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06util: Add spd_tools to generate SPDs for TGL and JSL boardsFurquan Shaikh
Serial Presence Detect (SPD) data for memory modules is used by Memory Reference Code (MRC) for training the memory. This SPD data is typically obtained from part vendors but has to be massaged to format it correctly as per JEDEC and MRC expectations. There have been numerous times in the past where the SPD data used is not always correct. In order to reduce the manual effort of creating SPDs and generating DRAM IDs, this change adds tools for generating SPD files for LPDDR4x memory used in memory down configurations on Intel Tiger Lake (TGL) and Jasper Lake (JSL) based platforms. These tools generate SPDs following JESD209-4C specification and Intel recommendations (doc Two tools are provided: * gen_spd.go: Generates de-duplicated SPD files using a global memory part list provided by the mainboard in JSON format. Additionally, generates a SPD manifest file (in CSV format) with information about what memory part from the global list uses which of the generated SPD files. * gen_part_id.go: Allocates DRAM strap IDs for different LPDDR4x memory parts used by the board. Takes as input list of memory parts used by the board (with one memory part on each line) and the SPD manifest file generated by gen_spd.go. Generates Makefile.inc for integrating the generated SPD files in the coreboot build. BUG=b:155239397,b:147321551 Change-Id: Ia9b64d1d48371ccea1c01630a33a245d90f45214 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-06-04util/mb/google: add templates for puff boardsPaul Fagerburg
Add template directory for the Puff reference board. BUG=b:157701044 BRANCH=None TEST=N/A Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Change-Id: Ic81c663b92eeb1d39c2b425d331eb16812f58b7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/42026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2020-06-04util: Allow overriding gcc as default host compilerPatrick Georgi
BUG=chromium:1088209 TEST=emerge coreboot-utils (with patches to the ebuild) works Signed-off-by: Patrick Georgi <pgeorgi@google.com> Change-Id: I25d237d048e417f4e412583031905ecf3614c431 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-06-02sconfig: Add support for firmware configurationDuncan Laurie
This change adds support to sconfig for generating the firmware configuration field and option definitions in devicetree.cb. In addition these fields and options can be used to probe for a device and have that device be disabled if it is not found at boot time. New tokens: fw_config: top level token, table can be defined before chips field: define field in the mask with the start and end bits option: define option in a field with the value of the field probe: indicate that a device should probe by field and option Example: fw_config field FEATURE 0 0 option DISABLE 0 option ENABLE 1 end end chip drivers/generic/feature device generic 0 on probe FEATURE ENABLE end end Variants can add new fields and add new options to existing fields in overridetree.cb but cannot redefine an existing option. Devices can have multiple probe tokens, and the device will be considered to be found if any of them return true. The output from defining this field are: 1) the various fields and options will be added as macro constants to static.h and can be used by fw_config for probing. 2) the probe entries will result in a list of fields/options to probe that is added to the resulting struct device and handled by coreboot. BUG=b:147462631 Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I8aea63e577d933aea09e0d0b09470929cc96e0de Reviewed-on: https://review.coreboot.org/c/coreboot/+/41440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-02util/sconfig: Move default includes out of emit_chips()Nico Huber
This should make it easier to add more includes. Change-Id: Ib4a25352901408c2b36de4972391df742a0d8037 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41744 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02util/sconfig: Refactor and fix add_register()Nico Huber
add_register() contained a duplicate check but only compared the new key to the first (smallest in order) list member. Fix that and factor the list handling out so it can be used by other functions. Change-Id: I5a8346f36fa024351e1282c9681868ecf451b283 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41743 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02util/mb/google: add templates for dedede boardsPaul Fagerburg
Add template directories for the Waddledee and Waddledoo reference boards of the Dedede baseboard. BUG=b:157183582 BRANCH=None TEST=N/A Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Change-Id: Ida70a44097334991a93fec8f4933d7f6e39a187b Reviewed-on: https://review.coreboot.org/c/coreboot/+/41640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-28testing: Add unit tests to what-jenkins-does procedurePatrick Georgi
They're not added as a dependency, even though that should be possible, because we want the build tests to run even when the unit tests fail. Change-Id: Ia3391d7b289160178fa773dfd7b7c51c6ef77805 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Dabros <jsd@semihalf.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-28util/mb/google: remove zork templatePaul Fagerburg
The templates for the zork reference boards are still being actively worked on in the trembyle-bringup branch. Remove the zork template from the main branch to avoid confusion when trembyle-bringup is merged. BUG=b:157099580 BRANCH=none TEST=N/A Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Change-Id: I0ff9de959c7b2646b90e68df05f0b2e9bdd60cf7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-28util/lint: Check for SPDX identifiers by defaultJacob Garber
The majority of the codebase has been converted to use SPDX identifiers now, so let's enforce those by default. The only exceptions are src/include and src/lib, which are not being checked since many of the files there do not have license headers at all. Files with custom licenses that aren't covered by SPDX can be listed as exceptions at the top of lint-000-license-headers. Change-Id: Ie6642153793d5735c74c5950bc9e27ee7eecacbc Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41602 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28docker/coreboot-jenkins-node: Add meson and ninjaPatrick Georgi
Our jenkins instance is also used for flashrom, which can be built with meson, a mode that we want to be able to test, so add that. ninja can be used as a backend to both meson and cmake (which coreboot will use to build cmocka for its unit tests) and may provide some additional coverage. Plus it's tiny but fast. Change-Id: If454164852303144eaa72c4071c03ee89e863318 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-27util/apcb: Use python3 for apcb_edit.pyRaul E Rangel
The code was written on a workstation that has python pointing to python3. BUG=b:157140753 TEST=Built trembyle and was able to boot to the OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I181d87aad1ffb10e12f8ffd7513318f6d6bcbc3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/41739 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-25drivers: Use SPDX identifiersJacob Garber
Convert the remaining files in src/drivers to use SPDX identifiers. int15.h and default_brightness_levels.asl did not have license headers, but they were both copied from other GPL2 files, so they should be under the GPL2 as well. ne2k.c and drm_dp_helper.h are licensed under custom BSD-like licenses that do not have an SPDX equivalent, so they are added as exceptions to the license header lint. Change-Id: I87fb1c637b8d11b0463f7c19f70b847413e14aed Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-21util/amdfwtool: Fix MAX_PSP_ENTRIES valueRob Barnes
Had to increase MAX_PSP_ENTRIES to accommodate the 16 APCBs we have the ability to add. BUG=b:150862063 TEST=Boot Trembyle BRANCH=None Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I64eccfa28839768788f53327caf187a564842162 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2090323 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41580 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18util/apcb: Add apcb_edit toolRob Barnes
On the Picasso architecture, the PSP is responsible for setting up DRAM before releasing the x86. The APCB (AGESA PSP Configuration Block) contains multiple SPDs and the GPIO numbers used to select the correct SPD. Since the source to build the APCBs is not public, it can't be built as part of the coreboot build. To work around this problem, we use a template APCB and inject the relevant information. BUG=b:147042464 Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I88a09743f8e8a184c47071ee5e417f5b6bdb7467 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2123799 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-18util/cbfstool: fix buffer over-readPhilipp Bartsch
Fix unterminated array. When looking for a type not specified in filetypes (cbfs.h:204), the loop in lookup_name_by_type (cbfs_image.c:60) will run into a buffer over-read. Found-by: AFL++ 2.64d rev 1317433 Signed-off-by: Philipp Bartsch <phil@grmr.de> Change-Id: Ib82bb92e82b09fa1e26b9ca34529ec7b98e8f7b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41421 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18util/autoport/bd82x6x.go: Drop unused includesElyes HAOUAS
Change-Id: Ifc0bf18dedc112e346062e0e0e988ac102991bb8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40826 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18util/release: Check that HEAD isn't used as referencePatrick Georgi
genrelnotes moves the tree between commits and so a relative location like HEAD isn't stable. Since I ran into the HEAD issue while preparing for two consecutive releases, let's guard against it. Change-Id: I70c6812cdfe0d0671b3d653744a062d9920a2394 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41339 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18util/release: Improve reporting of required toolsPatrick Georgi
genrelnotes checks for cloc, git and rename but only reported about needing the first two, so mention `rename` in missing message. Change-Id: If91d759fc68760fd89b98756ac5b19ac3589c197 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-12util/sconfig: Add LPC and ESPI busesRaul E Rangel
Picasso has an LPC and eSPI bridge on the same PCI DEVFN. They can both be active at the same time. This adds a way to specify which devices belong on which bus. i.e., device pci 14.3 on # - D14F3 bridge device espi 0 on chip ec/google/chromeec device pnp 0c09.0 on end end end device lpc 0 on end end BUG=b:154445472 TEST=Built trembyle and saw static.c contained the espi bus. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0c2f40813c05680f72e5f30cbb13617e8f994841 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-12inteltool: fix dumping of Lynx Point LP and Wildcat Point PM registersIru Cai
Currently inteltool uses the addresses and names of the PCH of previous generations. It's wrong for Lynx Point LP and Wildcat Point. The addresses and names of the I/O registers can be found in "Mobile 4th Generation Intel Core Processor Family I/O Datasheet" (Document Number: 329003-003) for Lynx Point LP and "Mobile 5th Generation Intel Core Processor Family I/O, Intel Core M Processor Family I/O, Mobile Intel Pentium Processor Family I/O, and Mobile Intel Celeron Processor Family I/O Datasheet" (Document Number: 330837-004) for Wildcat Point. Change-Id: If6ba718ccff077aa89affec89018bd7923527466 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40273 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11util/nvramtool: Remove license boiler plate from DISCLAIMER file, tooPatrick Georgi
Change-Id: I7ce0f08efaddb07a5d5f484d313068e5db3c7e2e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41220 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 11:30:48 +0000