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2020-09-06util/mb/google/tmpl/puff: Update DPTF to the new implementationSam McNally
Apply the change in CB:44905 to the puff template, moving DPTF policies from static ASL files into the new SSDT-based DPTF implementation. BUG=b:158986928 BRANCH=puff TEST=None Change-Id: I601fd4c6aeaa3afee0f7fd9d13376f2fffd6d793 Signed-off-by: Sam McNally <sammc@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-09-03crossgcc: Ensure that GMP is built for a generic CPU on x86Patrick Georgi
While GMP supports fat builds on x86 that adapt to the CPU's capabilities, by default it builds for the CPU of the builder. Running that binary on an older CPU then can fail. Change-Id: Iafdc2eb696189b9e2c5ead316f310d98c949ef74 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45044 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-03util/amdfwtool: Add PSP verstage signature entryMartin Roth
Add the field for the PSP verstage signature entry. This adds the public key signing token to the PSP Directory table to verify the signed PSP verstage binary BUG=b:166100797 TEST=Build in a file and verify that it's present with the correct ID. BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I7525045d8746b6857979d07b02758ab4d4835026 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Eric Peers <epeers@google.com>
2020-09-03util/amdfwtool: Fix warning taking address of packed struct memberMartin Roth
GCC9 introduced a new warning [-Waddress-of-packed-member]. This is giving the following warning when building amdfwtool: warning: taking address of packed member of ‘struct _bios_directory_entry’ may result in an unaligned pointer value. Looking at the definition of the struct, it looks like this is probably true. Since the function being called doesn't read from the values, zeroing them out in the beginning of the function, the code just passes pointers to the temporary variables without initializing them. BUG=None TEST=Build & use AMD firmware table. BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I2f1e0aede8563e39ab0f2ec6daed91d6431eac43 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Eric Peers <epeers@google.com>
2020-09-02util/ifdtool: Fix eSPI frequency as per Gen 11 SPI flash guideSubrata Banik
BUG=b:153888802 TEST=Able to list correct eSPI frequency as per TGL SPI flash guide Without this CL : Found Component Section FLCOMP 0x093030f6 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 50MHz Write/Erase Clock Frequency: 50MHz Fast Read Clock Frequency: 50MHz Fast Read Support: supported Read Clock Frequency: 20MHz With this CL : Found Component Section FLCOMP 0x093030f6 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 50MHz Write/Erase Clock Frequency: 50MHz Fast Read Clock Frequency: 50MHz Fast Read Support: supported Read eSPI/EC Bus Frequency: 60MHz Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I20840e6f931d7c1fabea0b6892e3bd19ead81168 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-02util/ifdtool: Fix SPI frequency as per Gen11 SPI flash guideSubrata Banik
BUG=b:153888802 TEST=Able to list correct SPI frequency as per TGL SPI flash guide Without this CL : Found Component Section FLCOMP 0x093030f6 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 33MHz Write/Erase Clock Frequency: 33MHz Fast Read Clock Frequency: 33MHz Fast Read Support: supported Read Clock Frequency: 20MHz With this CL : Found Component Section FLCOMP 0x093030f6 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 50MHz Write/Erase Clock Frequency: 50MHz Fast Read Clock Frequency: 50MHz Fast Read Support: supported Read Clock Frequency: 20MHz Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Id0a0a0cbd948ef8334cf522c09e881b464e87f0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/44819 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-02util/ifdtool: Add FLMAP3 dump for Gen11 onwards PCHSubrata Banik
BUG=b:153888802 TEST=Able to dump FLMAP3 for Volteer platform with TGP > ifdtool -d coreboot.rom FLMAP3: 0x00000000 Minor Revision ID: 0x0000 Major Revision ID: 0x0000 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I681abd6ae7b87f6638d4f6dc59168cf22b93c787 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44818 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-02util/ifdtool: Fix miscellaneous IFD offset since Gen 5 PCHSubrata Banik
This patch performs below operations: 1. Remove reserved NR field from Gen 5 onwards SPI programming guide 2. Convert ISL to PSL as applicable for Gen 5 onwards PCH 3. Skip FLMAP2 register dump due to nonuniformity since Gen 5 onwards PCH 4. Dump FLILL1 register as applicable for Gen 5 onwards PCH 5. Remove FLPB register as not applicable since Gen 5 PCH BUG=b:153888802 TEST=Dump FD for Hatch platform as below > ifdtool -d coreboot.rom PCH Revision: 300 series Cannon Point/ 400 series Ice Point FLMAP0: 0x00040003 FRBA: 0x40 NC: 1 FCBA: 0x30 FLMAP1: 0x45100208 PSL: 0x45 FPSBA: 0x100 NM: 2 FMBA: 0x80 FLILL1 0xc7c4b9b7 Invalid Instruction 7: 0xc7 Invalid Instruction 6: 0xc4 Invalid Instruction 5: 0xb9 Invalid Instruction 4: 0xb7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I5141ae5dd174659fde5401fac313a701ae4f8f44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-02util/ifdtool: Identify between ICH and PCH RevisionSubrata Banik
Consider IBEX_PEAK onwards all chipsets are belong to PCH family. BUG=b:153888802 TEST=Able to print correct PCH revision on Hatch Platform. > ifdtool -d coreboot.rom Without this CL : ICH Revision: 300 series Cannon Point/ 400 series Ice Point With this CL : PCH Revision: 300 series Cannon Point/ 400 series Ice Point Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Ifd40dddc9179f347c0ea75149ec08089a829fdb4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-31util/ifdtool: Identify chipset without platform nameSubrata Banik
Able to uniquely identify the chipset without specifying the platform specific quirks (adl/cnl/icl/jsl/tgl etc.). BUG=b:153888802 TEST=Able to dump FD contains correctly without specifying platform quirks on Hatch Platform. > ifdtool -d coreboot.rom Without this CL : ICH Revision: 100 series Sunrise Point With this CL : ICH Revision: 300 series Cannon Point/ 400 series Ice Point Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I83763adb721e069343b19a10e503975ffa6abb24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44815 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31util/ifdtool: Skip unused and reserved Flash RegionSubrata Banik
This patch ensures all unused and reserved flash region sections are not getting listed while using -d option to dump FD. BUG=b:153888802 TEST=List only used flash region section with below command > ifdtool -p tgl -d coreboot.rom Without this CL : Found Region Section FLREG0: 0x00000000 Flash Region 0 (Flash Descriptor): 00000000 - 00000fff FLREG1: 0x1fff0400 Flash Region 1 (BIOS): 00400000 - 01ffffff FLREG2: 0x03ff0001 Flash Region 2 (Intel ME): 00001000 - 003fffff FLREG3: 0x00007fff Flash Region 3 (GbE): 07fff000 - 00000fff (unused) FLREG4: 0x00007fff Flash Region 4 (Platform Data): 07fff000 - 00000fff (unused) FLREG5: 0x00007fff Flash Region 5 (Reserved): 07fff000 - 00000fff (unused) FLREG6: 0x00007fff Flash Region 6 (Reserved): 07fff000 - 00000fff (unused) FLREG7: 0x00007fff Flash Region 7 (Reserved): 07fff000 - 00000fff (unused) FLREG8: 0x00007fff Flash Region 8 (EC): 07fff000 - 00000fff (unused) With this CL : Found Region Section FLREG0: 0x00000000 Flash Region 0 (Flash Descriptor): 00000000 - 00000fff FLREG1: 0x1fff0400 Flash Region 1 (BIOS): 00400000 - 01ffffff FLREG2: 0x03ff0001 Flash Region 2 (Intel ME): 00001000 - 003fffff FLREG3: 0x00007fff Flash Region 3 (GbE): 07fff000 - 00000fff (unused) FLREG4: 0x00007fff Flash Region 4 (Platform Data): 07fff000 - 00000fff (unused) FLREG8: 0x00007fff Flash Region 8 (EC): 07fff000 - 00000fff (unused) Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I900a29d8968bd61d66c04012e60e1ba4baff786d Reviewed-on: https://review.coreboot.org/c/coreboot/+/44813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-31util/ifdtool: Add platform specific quirks for ADL/ICL/JSL/TGLSubrata Banik
BUG=b:153888802 TEST=Able to dump FD contain using below command > ifdtool -p tgl -d coreboot.rom Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I0c9106051f4daf592d2467ebf79f9ddb037011dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/44809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-31lint/lint-extended-007-checkpatch: Remove obsolete pathElyes HAOUAS
Change-Id: I8a91d2a8bc6a1fa709aeadd3b7482d1785068276 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-31{intel/gma,include/device}: Delete unused 'drm_dp_helper.h' fileElyes HAOUAS
'drm_dp_helper.h' file is duplicated and not used. Change-Id: Ibb08f7ff91c3914940dfe899be331b06e292c7c9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-08-31cross-repo-cherrypick: Do not prepend "Original-" to "Cq-Depend:"Karthikeyan Ramasubramanian
Marking dependencies has undergone some change in Chrome OS tree. The script to cherry-pick the changes to ChromeOS tree prepends "Original-" to the concerned meta data i.e. Cq-Depend becomes Original-Cq-Depend. This causes dependencies to not take effect when changes are submitted to the continuous integration. Do not prepend "Original-" to the dependency meta data. BUG=None TEST=Ensure that the Cq-Depend line is added without any prefix. Change-Id: I0503234954f872ee56708e19e89cae9d9fa30df7 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-29util/inteltool: Add support for Comet Lake-UMatt DeVillier
Add support for 10th-gen/Comet Lake-U based boards: - add PCI IDs for host bridge, IGD, LPC devices - add support for dumping GPIOs, PCRs, etc Tested on an unbranded CML-U board running AMI firmware Change-Id: I44871917565fc628fd1073a6e5c36b6a3246a61c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-28util: Add memory parts needed by zork boardsRob Barnes
Add memory parts needed by zork boards. Attributes are derived from data sheets. BUG=b:162939176 TEST=Compared generated SPDs with data sheets and checked in SPDs Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I67f205f9af24bbc5c12656be1f363a15fe975955 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44447 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28util/gen_spd: translate DeviceBusWidth to die bus widthNick Vaccaro
If a memory part is a x16 part that has two dies and only a single rank, then the x16 describes the part width (since this solution will need to be a stacked solution) and as such, we must translate the DeviceBusWidth to the "die bus width" instead. Change DeviceBusWidth variable name to PackageBusWidth to be more descriptive BUG=b:166645306, b:160157545 TEST=run gen_spd and verify that spds for parts matching description above changed appropriately. Change-Id: Ia6f3ca109d344b7a015da28125a94ce10d2bdfb8 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-28Revert "util: update lp4x gen_part_id tool to include memory type"Aaron Durbin
This reverts commit eb7a1dd80e72ef435c71650284f355f7f57ebe72. MEMORY_TYPE = lines in Makefiles are not longer needed. Drop it. Change-Id: I96ac39a30555a870e7778a0e71d738407b6b89ef Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44895 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28util: Add support to spd_tools for fixed idRob Barnes
For boards that have already assigned memory ids, there needs to be a way to fix parts to a specific id. After assigning all the fixed ids the tool still attempts to minimize the SPDs entries. Since a fixed ID could be anywhere, gaps can be created in the list. So an empty SPD entry is created to fill the gaps in the list until they are used. BUG=b:162939176 TEST=Generate various outputs Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I1f8ea1ff4f33a97ab28ba94896a1054e89189576 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-08-28util: volteer/dedede: move generic SPDs to common locationNick Vaccaro
Now that generic SPD files have the memory type prepended to the filename, they can be stored in the same location. This CL moves the generic SPDs to the new location. Change the ddr4 gen_part_id.go and gen_spd.go tools to use "ddr4_spd_manifest.generated" instead of "spd_manifest.generated". Change the lpddr4x gen_part_id.go and gen_spd.go tools to use "lp4x_spd_manifest.generated" instead of "spd_manifest.generated". Move TGL DDR4 and LPDDR4x generic SPDs into a common location. Move JSL DDR4 and LPDDR4x generic SPDs into a common location. Change the volteer/spd/Makefile.inc to use the new path for the spds. Change the dedede/spd/Makefile.inc to use the new path for the spds. BUG=b:165854055 TEST="emerge-volteer coreboot" and verify all variants build correctly. Change-Id: I83b088cb718d15ffd3012c84a12b5231ae84a3e4 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44648 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-27util: Add check for duplicate entries in mem parts jsonRob Barnes
Check for duplicate entries in mem parts json file. BUG=b:162939176 TEST=Verified that tool throws error when there is a duplicate. Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I7c638c7938958727cfc832e7b4556acbc04b0ca4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44478 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-27util: Add Picasso and Pollock platforms to spd_toolsRob Barnes
PCO = Picasso PLK = Pollock BUG=b:162939176 Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I43b74f68871062112f53fbbef8a170db53734b3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/44477 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-27util/spd_tools: Support comments in jsonRob Barnes
Allow comments in json file for better documentation. Comments must be on seperate line. BUG=none TEST=Injest global_ddr4_mem_parts.json.txt with comments Change-Id: I51295408d4f916708e4ed5bc42d5468ccdc68a6b Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-27util/spd_tools: Remove intel subfolderRob Barnes
Move ddr4 and lp4x to spd_tools root folder. The tool now applies to non intel platforms. BUG=b:162939176 TEST=Run tool Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I0941ea036d760ee27eb34f259f4506a4b7584bee Reviewed-on: https://review.coreboot.org/c/coreboot/+/44844 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-25util: update lp4x gen_part_id tool to include memory typeNick Vaccaro
Add "MEMORY_TYPE = lp4x" to the generated Makefile.inc to indicate this is lpddr4x memory and to use the generic SPDs from the lpddr4x respository of SPDs. BUG=b:160157545 TEST=run gen_part_id for volteer and verify that it adds the line "MEMORY_TYPE = lp4x" to the makefile produced. Change-Id: I416690ae8aff8052474b16ef0d3e940e72e6a2fb Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-25util: Add spd_tools to generate DDR4 SPDs for TGL boardsNick Vaccaro
Serial Presence Detect (SPD) data for memory modules is used by Memory Reference Code (MRC) for training the memory. This SPD data is typically obtained from part vendors but has to be massaged to format it correctly as per JEDEC and MRC expectations. There have been numerous times in the past where the SPD data used is not always correct. In order to reduce the manual effort of creating SPDs and generating DRAM IDs, this change adds tools for generating SPD files for DDR4 memory used in memory down configurations on Intel Tiger Lake (TGL) based platforms. These tools generate SPDs following JESD79-4C and Jedec "4.1.2.L-5 R29 v103" specification. Two tools are provided: * gen_spd.go: Generates de-duplicated SPD files using a global memory part list provided by the mainboard in JSON format. Additionally, generates a SPD manifest file (in CSV format) with information about what memory part from the global list uses which of the generated SPD files. * gen_part_id.go: Allocates DRAM strap IDs for different DDR4 memory parts used by the board. Takes as input list of memory parts used by the board (with one memory part on each line) and the SPD manifest file generated by gen_spd.go. Generates Makefile.inc for integrating the generated SPD files in the coreboot build. BUG=b:160157545 Change-Id: I263f936b332520753a6791c8d892fc148cb6f103 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-24crossgcc: Upgrade MPC to version 1.2.0Elyes HAOUAS
Change-Id: I8b754c2bbb18e38d2f8619f6ac8e1544702836ee Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44551 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24util/abuild: Don't pass kconfig output through headPatrick Georgi
Closing stdout early seems to have a detrimental effect on kconfig on a system under high load (e.g. when doing lots of builds in parallel). Change-Id: I6987f1deac596124c7b397bf7bc5a78d691cc538 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-08-24util/abuild: Delete temporary config in failure casePatrick Georgi
Change-Id: I9b6e6b6dcfbf2b1f43c98027acae8d9af61bd6d8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44624 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-21util/amdfwtool: Refactor APOB_NV requirementsMartin Roth
amdfwtool currently assumes that we MUST have an apob_nv area if we have an aopb. This is not required, so if neither the apob_nv size or base are specified, just move on. BUG=b:158363448 TEST=Build an image with no APOB_NV region. Dump regions to show that it's not there. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ibaeacd3dcdfd73f690df61c2a19d39bbb9dcc838 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44045 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-19util/abuild: Avoid another git submodule invocationPatrick Georgi
.xcompile is generated before the submodules handling, but there's no need for the submodules to be around, so skip here, too. Change-Id: I60205f65b124a09067de5ae50f066b5cf64733f2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-08-18crossgcc: Upgrade LLVM to version 10.0.1Elyes HAOUAS
Change-Id: I1d96654fd66a5972c6c5cc24311ca2d889866331 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39921 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-18crossgcc: Upgrade CMake to version 3.18.1Elyes HAOUAS
Release Notes: https://cmake.org/cmake/help/v3.18/release/3.18.html Change-Id: I20b75b7c29be838c3c168547bcab25ea5c1af462 Signed-off-by: Griffin98 <griffin98@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-08-18util/intelp2m: Add support for Cannonlake-LP SoCsMatt DeVillier
Add support for Cannonlake-LP SoCs (Whiskeylake-U, Coffeelake-U, Cometlake-U) as a separate parsing profile, copying the existing 'Sunrise' profile and adjusting for differences in reset mapping and GPIO macro generation Test: convert inteltool GPIO log dump into coreboot macros for an out-of-tree CML-U board. Change-Id: I86296697ee892af7aa0818fb608b6d68fad2f307 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-08-17crossgcc: Enable GCC to get asan shadow offset at runtimeHarshit Sharma
Unlike Linux kernel which has a static shadow region layout, we have multiple stages in coreboot and thus require a different shadow offset address. Unfortunately, GCC currently only supports adding a static shadow offset at compile time using -fasan-shadow-offset flag. For this reason, we enable GCC to determine asan shadow offset address at runtime using a callback function named __asan_shadow_offset(). This supersedes the need to specify this address at compile time. GCC then makes use of this shadow offset to protect stack buffers by inserting red zones around them. Some other benefits of having this GCC patch are: a. We can place the shadow region in a separate linker section with all its advantages like automatic fit insurance. This ensures if a platform doesn't have enough memory space to hold shadow region, the build will fail. (However, if we use a fixed shadow offset on a platform that actually doesn't have enough memory, it may still build without any errors.) b. We don't modify the memory layout compared to the current one, as we are placing the shadow region at the end of the space already occupied by the program. c. We can be much more flexible later if needed (thinking of other stages like bootblock). d. Since we are appending the shadow buffer to the region already occupied, we make efficient use of the limited memory available which is highly beneficial when using cache as ram. Further, we have made sure that if you compile you tree with ASan enabled but missed this patch, it will end up in the following compilation error: "invalid --param name 'asan-use-shadow-offset-callback'" So, you cannot accidentally enable the feature without having your compiler patched. Change-Id: I401631938532a406a6d41e77c6c9716b6b2bf48d Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-08-17crossgcc: Upgrade IASL to version 20200717Elyes HAOUAS
Summary of changes: https://acpica.org/node/183 Change-Id: Ib325fa5c37c32702c572ab56c99e1f8f785cbe53 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-08-17crossgcc: Upgrade Python to version 3.8.5Elyes HAOUAS
Change-Id: I660994ece28f04d97de2fe3a074ebcf93fb4d2f4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39148 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17crossgcc: Upgrade nasm to version 2.15.03Elyes HAOUAS
Change-Id: I4b38595cef72053f82216df43f3667abed4c1989 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42855 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17crossgcc: Upgrade binutils to version 2.35Elyes HAOUAS
Using "MAKEINFO = @MAKEINFO@", it fails to compile, so binutils-2.35_no-makeinfo.patch will change that to "MAKEINFO = true" Change-Id: I0ad01e5da34c96fee6a9b1a63897a9fb28471c75 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38666 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17crossgcc: Update MPFR to version 4.1.0Elyes HAOUAS
Changes: https://www.mpfr.org/mpfr-current/#changes Change-Id: I1df2c952229056b44d4c618cebe774ea27b55bd1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43360 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17crossgcc: Upgrade GMP to v6.2.0Elyes HAOUAS
gmp_freebsd-configure.patch is integrated in upstream so we don't need it anymore. Changes: https://gmplib.org/gmp6.2 Change-Id: I8404872f1b65e9173c1fcbd24d7da7bdd7937503 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38465 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-01util/ifdtool: Add Alderlake platform support under IFDv2Subrata Banik
Change-Id: Ief8ab6ad280d8a2625404c19d57cd2a24f23cf13 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39533 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-01util/ifdtool: Make JSL platform entry for lock_descriptorSubrata Banik
Change-Id: Ia2ddb4eceab29810b22766a0f241ba4b11e79538 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44057 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-29util/apcb: Strip SPD manufacturer informationRob Barnes
Strip manufacturer information from SPDs before injecting into APCB. This allows more flexibility around changing DRAM modules in the future. BUG=b:162098961 TEST=Boot, dump memory info Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I1bbc81a858f381f62dbd38bb57b3df0e6707d647 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-28util/intelp2m: Add Intel Pad to Macro utilityMaxim Polyakov
This patch adds a new utility for converting a pad configuration from the inteltool dump to the PAD_CFG_*() macros [1] for coreboot and GPIO config data structures for FSP/sdk2-platforms/slimbootloader [2,3]. Mirror: https://github.com/maxpoliak/pch-pads-parser.git [1] src/soc/intel/common/block/include/intelblocks/gpio_defs.h [2] https://slimbootloader.github.io/tools/index.html#gpio-tool [3] 3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Include/GpioSampleDef.h Change-Id: If3e3b523c4f63dc2f91e9ccd16934e3a1b6e21fa Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35643 Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28intelvbttool: Fix some typos in error messagesPeter Lemenkov
Change-Id: Id6298883c39c21179b13696dab630818b81026ff Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43905 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-27util/lint/Kconfig_lint: Update Naked BOOL reference to errorMartin Roth
The lint-stable makefile target only watches for errors in the Kconfig file, so has not protected additional "Naked" references to BOOL type Kconfig symbols from entering the tree. Update it to an error so that they can't continue coming into the codebase. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Icce2a9a627c4fbcaa220df18474cb8bfea8b2a8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/43826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26util/inteltool/gpio_names: Make group and community titles consistentBenjamin Doron
Consistency is good for scripting and automation. The lowercase "group" in Sunrise Point-LP, for example, was breaking pattern matching used in intelp2m. Change-Id: Iffa8a8ac9c17c5cbd8d7b838d9c703cae6a858b5 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43068 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26mb/lenovo: Prepend EC event number with 0x to denote hex notationPaul Menzel
Currently, the message below is printed, suggesting it’s decimal notation: coreboot-4.12-1530-g7acbd5fc45 Sun Jul 19 07:47:58 UTC 2020 smm starting (log level: 7)... EC event 48 GPI (mask 1000) Prepend 0x, so it’s clear it’s hexadecimal notation. EC event 0x48 Use the command below change all places: git grep -l 'EC event %02x' | xargs sed -i 's/EC event %02x/EC event %#02x/' Change-Id: I8d1e6434a0e550c5a19576f9f7fea05e7a812e49 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 01:11:49 +0000