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2020-05-07util/sconfig: Drop use of ref_count for chip_instanceFurquan Shaikh
chip_instance structure currently uses a ref_count to determine how many devices hold reference to that instance. If the count drops to zero, then it is assumed that the chip instance is a duplicate in override tree and has a similar instance that is already overriden in base device tree. ref_count is currently decremented whenever a device in override tree matches the one in base device tree and the registers from the override tree instance are copied over to the base tree instance. On the other hand, if a device in override tree does not match any device in base tree under a given parent, then the device is added to base tree and all the devices in its subtree that hold pointers to its parent chip instance are updated to point to the parent's chip instance in base tree. This is done as part of update_chip_pointers. However, there are a couple of issues that this suffers from: a) If a device is present only in override tree and it does not have its own chip (i.e. pointing to parent's chip instance), then it results in sconfig emiiting parent's chip instance (which can be the SoC chip instance) in static.c even though it is unused. This is because update_chip_pointers() does not call delete_chip_instance() before reassigning the chip instance pointer. b) If a device is added under root device only in the override tree and it does not have its own chip instance (i.e. uses SoC chip instance), then it results in sconfig emitting a copy of the SoC chip instance and setting that as chip_ops for this new device in the override tree. In order to fix the above issues, this change drops the ref_count field from chip_instance structure and instead adds a forwarding pointer `base_chip_instance`. This is setup as per the following rules: 1. If the instance belongs to base devicetree, base_chip_instance is set to NULL. 2. If the instance belongs to override tree, then it is set to its corresponding chip instance in base tree (if present), else set to NULL. State of base_chip_instance is then used when emitting chips and devices using the following rules: 1. If a chip_instance has non-NULL base_chip_instance, then that chip instance is not emitted to static.c 2. When emitting chip_ops for a device, base_chip_instance is used to determine the correct chip instance name to emit. BUG=b:155549176 TEST=Verified that the static.c file generated for base/override tree combination is correct when new devices without chips are added only to override tree. Change-Id: Idbb5b34f49bf874da3f30ebb6a6a0e2d8d091fe5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41007 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-07util/sconfig: Move chip instance id assignment to emit_chips()Furquan Shaikh
This change moves the assignment of id for chip instance from new_chip_instance() to emit_chips(). This is similar to the previous change for moving dev id assignment to happen much later. This ensures that the same ID gets assigned to a chip when adding support for device trees which makes it easier to compare static.c files. BUG=b:155549176 Change-Id: I3efa9af5ed91123675be42bce1cb389bad19cb62 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-07util/sconfig: Drop id from struct device maintained by sconfigFurquan Shaikh
This change drops the id field from struct device as used by sconfig. It was primarily used for generating unique device names. This was maintained within device structure so that the order in which the device tree entries were parsed is clear. Since the ids are assigned in parsing order, it is problematic when a device is moved from base devicetree to override tree. The entire parsing order changes which makes it really difficult to compare what really changed in static.c file. By moving the dev name assignment to happen later when doing pass0 of static.c generation, the difference in static.c file is minimized when adding support for override trees. BUG=b:155549176 Change-Id: I31870ace5a2fd7d5f95ab5e30d794c3bc959ed46 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-06treewide: replace GPLv2 long form headers with SPDX headerPatrick Georgi
This replaces GPLv2-or-later and GPLv2-only long form text with the short SPDX identifiers. Commands used: perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.*of.*the.*License.*or.*(at.*your.*option).*any.*later.*version.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-or-later */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation[.;,].+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This software is licensed under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation,.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) Change-Id: I7a746088a35633c11fc7ebe86006e96458a1abf8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-06treewide: move copyrights and authors to AUTHORSPatrick Georgi
Also split "this is part of" line from copyright notices. Change-Id: Ibc2446410bcb3104ead458b40a9ce7819c61a8eb Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-06treewide: Move "is part of the coreboot project" line in its own commentPatrick Georgi
That makes it easier to identify "license only" headers (because they are now license only) Script line used for that: perl -i -p0e 's|/\*.*\n.*This file is part of the coreboot project.*\n.*\*|/* This file is part of the coreboot project. */\n/*|' # ...filelist... Change-Id: I2280b19972e37c36d8c67a67e0320296567fa4f6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-05sconfig: Allow `register` entries below devices, tooNico Huber
Every device belongs to a chip. And we already keep that relation by inheriting the `.chip_info` pointer if downstream devices don't have another chip specified. So we can also allow to specify `register` settings at the device level. Change-Id: I44e6b95d0cd708fef69b152ebc46b869b2bb9205 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40803 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-04treewide: Drop ACPI_VIDEO_DEVICE macroAngel Pons
It was always defined to the same value, and only used twice. Change-Id: I2736eb7ea2cf15475f7bb99d7d12450730eb8be0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40864 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-01util/intelmetool: Fix 16-bit read/write PCI_COMMAND registerElyes HAOUAS
Change-Id: I3a00db217ce7acd11f979e64bb5d417a8bfc8717 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-04-29util/kconfig: Remove miniconfig scriptPatrick Georgi
It replicates the functionality of savedefconfig because back when the script was added, savedefconfig didn't work for us. It now does, is the official way of doing things, is recommended in our documentation and is also a fair bit faster. Change-Id: Ia8e0377537ff7cd638c564037ea6a77b01a87243 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-28Documentation: Spell vboot all lowercasePatrick Rudolph
Update all occurrences of vboot and spell it lowercase. Change-Id: I432b0db8a3dda43b71844e557a3d89180f25f1c3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-04-22util/scripts/ucode_h_to_bin.sh: Fix .inc-lines with just commentWerner Zeh
There are microcodes in .inc format out in the wild which contains lines with just a comment. So these files look like the following example: ; External header dd 000000001h dd 00000001bh ... ; Data dd 000000000h ... The lines with just a comment starts with a ';' and will break the current awk formatting which is performed to reformat the content into C code style. As we are just interested in the data we can simply drop all lines that start with a ';' which sed can do pretty easy. Change-Id: I9ff5db51667672cffd9d776fb9497962b4a6083a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-22util/scripts/ucode_h_to_bin.sh: Drop disruptive quotesWerner Zeh
The double quotes around the remaining shell parameters '${@:2}' causes that the provided *.h files in $(CONFIG_CPU_MICROCODE_HEADER_FILES), which is a space separated list, cannot be broken down to every single file as needed but stay as a single parameter in the for-loop. Therefore, the called function 'include_file' will get a single parameter with all files which will lead to a broken C code in terms of a wrong #include-syntax. This causes the script to fail. To fix this remove the double quotes which works just fine. Change-Id: Iab7b0dc8d850973d6af764899907d383e9ec7743 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-22util/scripts/ucode_h_to_bin.sh: Replace whitespace with TABsWerner Zeh
Newly added code in commit CB:25546 contains spaces instead of TABs for line indent. Replace every 4 spaces by a single TAB to match our coding guides. Change-Id: Ie3633bb42643f4abb5f1a8827a7dc2c9e023d6aa Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-20Doc,util: Update list of utilitiesJacob Garber
Remove entries for old utilities and add entries for new ones. Generated using util/util_readme, with some tweaks to preserve the markdown. Change-Id: I3a4d8a6bf15a677aa07aa72b8809328110fb72da Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-20util/cbfstool: Allow use of non-ASCII longoptFurquan Shaikh
CB:29744 ("util/cbfstool: Add optional argument ibb") added support for non-ASCII characters for long_options. However, there is a check later on which errors out since this character is not one of the commands[i].optstring. This change adds a function valid_opt() which does the following things: 1. Checks if the returned optchar is among the list of optstring supported by the command. 2. Checks if the returned optchar is a valid non-ASCII option. Currently, we do not maintain a list of non-ASCII options supported by each command. So, this function returns true if the optchar returned by getopt_long falls within the allowed range. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I27a4f9af9850e4c892573202904fa9e5fbb64df6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-04-16autoport: use GMA_STATIC_DISPLAYSIru Cai
Change-Id: Ie988b2caeb2cdc07a3d6466b7ae3501df469ef41 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-16autoport: Support bigger ACPI tablesIru Cai
DSDT can be bigger than 0x10000 bytes, so increase the space up to 1MB for an ACPI table and support lines in acpidump.log with address higher than 0x10000. Change-Id: Iaadcfd0964c1c516e9e39d6cbfe41ec9a8c45e9d Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31759 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14src/Kconfig: enable USE_BLOBS by defaultFelix Held
To provide sane defaults for most of the user base, this patch switches on the USE_BLOBS option by default. Since it only changes the default, this behaviour can still be easily disabled. With this abuild doesn't have to select USE_BLOBS any more, so what abuild tests becomes the coreboot default again. Change-Id: Ia0632b9ae7a1f212a8640b3faec2695d17d238c5 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-13util/lint: Accept "GPL-2.0-only WITH Linux-syscall-note" licensesRajat Jain
The Linux kernel UAPI header files are licensed under /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ Allows files with this license to be included in coreboot. For more details about this particular license: https://www.kernel.org/doc/html/v4.17/process/license-rules.html https://spdx.org/licenses/Linux-syscall-note.html Change-Id: I4f0f8d36c637a66a6999a18321fdbc4c42d5751e Signed-off-by: Rajat Jain <rajatja@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-10util/nvramtool: Remove 2nd initializationElyes HAOUAS
'result' is already defined as 'unsigned long long result = 0;' so no need to re-write 'result = 0;'. Change-Id: Ie897453fb5e7b09af755ce8d61ee8e80943ffc1c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-05fsp2_0: Clean up around `config FSP_USE_REPO`Nico Huber
We can make our lifes much easier by removing its dependency on `ADD_FSP_BINARIES`. Instead, we imply the latter if the repository is to be used. We can also hide a lot of unnecessary prompts in this case. Also, remove default overrides and selects for the two that are now unnecessary. Change-Id: I8538f2e966adc9da0fbea2250c954d86e42dfeb3 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39882 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-30util/sconfig: emit NULL sibling fieldsAaron Durbin
It's helpful to see the sibling field, even when it's NULL, when debugging the static.c output from a devictree.cb file. Ensure the NULL fields are emitted for fullness. Change-Id: Ib6d5b8164769a6512e762d5a525c7df1f429c866 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-27amdfwtool: Allow for up to 16 APCB entriesRob Barnes
Increase the number of allowed APCB entries in amdfwtool. BUG=b:150455865 TEST=Boot Trembyle BRANCH=None Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: Ibdd2f2b9766735bc9aba98b5216e589b6cace238 Reviewed-on: https://chromium-review.googlesource.com/2084944 Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39861 Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-25util/board-status: Reject logs from dirty imagesPaul Menzel
Currently, there are a lot of uploads in the board status repository, where the logs say, that the coreboot image or payload were built from a dirty source tree. Add a check to reject such uploads. Change-Id: I920e26a10f74e1f3b9b4e5f8c9284c59692a519b Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-24drivers/intel/gma: Ditch `link_frequency_270_mhz` settingNico Huber
The `link_frequency_270_mhz` setting was originally used by the native graphics init code for Sandy/Ivy Bridge, which is long gone. The value of this information (which board had it set) is questionable. The only board that had an LVDS panel and set it to 0 was the ThinkPad L520, where native graphics init was never reported to work. Also, the native graphics init only used it for calculations, but never confi- gured the hardware to use a specific frequency. A look into the docu- mentation also doesn't reveal any straps that could be used to confi- gure it. Change-Id: Ieceaa13e4529096a8ba9036479fd84969faebd14 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39763 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-24util/inteltool: add inteltool path to include pathMichael Niewöhner
Add the inteltool path to the include path to be able to avoid ugly include hacks like `#include "../inteltool.h"`. Change-Id: Id363fa20fe3b52248a224ca14b2626a8e3ce44a2 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39744 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-23Doc/security/vboot: Add a script generated device listMarcello Sylvester Bauer
Add a script generated list of vboot enabled devices to the documentation. Add a entry to the release checklist. Change-Id: Ibb57d26c5f0cb8efd27ca9a97fd762c25b566f93 Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-23cbfstool: Build vboot libraryYu-Ping Wu
Currently cbfstool cherry-picks a few files from vboot and hopes these files will work standalone without any dependencies. This is pretty brittle (for example, CL:2084062 will break it), and could be improved by building the whole vboot library and then linking against it. Therefore, this patch creates a new target $(VBOOT_HOSTLIB) and includes it as a dependency for cbfstool and ifittool. To prevent building the vboot lib twice (one for cbfstool and the other for futility) when building coreboot tools together, add the variable 'VBOOT_BUILD' in Makefile to define a shared build path among different tools so that vboot files don't need to be recompiled. Also ignore *.o.d and *.a for vboot library. BRANCH=none BUG=none TEST=make -C util/cbfstool TEST=make -C util/futility TEST=Run 'make tools' and make sure common files such as 2sha1.c are compiled only once TEST=emerge-nami coreboot-utils Change-Id: Ifc826896d895f53d69ea559a88f75672c2ec3146 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-21util/inteltool: use read* macros instead of pointersMichael Niewöhner
Switch to using read* macros instead of pointers. Change-Id: I1fe54b496a5998597b79cdd7108f3a4075744a78 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-20util/inteltool: powermgt: add code for dumping config registersMichael Niewöhner
This adds the code required to dump config registers. Change-Id: Ic78f847ba07240c112492229f9a23f9a88275ad9 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-20util/scripts/gerrit-rebase: Fix shell invocationPatrick Georgi
The single apostrophe confuses the shell that's calling the command. Change-Id: I7d3183e9a612de0121b2d208c06a45645b8d67f6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-20util/autoport: Emit SPDX license headersAngel Pons
Change-Id: I8896b6c92c3126cc611e47b39d596108b90c6bf2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-20util/xcompile: Split $CFLAGS_GCCNico Huber
Split common flags that are not specific to the C language out of $CFLAGS_GCC into $FLAGS_GCC. This way, we can test for C specific flags, too, without adding them to $ADAFLAGS_*. Currently this is done for `-Wno-address-of-packed-member` which only applies to C. Change-Id: Ib793c62656efb07b6e5b3385f1ed1c96a40efd1d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39633 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-19util/bincfg: Add DDR4 SPD specRob Barnes
Additionally provide a simple script for decoding spd hex files using bincfg. BUG=b:148561711 TEST=Decoded spd files in zork BRANCH=None Change-Id: Ic62868d59e075fd6816d7be55cc935e3e3f82499 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://chromium-review.googlesource.com/2067697 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-03-18util/lint/spelling.txt: Disable `afe`Angel Pons
Uppercase `AFE` is an acronym for `Analog Front-End`. As it is a valid spelling, comment out its entry to prevent false positives. Change-Id: Ib8612d970d33d4955c572838bda217cfdb49dfe6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-18util/lint/spelling.txt: Explain the commented-out entriesAngel Pons
If they were removed instead, it would be too easy to end up adding them back again. They are kept in a comment so that they can be tracked. Also, explain why these two entries have been commented out. Change-Id: I8225944b5e3d1e022af169dda33e0344d4c3bccd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-18util/inteltool: powermgt: make Sunrise Point dumping workMichael Niewöhner
The existing Sunrise Point ids are assigned to the wrong implementation, which would never work for these chipsets. Assign them to the right dumping implementation, which works for both Sunrise Point PCH-H and PCH-LP. This also adds some missing device ids from doc#332691-003EN and doc#334659-005. Change-Id: Id102ef3809d675dc9a915d2cb3062e093487fa27 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-18util/autoport: Correct formatting issuesAngel Pons
There is no need to use hexadecimal values in azalia codec IDs, nor need to print a redundant "LPC bridge PCI-LPC bridge" comment. Change-Id: I6658051c7a3d5b65a86ccca8bab7834bf4628a16 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-03-18util/inteltool: Makefile: add src/arch to includes.Michael Niewöhner
Add src/arch to includes. Change-Id: I157178a055a259e40c57f3915671d3b8966fbb96 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-17util/amdfwtool: Fix file open error msgEric Peers
Print out the name of the file that failed to open. BUG=none TEST=rerun build-board.sh with missing files BRANCH=none Signed-off-by: Eric Peers <epeers@google.com> Change-Id: Id8543f25ea827fc8764e0315434b834e65bfa7fb Reviewed-on: https://chromium-review.googlesource.com/2090667 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-17util/inteltool: spi: add a bunch of missing chipsets to print_bioscntlMichael Niewöhner
Add a bunch of missing chipsets to print_bioscntl. Change-Id: I96c010a1d64dcf5296f78a6decd1a218aba4b04f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-17util/inteltool: add code for dumping LPC registersMichael Niewöhner
This adds the implementation for dumping LPC registers Change-Id: I50ae4913933f7594f0d63ce3f752302ed5c461e2 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39517 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16util/inteltool: ahci: add Sunrise Point config and SIR registersMichael Niewöhner
This adds the Sunrise Point AHCI config and SIR registers from doc#332691-003EN. Change-Id: Id4a462d625194a6ccfdb88fb415d5eb278f2900a Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39506 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16util/inteltool: ahci: add code for dumping config and SIR registersMichael Niewöhner
This adds the code required to dump config and SIR registers. Change-Id: I3726c52d415ff4dd6b19513b310f11254f7fbf92 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39560 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16util/inteltool: ahci: rework AHCIMichael Niewöhner
Rework AHCI to align the code with the rest of inteltool. Change-Id: I37116f8e269d0376e147dd6de7365c45ac90bda0 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39504 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16inteltool: add support for CannonPoint-LPMatt DeVillier
Add support for CannonPoint-LP U Premium (CoffeeLake-U and WhiskeyLake-U) GPIO info taken from: - Intel doc #337867-002 - coreboot soc/intel/cannonlake/include/soc/gpio_soc_defs.h Test: Read GPIOs from out-of-tree WhiskeyLake-U board Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: I70f23eec71abb8d7c2a7a109c9e760bb31dee2ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/39393 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16util/inteltool: Split GPIO community switch-case into its own functionJohanna Schander
So far printing the GPIO groups chose the community definition. As the list of supported platforms grows the massive switch case gets repetetive and hinders the readers view. It also reduces the ability to reuse the code in a potential libinteltool. To takle these issues the detection logic was split into its own function. Change-Id: I215c1b7d6ec164b8afd9489ebd54b63d3df50cb9 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38631 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16util/inteltool: Move Denverton definitions into their own headerJohanna Schander
So far all group and community definitions live in one big c file. This 2500 line file slowly grows to a size, where readability is lost. Also the definitions are not reusable in a potential libinteltool. This commit moved the Denverton definitions into its own header. Change-Id: I6ce672c24059b9f3a4a984766184066f14df3013 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38630 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christoph Pomaska <github@slrie.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 09:48:20 +0000