From 021fa78bcae3224ca8bcdb7a0f5acbd5e90ab897 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 16 Aug 2013 06:34:04 +0300 Subject: usbdebug: Change reference to EHCI BAR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change the defines, as follow-up patch will replace use of constant CONFIG_EHCI_BAR. Change-Id: I44ff77cb7a2826f3b43d8d46440fd4482a29d18c Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/3875 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/southbridge/amd/agesa/hudson/enable_usbdebug.c | 9 +++++---- src/southbridge/amd/sb700/enable_usbdebug.c | 9 +++++---- src/southbridge/amd/sb800/enable_usbdebug.c | 9 +++++---- 3 files changed, 15 insertions(+), 12 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c index 147056ddc4..dda29c1724 100644 --- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c +++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c @@ -30,19 +30,20 @@ #define HUDSON_DEVN_BASE 0 #endif -#define EHCI_EOR (CONFIG_EHCI_BAR + 0x20) -#define DEBUGPORT_MISC_CONTROL (EHCI_EOR + 0x80) +#define EHCI_EOR 0x20 +#define DEBUGPORT_MISC_CONTROL 0x80 void set_debug_port(unsigned int port) { + u32 base_regs = CONFIG_EHCI_BAR + EHCI_EOR; u32 reg32; /* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */ - reg32 = read32(DEBUGPORT_MISC_CONTROL); + reg32 = read32(base_regs + DEBUGPORT_MISC_CONTROL); reg32 &= ~(0xf << 28); reg32 |= (port << 28); reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */ - write32(DEBUGPORT_MISC_CONTROL, reg32); + write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32); } diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c index 00eb4d924b..3aaf7c82bf 100644 --- a/src/southbridge/amd/sb700/enable_usbdebug.c +++ b/src/southbridge/amd/sb700/enable_usbdebug.c @@ -27,19 +27,20 @@ #include #include "sb700.h" -#define EHCI_EOR (CONFIG_EHCI_BAR + 0x20) -#define DEBUGPORT_MISC_CONTROL (EHCI_EOR + 0x80) +#define EHCI_EOR 0x20 +#define DEBUGPORT_MISC_CONTROL 0x80 void set_debug_port(unsigned int port) { + u32 base_regs = CONFIG_EHCI_BAR + EHCI_EOR; u32 reg32; /* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */ - reg32 = read32(DEBUGPORT_MISC_CONTROL); + reg32 = read32(base_regs + DEBUGPORT_MISC_CONTROL); reg32 &= ~(0xf << 28); reg32 |= (port << 28); reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */ - write32(DEBUGPORT_MISC_CONTROL, reg32); + write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32); } /* diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c index 8b80b3770f..09f742915d 100644 --- a/src/southbridge/amd/sb800/enable_usbdebug.c +++ b/src/southbridge/amd/sb800/enable_usbdebug.c @@ -30,19 +30,20 @@ #define SB800_DEVN_BASE 0 #endif -#define EHCI_EOR (CONFIG_EHCI_BAR + 0x20) -#define DEBUGPORT_MISC_CONTROL (EHCI_EOR + 0x80) +#define EHCI_EOR 0x20 +#define DEBUGPORT_MISC_CONTROL 0x80 void set_debug_port(unsigned int port) { + u32 base_regs = CONFIG_EHCI_BAR + EHCI_EOR; u32 reg32; /* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */ - reg32 = read32(DEBUGPORT_MISC_CONTROL); + reg32 = read32(base_regs + DEBUGPORT_MISC_CONTROL); reg32 &= ~(0xf << 28); reg32 |= (port << 28); reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */ - write32(DEBUGPORT_MISC_CONTROL, reg32); + write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32); } -- cgit v1.2.3