From 035876c4ddb0c9cb92b867bc329f74f1021bf0f7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 27 Feb 2019 08:15:01 +0200 Subject: mb/intel/saddlebrook: Fix 2nd DIMM slot MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Assumed broken during review and rebase. The SPD at address 0x52 will appear at index 1. Change-Id: I213853d2b981294554d8d1b254da476905a41c13 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/31630 Tested-by: build bot (Jenkins) Reviewed-by: PraveenX Hodagatta Pranesh Reviewed-by: Angel Pons --- src/mainboard/intel/saddlebrook/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c index 5b4732a8c7..d19629cf9e 100644 --- a/src/mainboard/intel/saddlebrook/romstage.c +++ b/src/mainboard/intel/saddlebrook/romstage.c @@ -56,7 +56,7 @@ void mainboard_memory_init_params( printk(BIOS_SPEW, "spd block length: 0x%08x\n", blk.len); memory_params->MemorySpdPtr00 = (UINT32) blk.spd_array[0]; - memory_params->MemorySpdPtr10 = (UINT32) blk.spd_array[2]; + memory_params->MemorySpdPtr10 = (UINT32) blk.spd_array[1]; printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n", memory_params->MemorySpdPtr00); printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n", -- cgit v1.2.3