From 04b28608087dd12447f8f5f7d891745e4864aff1 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 17 May 2021 13:54:24 +0200 Subject: mb/asus/p8h61-m_lx/devicetree.cb: Rewrite number in hex Done for consistency with the other variants. Tested with BUILD_TIMELESS=1, Asus P8H61-M LX remains identical. Change-Id: I440706f6fa11d3c2410c445cb7e946c063578c4e Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/54376 Tested-by: build bot (Jenkins) Reviewed-by: Tristan Corrick --- src/mainboard/asus/h61-series/variants/p8h61-m_lx/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/devicetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/devicetree.cb index 276119051c..05b8e38f82 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/devicetree.cb +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/devicetree.cb @@ -19,7 +19,7 @@ chip northbridge/intel/sandybridge device pci 02.0 on end # VGA controller chip southbridge/intel/bd82x6x - register "c2_latency" = "101" + register "c2_latency" = "0x0065" register "gen1_dec" = "0x00000295" # Super I/O HWM register "sata_port_map" = "0x33" register "spi_lvscc" = "0x2005" -- cgit v1.2.3