From 0b80bd1cf4510b3a4f028b5bb5570a2806c22320 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 9 Sep 2017 19:46:44 +0200 Subject: nb/intel/i945: Clear timeout bits after disabling watchdog MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Even with the watchdog disabled, these bits influence other hardware blocks (e.g. SECOND_TO_STS stops SMBus block transfers, possibly yet before they started). Change-Id: If9f93fcc96827bb192148a80b4476796c9358a7a Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/21471 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Reviewed-by: Kyösti Mälkki --- src/northbridge/intel/i945/early_init.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 1d473d3104..0abd42eec8 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -170,6 +170,8 @@ static void i945_setup_bars(void) printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ + outw((1 << 3), DEFAULT_PMBASE | 0x60 | 0x04); /* clear timeout */ + outw((1 << 1), DEFAULT_PMBASE | 0x60 | 0x06); /* clear 2nd timeout */ printk(BIOS_DEBUG, " done.\n"); /* Enable upper 128bytes of CMOS */ -- cgit v1.2.3