From 14b7e655bf876e8389bc83bc30e702ca3c58e845 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 17 May 2021 12:50:55 +0200 Subject: mb/asus/p8h61-m_pro: Transform into variant setup Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8H61-M PRO remains identical when not adding the .config file in it. Change-Id: Iaa53a8a1b75f4c7359e32c6cd8c8a488c5763bbe Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/54373 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- MAINTAINERS | 5 - src/mainboard/asus/h61-series/Kconfig | 8 + src/mainboard/asus/h61-series/Kconfig.name | 12 ++ .../h61-series/variants/p8h61-m_pro/board_info.txt | 6 + .../h61-series/variants/p8h61-m_pro/cmos.default | 6 + .../h61-series/variants/p8h61-m_pro/cmos.layout | 66 ++++++++ .../asus/h61-series/variants/p8h61-m_pro/data.vbt | Bin 0 -> 3902 bytes .../h61-series/variants/p8h61-m_pro/devicetree.cb | 111 +++++++++++++ .../h61-series/variants/p8h61-m_pro/early_init.c | 57 +++++++ .../variants/p8h61-m_pro/gma-mainboard.ads | 21 +++ .../asus/h61-series/variants/p8h61-m_pro/gpio.c | 183 +++++++++++++++++++++ .../h61-series/variants/p8h61-m_pro/hda_verb.c | 36 ++++ src/mainboard/asus/p8h61-m_pro/Kconfig | 32 ---- src/mainboard/asus/p8h61-m_pro/Kconfig.name | 2 - src/mainboard/asus/p8h61-m_pro/Makefile.inc | 6 - src/mainboard/asus/p8h61-m_pro/acpi/ec.asl | 0 src/mainboard/asus/p8h61-m_pro/acpi/platform.asl | 16 -- src/mainboard/asus/p8h61-m_pro/acpi/superio.asl | 3 - src/mainboard/asus/p8h61-m_pro/board_info.txt | 6 - src/mainboard/asus/p8h61-m_pro/cmos.default | 6 - src/mainboard/asus/p8h61-m_pro/cmos.layout | 66 -------- src/mainboard/asus/p8h61-m_pro/data.vbt | Bin 3902 -> 0 bytes src/mainboard/asus/p8h61-m_pro/devicetree.cb | 111 ------------- src/mainboard/asus/p8h61-m_pro/dsdt.asl | 27 --- src/mainboard/asus/p8h61-m_pro/early_init.c | 57 ------- src/mainboard/asus/p8h61-m_pro/gma-mainboard.ads | 21 --- src/mainboard/asus/p8h61-m_pro/gpio.c | 183 --------------------- src/mainboard/asus/p8h61-m_pro/hda_verb.c | 36 ---- 28 files changed, 506 insertions(+), 577 deletions(-) create mode 100644 src/mainboard/asus/h61-series/variants/p8h61-m_pro/board_info.txt create mode 100644 src/mainboard/asus/h61-series/variants/p8h61-m_pro/cmos.default create mode 100644 src/mainboard/asus/h61-series/variants/p8h61-m_pro/cmos.layout create mode 100644 src/mainboard/asus/h61-series/variants/p8h61-m_pro/data.vbt create mode 100644 src/mainboard/asus/h61-series/variants/p8h61-m_pro/devicetree.cb create mode 100644 src/mainboard/asus/h61-series/variants/p8h61-m_pro/early_init.c create mode 100644 src/mainboard/asus/h61-series/variants/p8h61-m_pro/gma-mainboard.ads create mode 100644 src/mainboard/asus/h61-series/variants/p8h61-m_pro/gpio.c create mode 100644 src/mainboard/asus/h61-series/variants/p8h61-m_pro/hda_verb.c delete mode 100644 src/mainboard/asus/p8h61-m_pro/Kconfig delete mode 100644 src/mainboard/asus/p8h61-m_pro/Kconfig.name delete mode 100644 src/mainboard/asus/p8h61-m_pro/Makefile.inc delete mode 100644 src/mainboard/asus/p8h61-m_pro/acpi/ec.asl delete mode 100644 src/mainboard/asus/p8h61-m_pro/acpi/platform.asl delete mode 100644 src/mainboard/asus/p8h61-m_pro/acpi/superio.asl delete mode 100644 src/mainboard/asus/p8h61-m_pro/board_info.txt delete mode 100644 src/mainboard/asus/p8h61-m_pro/cmos.default delete mode 100644 src/mainboard/asus/p8h61-m_pro/cmos.layout delete mode 100644 src/mainboard/asus/p8h61-m_pro/data.vbt delete mode 100644 src/mainboard/asus/p8h61-m_pro/devicetree.cb delete mode 100644 src/mainboard/asus/p8h61-m_pro/dsdt.asl delete mode 100644 src/mainboard/asus/p8h61-m_pro/early_init.c delete mode 100644 src/mainboard/asus/p8h61-m_pro/gma-mainboard.ads delete mode 100644 src/mainboard/asus/p8h61-m_pro/gpio.c delete mode 100644 src/mainboard/asus/p8h61-m_pro/hda_verb.c diff --git a/MAINTAINERS b/MAINTAINERS index 29d0f71a18..860b79c9f7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -200,11 +200,6 @@ M: Tristan Corrick S: Maintained F: src/mainboard/asus/p8h61-m_lx/ -ASUS P8H61-M PRO MAINBOARD -M: Angel Pons -S: Maintained -F: src/mainboard/asus/p8h61-m_pro/ - ASUS P8Z77-M PRO MAINBOARD M: Vlado Cibic S: Maintained diff --git a/src/mainboard/asus/h61-series/Kconfig b/src/mainboard/asus/h61-series/Kconfig index 2ef6642788..959580f48e 100644 --- a/src/mainboard/asus/h61-series/Kconfig +++ b/src/mainboard/asus/h61-series/Kconfig @@ -20,13 +20,21 @@ config MAINBOARD_DIR config VARIANT_DIR string default "p8h61-m_lx3_r2_0" if BOARD_ASUS_P8H61_M_LX3_R2_0 + default "p8h61-m_pro" if BOARD_ASUS_P8H61_M_PRO config MAINBOARD_PART_NUMBER string default "P8H61-M LX3 R2.0" if BOARD_ASUS_P8H61_M_LX3_R2_0 + default "P8H61-M PRO" if BOARD_ASUS_P8H61_M_PRO config DEVICETREE string default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" +config CMOS_DEFAULT_FILE + default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(CONFIG_VARIANT_DIR)/cmos.default" + +config CMOS_LAYOUT_FILE + default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(CONFIG_VARIANT_DIR)/cmos.layout" + endif diff --git a/src/mainboard/asus/h61-series/Kconfig.name b/src/mainboard/asus/h61-series/Kconfig.name index 14ca540753..d876aea3b7 100644 --- a/src/mainboard/asus/h61-series/Kconfig.name +++ b/src/mainboard/asus/h61-series/Kconfig.name @@ -6,3 +6,15 @@ config BOARD_ASUS_P8H61_M_LX3_R2_0 select REALTEK_8168_RESET select RT8168_SET_LED_MODE select SUPERIO_NUVOTON_NCT6779D + +config BOARD_ASUS_P8H61_M_PRO + bool "P8H61-M PRO" + select BOARD_ASUS_H61_SERIES + select BOARD_ROMSIZE_KB_4096 + select DRIVERS_ASMEDIA_ASPM_BLACKLIST + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select MAINBOARD_HAS_LPC_TPM + select REALTEK_8168_RESET + select RT8168_SET_LED_MODE + select SUPERIO_NUVOTON_NCT6776 diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/board_info.txt b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/board_info.txt new file mode 100644 index 0000000000..febee582b2 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: https://www.asus.com/Motherboards/P8H61M_PRO +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/cmos.default b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/cmos.default new file mode 100644 index 0000000000..6f3cec735e --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/cmos.default @@ -0,0 +1,6 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Enable +nmi=Enable +sata_mode=AHCI +gfx_uma_size=32M diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/cmos.layout b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/cmos.layout new file mode 100644 index 0000000000..8c6a055ca3 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/cmos.layout @@ -0,0 +1,66 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +421 1 e 9 sata_mode + +# coreboot config options: cpu + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M + +# ----------------------------------------------------------------- +checksums + +checksum 392 439 984 diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/data.vbt b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/data.vbt new file mode 100644 index 0000000000..114a840660 Binary files /dev/null and b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/data.vbt differ diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/devicetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/devicetree.cb new file mode 100644 index 0000000000..a0221fe761 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/devicetree.cb @@ -0,0 +1,111 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/sandybridge + device cpu_cluster 0 on + chip cpu/intel/model_206ax + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" + device lapic 0 on end + device lapic 0xacac off end + end + end + device domain 0 on + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe bridge for discrete graphics (PCIEX16_1) + device pci 02.0 on end # Internal graphics VGA controller + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "gen1_dec" = "0x000c0291" # HWM + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x33" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1c.0 on end # PCIe x1 Port (PCIEX1_1) + device pci 1c.1 on end # PCIe x1 Port (PCIEX1_2) + device pci 1c.2 on # Realtek RTL8111E Ethernet Controller + chip drivers/net + register "customized_leds" = "0x00f6" + register "wake" = "9" + device pci 00.0 on end + end + end + device pci 1c.3 on end # ASMedia ASM1042 USB3 Controller + device pci 1c.4 on end # PCIe x1 Port, x16 size (PCIEX16_2) + device pci 1c.5 on end # ASMedia ASM1062 SATA Controller + device pci 1c.6 off end # Unused PCIe Port + device pci 1c.7 off end # Unused PCIe Port + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 5 + drq 0x74 = 4 + irq 0xf0 = 0x3c + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # COM2, IR + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6-9 + device pnp 2e.8 off end # WDT1, GPIO0, GPIO1, GPIOA + device pnp 2e.9 off end # GPIO2-5 + device pnp 2e.a on # ACPI + irq 0xe5 = 0x06 + irq 0xe6 = 0x0c + irq 0xe7 = 0x11 + irq 0xf0 = 0x00 + irq 0xf2 = 0x5d + end + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + io 0x62 = 0x0000 + end + device pnp 2e.d on end # VID + device pnp 2e.e off end # CIR WAKE-UP + device pnp 2e.f on # GPIO Push-Pull or Open-drain + irq 0xf0 = 0x9d + end + device pnp 2e.14 off end # SVID + device pnp 2e.16 on # Deep Sleep + io 0x30 = 0x20 + end + device pnp 2e.17 on # GPIOA + irq 0xe0 = 0xff + irq 0xe1 = 0xff + irq 0xe2 = 0xff + irq 0xe3 = 0xff + irq 0xe5 = 0xff + end + end + chip drivers/pc80/tpm + device pnp 4e.0 on end # TPM + end + end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/early_init.c b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/early_init.c new file mode 100644 index 0000000000..05e87c1c68 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/early_init.c @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + /* Enable UART */ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin states. */ + pnp_write_config(GLOBAL_DEV, 0x1c, 0x83); + pnp_write_config(GLOBAL_DEV, 0x24, 0x30); + pnp_write_config(GLOBAL_DEV, 0x27, 0x40); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x20); + + /* Power RAM in S3. */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x10); + + pnp_set_logical_device(SERIAL_DEV); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/gma-mainboard.ads b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/gma-mainboard.ads new file mode 100644 index 0000000000..ddbbd82bf7 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/gma-mainboard.ads @@ -0,0 +1,21 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- For a three-pipe setup, bandwidth is shared between the 2nd and + -- the 3rd pipe. Thus, probe ports that likely have a high-resolution + -- display attached first. + + ports : constant Port_List := + (HDMI3, -- mainboard HDMI port + HDMI1, -- mainboard DVI-D port + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/gpio.c b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/gpio.c new file mode 100644 index 0000000000..d57a0f352a --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/gpio.c @@ -0,0 +1,183 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, /* wired to GPU Boost switch */ + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/hda_verb.c b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/hda_verb.c new file mode 100644 index 0000000000..9f77ac7f9e --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/hda_verb.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ + 0x10438444, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x10438444), + AZALIA_PIN_CFG(0, 0x11, 0x99430140), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x01012014), + AZALIA_PIN_CFG(0, 0x18, 0x01a19850), + AZALIA_PIN_CFG(0, 0x19, 0x02a19c60), + AZALIA_PIN_CFG(0, 0x1a, 0x0181305f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4005e601), + AZALIA_PIN_CFG(0, 0x1e, 0x01456130), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x58560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/p8h61-m_pro/Kconfig b/src/mainboard/asus/p8h61-m_pro/Kconfig deleted file mode 100644 index 56745496db..0000000000 --- a/src/mainboard/asus/p8h61-m_pro/Kconfig +++ /dev/null @@ -1,32 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -if BOARD_ASUS_P8H61_M_PRO - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select BOARD_ROMSIZE_KB_4096 - select DRIVERS_ASMEDIA_ASPM_BLACKLIST - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select HAVE_CMOS_DEFAULT - select HAVE_OPTION_TABLE - select INTEL_GMA_HAVE_VBT - select MAINBOARD_HAS_LIBGFXINIT - select MAINBOARD_HAS_LPC_TPM - select NORTHBRIDGE_INTEL_SANDYBRIDGE - select REALTEK_8168_RESET - select RT8168_SET_LED_MODE - select SERIRQ_CONTINUOUS_MODE - select SOUTHBRIDGE_INTEL_BD82X6X - select SUPERIO_NUVOTON_NCT6776 - select USE_NATIVE_RAMINIT - -config MAINBOARD_DIR - string - default "asus/p8h61-m_pro" - -config MAINBOARD_PART_NUMBER - string - default "P8H61-M PRO" - -endif # BOARD_ASUS_P8H61_M_PRO diff --git a/src/mainboard/asus/p8h61-m_pro/Kconfig.name b/src/mainboard/asus/p8h61-m_pro/Kconfig.name deleted file mode 100644 index a19d4e5203..0000000000 --- a/src/mainboard/asus/p8h61-m_pro/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ASUS_P8H61_M_PRO - bool "P8H61-M PRO" diff --git a/src/mainboard/asus/p8h61-m_pro/Makefile.inc b/src/mainboard/asus/p8h61-m_pro/Makefile.inc deleted file mode 100644 index e402ffa605..0000000000 --- a/src/mainboard/asus/p8h61-m_pro/Makefile.inc +++ /dev/null @@ -1,6 +0,0 @@ -bootblock-y += gpio.c -romstage-y += gpio.c - -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -bootblock-y += early_init.c -romstage-y += early_init.c diff --git a/src/mainboard/asus/p8h61-m_pro/acpi/ec.asl b/src/mainboard/asus/p8h61-m_pro/acpi/ec.asl deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/src/mainboard/asus/p8h61-m_pro/acpi/platform.asl b/src/mainboard/asus/p8h61-m_pro/acpi/platform.asl deleted file mode 100644 index bbee0a2787..0000000000 --- a/src/mainboard/asus/p8h61-m_pro/acpi/platform.asl +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method(_PTS,1) -{ -} - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - Return(Package(){0,0}) -} diff --git a/src/mainboard/asus/p8h61-m_pro/acpi/superio.asl b/src/mainboard/asus/p8h61-m_pro/acpi/superio.asl deleted file mode 100644 index ee2eabeb75..0000000000 --- a/src/mainboard/asus/p8h61-m_pro/acpi/superio.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include diff --git a/src/mainboard/asus/p8h61-m_pro/board_info.txt b/src/mainboard/asus/p8h61-m_pro/board_info.txt deleted file mode 100644 index febee582b2..0000000000 --- a/src/mainboard/asus/p8h61-m_pro/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Category: desktop -Board URL: https://www.asus.com/Motherboards/P8H61M_PRO -ROM package: DIP-8 -ROM protocol: SPI -ROM socketed: y -Flashrom support: y diff --git a/src/mainboard/asus/p8h61-m_pro/cmos.default b/src/mainboard/asus/p8h61-m_pro/cmos.default deleted file mode 100644 index 6f3cec735e..0000000000 --- a/src/mainboard/asus/p8h61-m_pro/cmos.default +++ /dev/null @@ -1,6 +0,0 @@ -boot_option=Fallback -debug_level=Debug -power_on_after_fail=Enable -nmi=Enable -sata_mode=AHCI -gfx_uma_size=32M diff --git a/src/mainboard/asus/p8h61-m_pro/cmos.layout b/src/mainboard/asus/p8h61-m_pro/cmos.layout deleted file mode 100644 index 8c6a055ca3..0000000000 --- a/src/mainboard/asus/p8h61-m_pro/cmos.layout +++ /dev/null @@ -1,66 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -# ----------------------------------------------------------------- -entries - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter - -# ----------------------------------------------------------------- -# coreboot config options: console -395 4 e 6 debug_level - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail - -421 1 e 9 sata_mode - -# coreboot config options: cpu - -# coreboot config options: northbridge -432 3 e 11 gfx_uma_size - -# coreboot config options: check sums -984 16 h 0 check_sum - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -9 0 AHCI -9 1 IDE -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M - -# ----------------------------------------------------------------- -checksums - -checksum 392 439 984 diff --git a/src/mainboard/asus/p8h61-m_pro/data.vbt b/src/mainboard/asus/p8h61-m_pro/data.vbt deleted file mode 100644 index 114a840660..0000000000 Binary files a/src/mainboard/asus/p8h61-m_pro/data.vbt and /dev/null differ diff --git a/src/mainboard/asus/p8h61-m_pro/devicetree.cb b/src/mainboard/asus/p8h61-m_pro/devicetree.cb deleted file mode 100644 index a0221fe761..0000000000 --- a/src/mainboard/asus/p8h61-m_pro/devicetree.cb +++ /dev/null @@ -1,111 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -chip northbridge/intel/sandybridge - device cpu_cluster 0 on - chip cpu/intel/model_206ax - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" - device lapic 0 on end - device lapic 0xacac off end - end - end - device domain 0 on - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe bridge for discrete graphics (PCIEX16_1) - device pci 02.0 on end # Internal graphics VGA controller - - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" - register "gen1_dec" = "0x000c0291" # HWM - register "sata_interface_speed_support" = "0x3" - register "sata_port_map" = "0x33" - register "spi_lvscc" = "0x2005" - register "spi_uvscc" = "0x2005" - - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio Audio controller - device pci 1c.0 on end # PCIe x1 Port (PCIEX1_1) - device pci 1c.1 on end # PCIe x1 Port (PCIEX1_2) - device pci 1c.2 on # Realtek RTL8111E Ethernet Controller - chip drivers/net - register "customized_leds" = "0x00f6" - register "wake" = "9" - device pci 00.0 on end - end - end - device pci 1c.3 on end # ASMedia ASM1042 USB3 Controller - device pci 1c.4 on end # PCIe x1 Port, x16 size (PCIEX16_2) - device pci 1c.5 on end # ASMedia ASM1062 SATA Controller - device pci 1c.6 off end # Unused PCIe Port - device pci 1c.7 off end # Unused PCIe Port - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge - chip superio/nuvoton/nct6776 - device pnp 2e.0 off end # Floppy - device pnp 2e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 5 - drq 0x74 = 4 - irq 0xf0 = 0x3c - end - device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off end # COM2, IR - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off end # CIR - device pnp 2e.7 off end # GPIO6-9 - device pnp 2e.8 off end # WDT1, GPIO0, GPIO1, GPIOA - device pnp 2e.9 off end # GPIO2-5 - device pnp 2e.a on # ACPI - irq 0xe5 = 0x06 - irq 0xe6 = 0x0c - irq 0xe7 = 0x11 - irq 0xf0 = 0x00 - irq 0xf2 = 0x5d - end - device pnp 2e.b on # HWM, LED - io 0x60 = 0x0290 - io 0x62 = 0x0000 - end - device pnp 2e.d on end # VID - device pnp 2e.e off end # CIR WAKE-UP - device pnp 2e.f on # GPIO Push-Pull or Open-drain - irq 0xf0 = 0x9d - end - device pnp 2e.14 off end # SVID - device pnp 2e.16 on # Deep Sleep - io 0x30 = 0x20 - end - device pnp 2e.17 on # GPIOA - irq 0xe0 = 0xff - irq 0xe1 = 0xff - irq 0xe2 = 0xff - irq 0xe3 = 0xff - irq 0xe5 = 0xff - end - end - chip drivers/pc80/tpm - device pnp 4e.0 on end # TPM - end - end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal - end - end -end diff --git a/src/mainboard/asus/p8h61-m_pro/dsdt.asl b/src/mainboard/asus/p8h61-m_pro/dsdt.asl deleted file mode 100644 index 149d548778..0000000000 --- a/src/mainboard/asus/p8h61-m_pro/dsdt.asl +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -DefinitionBlock( - "dsdt.aml", - "DSDT", - ACPI_DSDT_REV_2, - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20141018 // OEM revision -) -{ - #include - #include "acpi/platform.asl" - #include - #include - - /* global NVS and variables. */ - #include - #include - - Device (\_SB.PCI0) - { - #include - #include - } -} diff --git a/src/mainboard/asus/p8h61-m_pro/early_init.c b/src/mainboard/asus/p8h61-m_pro/early_init.c deleted file mode 100644 index 05e87c1c68..0000000000 --- a/src/mainboard/asus/p8h61-m_pro/early_init.c +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include - -#define GLOBAL_DEV PNP_DEV(0x2e, 0) -#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) -#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; - -void bootblock_mainboard_early_init(void) -{ - /* Enable UART */ - nuvoton_pnp_enter_conf_state(GLOBAL_DEV); - - /* Select SIO pin states. */ - pnp_write_config(GLOBAL_DEV, 0x1c, 0x83); - pnp_write_config(GLOBAL_DEV, 0x24, 0x30); - pnp_write_config(GLOBAL_DEV, 0x27, 0x40); - pnp_write_config(GLOBAL_DEV, 0x2a, 0x20); - - /* Power RAM in S3. */ - pnp_set_logical_device(ACPI_DEV); - pnp_write_config(ACPI_DEV, 0xe4, 0x10); - - pnp_set_logical_device(SERIAL_DEV); - - nuvoton_pnp_exit_conf_state(GLOBAL_DEV); - - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} diff --git a/src/mainboard/asus/p8h61-m_pro/gma-mainboard.ads b/src/mainboard/asus/p8h61-m_pro/gma-mainboard.ads deleted file mode 100644 index ddbbd82bf7..0000000000 --- a/src/mainboard/asus/p8h61-m_pro/gma-mainboard.ads +++ /dev/null @@ -1,21 +0,0 @@ --- SPDX-License-Identifier: GPL-2.0-or-later - -with HW.GFX.GMA; -with HW.GFX.GMA.Display_Probing; - -use HW.GFX.GMA; -use HW.GFX.GMA.Display_Probing; - -private package GMA.Mainboard is - - -- For a three-pipe setup, bandwidth is shared between the 2nd and - -- the 3rd pipe. Thus, probe ports that likely have a high-resolution - -- display attached first. - - ports : constant Port_List := - (HDMI3, -- mainboard HDMI port - HDMI1, -- mainboard DVI-D port - Analog, - others => Disabled); - -end GMA.Mainboard; diff --git a/src/mainboard/asus/p8h61-m_pro/gpio.c b/src/mainboard/asus/p8h61-m_pro/gpio.c deleted file mode 100644 index d57a0f352a..0000000000 --- a/src/mainboard/asus/p8h61-m_pro/gpio.c +++ /dev/null @@ -1,183 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -static const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_GPIO, - .gpio1 = GPIO_MODE_GPIO, - .gpio2 = GPIO_MODE_NATIVE, - .gpio3 = GPIO_MODE_NATIVE, - .gpio4 = GPIO_MODE_NATIVE, - .gpio5 = GPIO_MODE_NATIVE, - .gpio6 = GPIO_MODE_GPIO, - .gpio7 = GPIO_MODE_GPIO, - .gpio8 = GPIO_MODE_GPIO, - .gpio9 = GPIO_MODE_NATIVE, - .gpio10 = GPIO_MODE_GPIO, - .gpio11 = GPIO_MODE_NATIVE, - .gpio12 = GPIO_MODE_GPIO, - .gpio13 = GPIO_MODE_GPIO, - .gpio14 = GPIO_MODE_GPIO, - .gpio15 = GPIO_MODE_GPIO, - .gpio16 = GPIO_MODE_GPIO, - .gpio17 = GPIO_MODE_GPIO, - .gpio18 = GPIO_MODE_NATIVE, - .gpio19 = GPIO_MODE_NATIVE, - .gpio20 = GPIO_MODE_NATIVE, - .gpio21 = GPIO_MODE_NATIVE, - .gpio22 = GPIO_MODE_NATIVE, - .gpio23 = GPIO_MODE_NATIVE, - .gpio24 = GPIO_MODE_GPIO, - .gpio25 = GPIO_MODE_NATIVE, - .gpio26 = GPIO_MODE_NATIVE, - .gpio27 = GPIO_MODE_GPIO, - .gpio28 = GPIO_MODE_GPIO, - .gpio29 = GPIO_MODE_GPIO, - .gpio30 = GPIO_MODE_NATIVE, - .gpio31 = GPIO_MODE_GPIO, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio0 = GPIO_DIR_OUTPUT, - .gpio1 = GPIO_DIR_INPUT, - .gpio6 = GPIO_DIR_INPUT, - .gpio7 = GPIO_DIR_INPUT, - .gpio8 = GPIO_DIR_INPUT, - .gpio10 = GPIO_DIR_INPUT, - .gpio12 = GPIO_DIR_INPUT, - .gpio13 = GPIO_DIR_INPUT, - .gpio14 = GPIO_DIR_INPUT, - .gpio15 = GPIO_DIR_OUTPUT, - .gpio16 = GPIO_DIR_INPUT, - .gpio17 = GPIO_DIR_INPUT, - .gpio24 = GPIO_DIR_OUTPUT, - .gpio27 = GPIO_DIR_INPUT, - .gpio28 = GPIO_DIR_OUTPUT, - .gpio29 = GPIO_DIR_INPUT, - .gpio31 = GPIO_DIR_OUTPUT, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio0 = GPIO_LEVEL_LOW, - .gpio15 = GPIO_LEVEL_LOW, - .gpio24 = GPIO_LEVEL_LOW, - .gpio28 = GPIO_LEVEL_LOW, - .gpio31 = GPIO_LEVEL_HIGH, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_reset = { -}; - -static const struct pch_gpio_set1 pch_gpio_set1_invert = { - .gpio1 = GPIO_INVERT, - .gpio6 = GPIO_INVERT, - .gpio13 = GPIO_INVERT, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_blink = { -}; - -static const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio32 = GPIO_MODE_GPIO, - .gpio33 = GPIO_MODE_GPIO, - .gpio34 = GPIO_MODE_GPIO, - .gpio35 = GPIO_MODE_NATIVE, - .gpio36 = GPIO_MODE_NATIVE, - .gpio37 = GPIO_MODE_NATIVE, - .gpio38 = GPIO_MODE_NATIVE, - .gpio39 = GPIO_MODE_NATIVE, - .gpio40 = GPIO_MODE_NATIVE, - .gpio41 = GPIO_MODE_NATIVE, - .gpio42 = GPIO_MODE_GPIO, - .gpio43 = GPIO_MODE_NATIVE, - .gpio44 = GPIO_MODE_NATIVE, - .gpio45 = GPIO_MODE_NATIVE, - .gpio46 = GPIO_MODE_GPIO, /* wired to GPU Boost switch */ - .gpio47 = GPIO_MODE_NATIVE, - .gpio48 = GPIO_MODE_NATIVE, - .gpio49 = GPIO_MODE_GPIO, - .gpio50 = GPIO_MODE_NATIVE, - .gpio51 = GPIO_MODE_NATIVE, - .gpio52 = GPIO_MODE_NATIVE, - .gpio53 = GPIO_MODE_NATIVE, - .gpio54 = GPIO_MODE_NATIVE, - .gpio55 = GPIO_MODE_NATIVE, - .gpio56 = GPIO_MODE_NATIVE, - .gpio57 = GPIO_MODE_GPIO, - .gpio58 = GPIO_MODE_NATIVE, - .gpio59 = GPIO_MODE_NATIVE, - .gpio60 = GPIO_MODE_NATIVE, - .gpio61 = GPIO_MODE_GPIO, - .gpio62 = GPIO_MODE_NATIVE, - .gpio63 = GPIO_MODE_NATIVE, -}; - -static const struct pch_gpio_set2 pch_gpio_set2_direction = { - .gpio32 = GPIO_DIR_OUTPUT, - .gpio33 = GPIO_DIR_OUTPUT, - .gpio34 = GPIO_DIR_INPUT, - .gpio42 = GPIO_DIR_INPUT, - .gpio46 = GPIO_DIR_INPUT, - .gpio49 = GPIO_DIR_INPUT, - .gpio57 = GPIO_DIR_INPUT, - .gpio61 = GPIO_DIR_OUTPUT, -}; - -static const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio32 = GPIO_LEVEL_HIGH, - .gpio33 = GPIO_LEVEL_HIGH, - .gpio61 = GPIO_LEVEL_HIGH, -}; - -static const struct pch_gpio_set2 pch_gpio_set2_reset = { -}; - -static const struct pch_gpio_set3 pch_gpio_set3_mode = { - .gpio64 = GPIO_MODE_NATIVE, - .gpio65 = GPIO_MODE_NATIVE, - .gpio66 = GPIO_MODE_NATIVE, - .gpio67 = GPIO_MODE_NATIVE, - .gpio68 = GPIO_MODE_GPIO, - .gpio69 = GPIO_MODE_GPIO, - .gpio70 = GPIO_MODE_NATIVE, - .gpio71 = GPIO_MODE_NATIVE, - .gpio72 = GPIO_MODE_GPIO, - .gpio73 = GPIO_MODE_NATIVE, - .gpio74 = GPIO_MODE_NATIVE, - .gpio75 = GPIO_MODE_NATIVE, -}; - -static const struct pch_gpio_set3 pch_gpio_set3_direction = { - .gpio68 = GPIO_DIR_INPUT, - .gpio69 = GPIO_DIR_INPUT, - .gpio72 = GPIO_DIR_INPUT, -}; - -static const struct pch_gpio_set3 pch_gpio_set3_level = { -}; - -static const struct pch_gpio_set3 pch_gpio_set3_reset = { -}; - -const struct pch_gpio_map mainboard_gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - .blink = &pch_gpio_set1_blink, - .invert = &pch_gpio_set1_invert, - .reset = &pch_gpio_set1_reset, - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - .reset = &pch_gpio_set2_reset, - }, - .set3 = { - .mode = &pch_gpio_set3_mode, - .direction = &pch_gpio_set3_direction, - .level = &pch_gpio_set3_level, - .reset = &pch_gpio_set3_reset, - }, -}; diff --git a/src/mainboard/asus/p8h61-m_pro/hda_verb.c b/src/mainboard/asus/p8h61-m_pro/hda_verb.c deleted file mode 100644 index 9f77ac7f9e..0000000000 --- a/src/mainboard/asus/p8h61-m_pro/hda_verb.c +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -const u32 cim_verb_data[] = { - 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ - 0x10438444, /* Subsystem ID */ - 15, /* Number of 4 dword sets */ - AZALIA_SUBVENDOR(0, 0x10438444), - AZALIA_PIN_CFG(0, 0x11, 0x99430140), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), - AZALIA_PIN_CFG(0, 0x14, 0x01014010), - AZALIA_PIN_CFG(0, 0x15, 0x01011012), - AZALIA_PIN_CFG(0, 0x16, 0x01016011), - AZALIA_PIN_CFG(0, 0x17, 0x01012014), - AZALIA_PIN_CFG(0, 0x18, 0x01a19850), - AZALIA_PIN_CFG(0, 0x19, 0x02a19c60), - AZALIA_PIN_CFG(0, 0x1a, 0x0181305f), - AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1d, 0x4005e601), - AZALIA_PIN_CFG(0, 0x1e, 0x01456130), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), - - 0x80862805, /* Codec Vendor / Device ID: Intel */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of 4 dword sets */ - AZALIA_SUBVENDOR(3, 0x80860101), - AZALIA_PIN_CFG(3, 0x05, 0x58560010), - AZALIA_PIN_CFG(3, 0x06, 0x58560020), - AZALIA_PIN_CFG(3, 0x07, 0x18560030), -}; - -const u32 pc_beep_verbs[0] = {}; - -AZALIA_ARRAY_SIZES; -- cgit v1.2.3