From 2446c1e9e99e6448f5f62c7a4f9c50dceec2b25e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 9 Jul 2020 07:13:37 +0300 Subject: arch/x86: Drop CBMEM_TOP_BACKUP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Code has evolved such that there seems to be little use for global definition of cbmem_top_chipset(). Even for AMD we had three different implementations. Change-Id: I44805aa49eab526b940e57bd51cd1d9ae0377b4b Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/43326 Reviewed-by: Angel Pons Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/arch/x86/Kconfig | 6 ------ src/arch/x86/Makefile.inc | 1 - src/arch/x86/cbmem.c | 13 ------------- src/cpu/amd/mtrr/amd_mtrr.c | 2 +- src/drivers/amd/agesa/romstage.c | 6 ++++++ src/include/cbmem.h | 11 ----------- src/northbridge/amd/agesa/Kconfig | 1 - src/northbridge/amd/agesa/family14/state_machine.c | 2 +- src/northbridge/amd/agesa/family15tn/state_machine.c | 4 ++-- src/northbridge/amd/agesa/family16kb/state_machine.c | 4 ++-- src/northbridge/amd/pi/00730F01/state_machine.c | 3 ++- src/northbridge/amd/pi/Kconfig | 1 - src/soc/amd/common/block/acpimmio/biosram.c | 1 - src/soc/amd/common/block/include/amdblocks/biosram.h | 8 ++++++++ src/soc/amd/common/block/pi/agesawrapper.c | 1 - src/soc/amd/stoneyridge/memmap.c | 2 +- 16 files changed, 23 insertions(+), 43 deletions(-) delete mode 100644 src/arch/x86/cbmem.c diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 968d784d8b..660ff2d4d2 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -133,12 +133,6 @@ config NUM_IPI_STARTS int default 2 -config CBMEM_TOP_BACKUP - def_bool n - help - Platform implements non-volatile storage to cache cbmem_top() - over stage transitions and optionally also over S3 suspend. - config PRERAM_CBMEM_CONSOLE_SIZE hex default 0xc00 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index fa647b7c9a..61e7edcfb9 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -164,7 +164,6 @@ romstage-y += post.c # gdt_init.S is included by entry32.inc when romstage is the first C # environment. romstage-y += gdt_init.S -romstage-y += cbmem.c romstage-y += cpu_common.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c deleted file mode 100644 index 353368a1ec..0000000000 --- a/src/arch/x86/cbmem.c +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -#if CONFIG(CBMEM_TOP_BACKUP) - -void *cbmem_top_chipset(void) -{ - /* Top of CBMEM is at highest usable DRAM address below 4GiB. */ - return (void *)restore_top_of_low_cacheable(); -} - -#endif /* CBMEM_TOP_BACKUP */ diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index 1234c82037..fc3212f1fc 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include #include #include #include diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 617416ab7a..29423ef1ba 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -107,3 +107,9 @@ asmlinkage void car_stage_entry(void) { romstage_main(); } + +void *cbmem_top_chipset(void) +{ + /* Top of CBMEM is at highest usable DRAM address below 4GiB. */ + return (void *)restore_top_of_low_cacheable(); +} diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 4cc4045055..b548cd9559 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -139,17 +139,6 @@ void cbmem_add_records_to_cbtable(struct lb_header *header); static cbmem_init_hook_t init_fn_ ## _unused3_ = init_fn_; #endif /* ENV_RAMSTAGE */ - -/* Any new chipset and board must implement cbmem_top() for both - * romstage and ramstage to support early features like COLLECT_TIMESTAMPS - * and CBMEM_CONSOLE. Sometimes it is necessary to have cbmem_top() - * value stored in nvram to enable early recovery on S3 path. - */ -#if ENV_X86 -void backup_top_of_low_cacheable(uintptr_t ramtop); -uintptr_t restore_top_of_low_cacheable(void); -#endif - /* * Returns 0 for the stages where we know that cbmem does not come online. * Even if this function returns 1 for romstage, depending upon the point in diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index 6711f8702d..6f6e3d63a9 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -3,7 +3,6 @@ config NORTHBRIDGE_AMD_AGESA bool default CPU_AMD_AGESA - select CBMEM_TOP_BACKUP if NORTHBRIDGE_AMD_AGESA diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c index 202cdaa9f5..36e5fd9416 100644 --- a/src/northbridge/amd/agesa/family14/state_machine.c +++ b/src/northbridge/amd/agesa/family14/state_machine.c @@ -2,8 +2,8 @@ #include #include +#include #include -#include #include #include #include diff --git a/src/northbridge/amd/agesa/family15tn/state_machine.c b/src/northbridge/amd/agesa/family15tn/state_machine.c index 8d450f94cd..29c1d87005 100644 --- a/src/northbridge/amd/agesa/family15tn/state_machine.c +++ b/src/northbridge/amd/agesa/family15tn/state_machine.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include + #include #include - -#include #include #include diff --git a/src/northbridge/amd/agesa/family16kb/state_machine.c b/src/northbridge/amd/agesa/family16kb/state_machine.c index 58bc345a6d..cbf0313267 100644 --- a/src/northbridge/amd/agesa/family16kb/state_machine.c +++ b/src/northbridge/amd/agesa/family16kb/state_machine.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include + #include #include - -#include #include #include diff --git a/src/northbridge/amd/pi/00730F01/state_machine.c b/src/northbridge/amd/pi/00730F01/state_machine.c index f3c45a01f1..a97faeb8ea 100644 --- a/src/northbridge/amd/pi/00730F01/state_machine.c +++ b/src/northbridge/amd/pi/00730F01/state_machine.c @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include + #include "Porting.h" #include "AGESA.h" -#include #include #include #include diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index e8c3530018..833afae9df 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -4,7 +4,6 @@ config NORTHBRIDGE_AMD_PI bool default y if CPU_AMD_PI default n - select CBMEM_TOP_BACKUP if NORTHBRIDGE_AMD_PI diff --git a/src/soc/amd/common/block/acpimmio/biosram.c b/src/soc/amd/common/block/acpimmio/biosram.c index b01c196013..06bbed99e0 100644 --- a/src/soc/amd/common/block/acpimmio/biosram.c +++ b/src/soc/amd/common/block/acpimmio/biosram.c @@ -2,7 +2,6 @@ #include #include -#include #include #include diff --git a/src/soc/amd/common/block/include/amdblocks/biosram.h b/src/soc/amd/common/block/include/amdblocks/biosram.h index 39ce112c0e..226fc173d4 100644 --- a/src/soc/amd/common/block/include/amdblocks/biosram.h +++ b/src/soc/amd/common/block/include/amdblocks/biosram.h @@ -5,6 +5,14 @@ #include +/* Any new chipset and board must implement cbmem_top() for both + * romstage and ramstage to support early features like COLLECT_TIMESTAMPS + * and CBMEM_CONSOLE. With AMD it is necessary to have cbmem_top() + * value stored in nvram to enable early recovery on S3 path. + */ +void backup_top_of_low_cacheable(uintptr_t ramtop); +uintptr_t restore_top_of_low_cacheable(void); + /* Returns the bootblock C entry point for APs */ void *get_ap_entry_ptr(void); /* Used by BSP to store the bootblock entry point for APs */ diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index de9144c02f..ff52fbd8c8 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c index 98079059ef..67a431976c 100644 --- a/src/soc/amd/stoneyridge/memmap.c +++ b/src/soc/amd/stoneyridge/memmap.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #if CONFIG(ACPI_BERT) #if CONFIG_SMM_TSEG_SIZE == 0x0 -- cgit v1.2.3