From 2983c708155466d88776338b3a7faec9f80f0134 Mon Sep 17 00:00:00 2001
From: Richard Spiegel <richard.spiegel@silverbackltd.com>
Date: Mon, 20 Nov 2017 12:30:32 -0700
Subject: Create SOC description file soc.asl

Request from commit 519680948b (move carrizo_fch.asl code to soc), merge
several includes into a single file in soc directory.

Rename soc_fch.asl to sb_fch.asl. Rename fch.asl to sb_pci0_fch.asl.
Then copy the required section from dsdt.asl into a new soc.asl.

Affected boards: amd/gardenia and google/kahlee.

BUG=b:69368752

Change-Id: I83d850cf9457f7c2c787336823d993ae2e9d28ce
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22541
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/amd/gardenia/dsdt.asl          |  17 +--
 src/mainboard/google/kahlee/dsdt.asl         |  17 +--
 src/soc/amd/stoneyridge/acpi/fch.asl         | 186 ---------------------------
 src/soc/amd/stoneyridge/acpi/sb_fch.asl      | 139 ++++++++++++++++++++
 src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl | 186 +++++++++++++++++++++++++++
 src/soc/amd/stoneyridge/acpi/soc.asl         |  28 ++++
 src/soc/amd/stoneyridge/acpi/soc_fch.asl     | 139 --------------------
 7 files changed, 359 insertions(+), 353 deletions(-)
 delete mode 100644 src/soc/amd/stoneyridge/acpi/fch.asl
 create mode 100644 src/soc/amd/stoneyridge/acpi/sb_fch.asl
 create mode 100644 src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
 create mode 100644 src/soc/amd/stoneyridge/acpi/soc.asl
 delete mode 100644 src/soc/amd/stoneyridge/acpi/soc_fch.asl

diff --git a/src/mainboard/amd/gardenia/dsdt.asl b/src/mainboard/amd/gardenia/dsdt.asl
index bc81602747..e6acfc8bbc 100644
--- a/src/mainboard/amd/gardenia/dsdt.asl
+++ b/src/mainboard/amd/gardenia/dsdt.asl
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
+ * Copyright (C) 2015-2017 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -61,19 +61,8 @@ DefinitionBlock (
 			Name(_STA, 0x0B)
 		}
 
-		Device(PCI0) {
-			/* Describe the AMD Northbridge */
-			#include <northbridge.asl>
-
-			/* Describe the AMD Fusion Controller Hub Southbridge */
-			#include <fch.asl>
-		}
-
-		/* Describe PCI INT[A-H] for the Southbridge */
-		#include <pci_int.asl>
-
-		/* Describe the devices in the Southbridge */
-		#include <soc_fch.asl>
+		/* Describe the SOC */
+		#include <soc.asl>
 
 	} /* End \_SB scope */
 
diff --git a/src/mainboard/google/kahlee/dsdt.asl b/src/mainboard/google/kahlee/dsdt.asl
index 885dd8dce0..ded0dc8779 100644
--- a/src/mainboard/google/kahlee/dsdt.asl
+++ b/src/mainboard/google/kahlee/dsdt.asl
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
+ * Copyright (C) 2015-2017 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -61,19 +61,8 @@ DefinitionBlock (
 			Name(_UID, 0xAA)
 		}
 
-		Device(PCI0) {
-			/* Describe the AMD Northbridge */
-			#include <northbridge.asl>
-
-			/* Describe the AMD Fusion Controller Hub Southbridge */
-			#include <fch.asl>
-		}
-
-		/* Describe PCI INT[A-H] for the Southbridge */
-		#include <pci_int.asl>
-
-		/* Describe the devices in the Southbridge */
-		#include <soc_fch.asl>
+		/* Describe the SOC */
+		#include <soc.asl>
 
 	} /* End \_SB scope */
 
diff --git a/src/soc/amd/stoneyridge/acpi/fch.asl b/src/soc/amd/stoneyridge/acpi/fch.asl
deleted file mode 100644
index 6dcafe6faf..0000000000
--- a/src/soc/amd/stoneyridge/acpi/fch.asl
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* South Bridge */
-/*  _SB.PCI0 */
-
-/* Operating System Capabilities Method */
-Method(_OSC,4)
-{
-	// Create DWord-addressable fields from the Capabilities Buffer
-	CreateDWordField(Arg3,0,CDW1)
-	CreateDWordField(Arg3,4,CDW2)
-	CreateDWordField(Arg3,8,CDW3)
-
-	/* Check for proper PCI/PCIe UUID */
-	If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
-	{
-		/* Let OS control everything */
-		Return (Arg3)
-	} Else {
-		Or(CDW1,4,CDW1)	// Unrecognized UUID
-		Return(Arg3)
-	}
-}
-
-/* Describe the Southbridge devices */
-
-/* 0:11.0 - SATA */
-Device(STCR) {
-	Name(_ADR, 0x00110000)
-} /* end STCR */
-
-/* 0:14.0 - SMBUS */
-Device(SBUS) {
-	Name(_ADR, 0x00140000)
-} /* end SBUS */
-
-#include "usb.asl"
-
-/* 0:14.2 - I2S Audio */
-
-/* 0:14.3 - LPC */
-#include "lpc.asl"
-
-/* 0:14.7 - SD Controller */
-Device(SDCN) {
-	Name(_ADR, 0x00140007)
-} /* end SDCN */
-
-Name(CRES, ResourceTemplate() {
-	/* Set the Bus number and Secondary Bus number for the PCI0 device
-	 * The Secondary bus range for PCI0 lets the system
-	 * know what bus values are allowed on the downstream
-	 * side of this PCI bus if there is a PCI-PCI bridge.
-	 * PCI busses can have 256 secondary busses which
-	 * range from [0-0xFF] but they do not need to be
-	 * sequential.
-	 */
-	WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
-		0x0000,		/* address granularity */
-		0x0000,		/* range minimum */
-		0x00ff,		/* range maximum */
-		0x0000,		/* translation */
-		0x0100,		/* length */
-		,, PSB0)		/* ResourceSourceIndex, ResourceSource, DescriptorName */
-
-	IO(Decode16, 0x0cf8, 0x0cf8, 1,	8)
-
-	WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-		0x0000,		/* address granularity */
-		0x0000,		/* range minimum */
-		0x0cf7,		/* range maximum */
-		0x0000,		/* translation */
-		0x0cf8		/* length */
-	)
-	WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-		0x0000,		/* address granularity */
-		0x03b0,		/* range minimum */
-		0x03df,		/* range maximum */
-		0x0000,		/* translation */
-		0x0030		/* length */
-	)
-
-	WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-		0x0000,		/* address granularity */
-		0x0d00,		/* range minimum */
-		0xffff,		/* range maximum */
-		0x0000,		/* translation */
-		0xf300		/* length */
-	)
-
-	Memory32Fixed(READONLY, 0x000a0000, 0x00020000, VGAM)	/* VGA memory space */
-	Memory32Fixed(READONLY, 0x000c0000, 0x00020000, EMM1)	/* Assume C0000-E0000 empty */
-
-	/* memory space for PCI BARs below 4GB */
-	Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
-}) /* End Name(_SB.PCI0.CRES) */
-
-Method(_CRS, 0) {
-	/* DBGO("\\_SB\\PCI0\\_CRS\n") */
-	CreateDWordField(CRES, ^MMIO._BAS, MM1B)
-	CreateDWordField(CRES, ^MMIO._LEN, MM1L)
-
-	/*
-	 * Declare memory between TOM1 and 4GB as available
-	 * for PCI MMIO.
-	 * Use ShiftLeft to avoid 64bit constant (for XP).
-	 * This will work even if the OS does 32bit arithmetic, as
-	 * 32bit (0x00000000 - TOM1) will wrap and give the same
-	 * result as 64bit (0x100000000 - TOM1).
-	 */
-	Store(TOM1, MM1B)
-	ShiftLeft(0x10000000, 4, Local0)
-	Subtract(Local0, TOM1, Local0)
-	Store(Local0, MM1L)
-
-	Return(CRES) /* note to change the Name buffer */
-} /* end of Method(_SB.PCI0._CRS) */
-
-/*
- *
- *               FIRST METHOD CALLED UPON BOOT
- *
- *  1. If debugging, print current OS and ACPI interpreter.
- *  2. Get PCI Interrupt routing from ACPI VSM, this
- *     value is based on user choice in BIOS setup.
- */
-Method(_INI, 0) {
-	/* DBGO("\\_SB\\_INI\n") */
-	/* DBGO("   DSDT.ASL code from ") */
-	/* DBGO(__DATE__) */
-	/* DBGO(" ") */
-	/* DBGO(__TIME__) */
-	/* DBGO("\n   Sleep states supported: ") */
-	/* DBGO("\n") */
-	/* DBGO("   \\_OS=") */
-	/* DBGO(\_OS) */
-	/* DBGO("\n   \\_REV=") */
-	/* DBGO(\_REV) */
-	/* DBGO("\n") */
-
-	/* Determine the OS we're running on */
-	OSFL()
-
-#if IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM)
-	/* TODO: It is unstable. */
-	#include "acpi/AmdImc.asl"
-#if IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE)
-	ITZE() /* enable IMC Fan Control*/
-#endif
-#endif
-} /* End Method(_SB._INI) */
-
-Method(OSFL, 0){
-
-	if (LNotEqual(OSVR, Ones)) {Return(OSVR)}	/* OS version was already detected */
-
-	if (CondRefOf(\_OSI))
-	{
-		Store(1, OSVR)					/* Assume some form of XP */
-		if (\_OSI("Windows 2006"))		/* Vista */
-		{
-			Store(2, OSVR)
-		}
-	} else {
-		If(WCMP(\_OS,"Linux")) {
-			Store(3, OSVR)				/* Linux */
-		} Else {
-			Store(4, OSVR)				/* Gotta be WinCE */
-		}
-	}
-	Return(OSVR)
-}
diff --git a/src/soc/amd/stoneyridge/acpi/sb_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_fch.asl
new file mode 100644
index 0000000000..9bf7decb49
--- /dev/null
+++ b/src/soc/amd/stoneyridge/acpi/sb_fch.asl
@@ -0,0 +1,139 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/gpio.h>
+
+Device (AAHB)
+{
+	Name (_HID, "AAHB0000")
+	Name (_UID, 0x0)
+	Name (_CRS, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, 0xFEDC0000, 0x2000)
+	})
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}
+
+Device (GPIO)
+{
+	Name (_HID, GPIO_DEVICE_NAME)
+	Name (_CID, GPIO_DEVICE_NAME)
+	Name (_UID, 0)
+	Name (_DDN, GPIO_DEVICE_DESC)
+
+	Name (_CRS, ResourceTemplate()
+	{
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
+			{ 7 }
+		Memory32Fixed (ReadWrite, 0xFED81500, 0x300)
+	})
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}
+
+Device (FUR0)
+{
+	Name (_HID, "AMD0020")
+	Name (_UID, 0x0)
+	Name (_CRS, ResourceTemplate()
+	{
+		IRQ (Edge, ActiveHigh, Exclusive) { 10 }
+		Memory32Fixed (ReadWrite, 0xFEDC6000, 0x2000)
+	})
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}
+
+Device (FUR1) {
+	Name (_HID, "AMD0020")
+	Name (_UID, 0x1)
+	Name (_CRS, ResourceTemplate()
+	{
+			IRQ (Edge, ActiveHigh, Exclusive) { 11 }
+			Memory32Fixed (ReadWrite, 0xFEDC8000, 0x2000)
+	})
+	Method (_STA, 0x0, NotSerialized)
+	{
+			Return (0x0F)
+	}
+}
+
+Device (I2CA) {
+	Name (_HID, "AMD0010")
+	Name (_UID, 0x0)
+	Name (_CRS, ResourceTemplate()
+	{
+		IRQ (Edge, ActiveHigh, Exclusive) { 3 }
+		Memory32Fixed (ReadWrite, 0xFEDC2000, 0x1000)
+	})
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}
+
+Device (I2CB)
+{
+	Name (_HID, "AMD0010")
+	Name (_UID, 0x1)
+	Name (_CRS, ResourceTemplate()
+	{
+		IRQ (Edge, ActiveHigh, Exclusive) { 15 }
+		Memory32Fixed (ReadWrite, 0xFEDC3000, 0x1000)
+	})
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}
+
+Device (I2CC) {
+	Name (_HID, "AMD0010")
+	Name (_UID, 0x0)
+	Name (_CRS, ResourceTemplate()
+	{
+		IRQ (Edge, ActiveHigh, Exclusive) { 6 }
+		Memory32Fixed (ReadWrite, 0xFEDC4000, 0x1000)
+	})
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}
+
+Device (I2CD)
+{
+	Name (_HID, "AMD0010")
+	Name (_UID, 0x1)
+	Name (_CRS, ResourceTemplate() {
+		IRQ (Edge, ActiveHigh, Exclusive) { 14 }
+		Memory32Fixed(ReadWrite, 0xFEDC5000, 0x1000)
+	})
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}
diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
new file mode 100644
index 0000000000..6dcafe6faf
--- /dev/null
+++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
@@ -0,0 +1,186 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* South Bridge */
+/*  _SB.PCI0 */
+
+/* Operating System Capabilities Method */
+Method(_OSC,4)
+{
+	// Create DWord-addressable fields from the Capabilities Buffer
+	CreateDWordField(Arg3,0,CDW1)
+	CreateDWordField(Arg3,4,CDW2)
+	CreateDWordField(Arg3,8,CDW3)
+
+	/* Check for proper PCI/PCIe UUID */
+	If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
+	{
+		/* Let OS control everything */
+		Return (Arg3)
+	} Else {
+		Or(CDW1,4,CDW1)	// Unrecognized UUID
+		Return(Arg3)
+	}
+}
+
+/* Describe the Southbridge devices */
+
+/* 0:11.0 - SATA */
+Device(STCR) {
+	Name(_ADR, 0x00110000)
+} /* end STCR */
+
+/* 0:14.0 - SMBUS */
+Device(SBUS) {
+	Name(_ADR, 0x00140000)
+} /* end SBUS */
+
+#include "usb.asl"
+
+/* 0:14.2 - I2S Audio */
+
+/* 0:14.3 - LPC */
+#include "lpc.asl"
+
+/* 0:14.7 - SD Controller */
+Device(SDCN) {
+	Name(_ADR, 0x00140007)
+} /* end SDCN */
+
+Name(CRES, ResourceTemplate() {
+	/* Set the Bus number and Secondary Bus number for the PCI0 device
+	 * The Secondary bus range for PCI0 lets the system
+	 * know what bus values are allowed on the downstream
+	 * side of this PCI bus if there is a PCI-PCI bridge.
+	 * PCI busses can have 256 secondary busses which
+	 * range from [0-0xFF] but they do not need to be
+	 * sequential.
+	 */
+	WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+		0x0000,		/* address granularity */
+		0x0000,		/* range minimum */
+		0x00ff,		/* range maximum */
+		0x0000,		/* translation */
+		0x0100,		/* length */
+		,, PSB0)		/* ResourceSourceIndex, ResourceSource, DescriptorName */
+
+	IO(Decode16, 0x0cf8, 0x0cf8, 1,	8)
+
+	WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+		0x0000,		/* address granularity */
+		0x0000,		/* range minimum */
+		0x0cf7,		/* range maximum */
+		0x0000,		/* translation */
+		0x0cf8		/* length */
+	)
+	WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+		0x0000,		/* address granularity */
+		0x03b0,		/* range minimum */
+		0x03df,		/* range maximum */
+		0x0000,		/* translation */
+		0x0030		/* length */
+	)
+
+	WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+		0x0000,		/* address granularity */
+		0x0d00,		/* range minimum */
+		0xffff,		/* range maximum */
+		0x0000,		/* translation */
+		0xf300		/* length */
+	)
+
+	Memory32Fixed(READONLY, 0x000a0000, 0x00020000, VGAM)	/* VGA memory space */
+	Memory32Fixed(READONLY, 0x000c0000, 0x00020000, EMM1)	/* Assume C0000-E0000 empty */
+
+	/* memory space for PCI BARs below 4GB */
+	Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
+}) /* End Name(_SB.PCI0.CRES) */
+
+Method(_CRS, 0) {
+	/* DBGO("\\_SB\\PCI0\\_CRS\n") */
+	CreateDWordField(CRES, ^MMIO._BAS, MM1B)
+	CreateDWordField(CRES, ^MMIO._LEN, MM1L)
+
+	/*
+	 * Declare memory between TOM1 and 4GB as available
+	 * for PCI MMIO.
+	 * Use ShiftLeft to avoid 64bit constant (for XP).
+	 * This will work even if the OS does 32bit arithmetic, as
+	 * 32bit (0x00000000 - TOM1) will wrap and give the same
+	 * result as 64bit (0x100000000 - TOM1).
+	 */
+	Store(TOM1, MM1B)
+	ShiftLeft(0x10000000, 4, Local0)
+	Subtract(Local0, TOM1, Local0)
+	Store(Local0, MM1L)
+
+	Return(CRES) /* note to change the Name buffer */
+} /* end of Method(_SB.PCI0._CRS) */
+
+/*
+ *
+ *               FIRST METHOD CALLED UPON BOOT
+ *
+ *  1. If debugging, print current OS and ACPI interpreter.
+ *  2. Get PCI Interrupt routing from ACPI VSM, this
+ *     value is based on user choice in BIOS setup.
+ */
+Method(_INI, 0) {
+	/* DBGO("\\_SB\\_INI\n") */
+	/* DBGO("   DSDT.ASL code from ") */
+	/* DBGO(__DATE__) */
+	/* DBGO(" ") */
+	/* DBGO(__TIME__) */
+	/* DBGO("\n   Sleep states supported: ") */
+	/* DBGO("\n") */
+	/* DBGO("   \\_OS=") */
+	/* DBGO(\_OS) */
+	/* DBGO("\n   \\_REV=") */
+	/* DBGO(\_REV) */
+	/* DBGO("\n") */
+
+	/* Determine the OS we're running on */
+	OSFL()
+
+#if IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM)
+	/* TODO: It is unstable. */
+	#include "acpi/AmdImc.asl"
+#if IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE)
+	ITZE() /* enable IMC Fan Control*/
+#endif
+#endif
+} /* End Method(_SB._INI) */
+
+Method(OSFL, 0){
+
+	if (LNotEqual(OSVR, Ones)) {Return(OSVR)}	/* OS version was already detected */
+
+	if (CondRefOf(\_OSI))
+	{
+		Store(1, OSVR)					/* Assume some form of XP */
+		if (\_OSI("Windows 2006"))		/* Vista */
+		{
+			Store(2, OSVR)
+		}
+	} else {
+		If(WCMP(\_OS,"Linux")) {
+			Store(3, OSVR)				/* Linux */
+		} Else {
+			Store(4, OSVR)				/* Gotta be WinCE */
+		}
+	}
+	Return(OSVR)
+}
diff --git a/src/soc/amd/stoneyridge/acpi/soc.asl b/src/soc/amd/stoneyridge/acpi/soc.asl
new file mode 100644
index 0000000000..d7772948ef
--- /dev/null
+++ b/src/soc/amd/stoneyridge/acpi/soc.asl
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+Device(PCI0) {
+	/* Describe the AMD Northbridge */
+	#include "northbridge.asl"
+
+	/* Describe the AMD Fusion Controller Hub */
+	#include "sb_pci0_fch.asl"
+}
+
+/* Describe PCI INT[A-H] for the Southbridge */
+#include "pci_int.asl"
+
+/* Describe the devices in the Southbridge */
+#include "sb_fch.asl"
diff --git a/src/soc/amd/stoneyridge/acpi/soc_fch.asl b/src/soc/amd/stoneyridge/acpi/soc_fch.asl
deleted file mode 100644
index 9bf7decb49..0000000000
--- a/src/soc/amd/stoneyridge/acpi/soc_fch.asl
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <soc/gpio.h>
-
-Device (AAHB)
-{
-	Name (_HID, "AAHB0000")
-	Name (_UID, 0x0)
-	Name (_CRS, ResourceTemplate()
-	{
-		Memory32Fixed (ReadWrite, 0xFEDC0000, 0x2000)
-	})
-
-	Method (_STA, 0x0, NotSerialized)
-	{
-		Return (0x0F)
-	}
-}
-
-Device (GPIO)
-{
-	Name (_HID, GPIO_DEVICE_NAME)
-	Name (_CID, GPIO_DEVICE_NAME)
-	Name (_UID, 0)
-	Name (_DDN, GPIO_DEVICE_DESC)
-
-	Name (_CRS, ResourceTemplate()
-	{
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
-			{ 7 }
-		Memory32Fixed (ReadWrite, 0xFED81500, 0x300)
-	})
-
-	Method (_STA, 0x0, NotSerialized)
-	{
-		Return (0x0F)
-	}
-}
-
-Device (FUR0)
-{
-	Name (_HID, "AMD0020")
-	Name (_UID, 0x0)
-	Name (_CRS, ResourceTemplate()
-	{
-		IRQ (Edge, ActiveHigh, Exclusive) { 10 }
-		Memory32Fixed (ReadWrite, 0xFEDC6000, 0x2000)
-	})
-	Method (_STA, 0x0, NotSerialized)
-	{
-		Return (0x0F)
-	}
-}
-
-Device (FUR1) {
-	Name (_HID, "AMD0020")
-	Name (_UID, 0x1)
-	Name (_CRS, ResourceTemplate()
-	{
-			IRQ (Edge, ActiveHigh, Exclusive) { 11 }
-			Memory32Fixed (ReadWrite, 0xFEDC8000, 0x2000)
-	})
-	Method (_STA, 0x0, NotSerialized)
-	{
-			Return (0x0F)
-	}
-}
-
-Device (I2CA) {
-	Name (_HID, "AMD0010")
-	Name (_UID, 0x0)
-	Name (_CRS, ResourceTemplate()
-	{
-		IRQ (Edge, ActiveHigh, Exclusive) { 3 }
-		Memory32Fixed (ReadWrite, 0xFEDC2000, 0x1000)
-	})
-
-	Method (_STA, 0x0, NotSerialized)
-	{
-		Return (0x0F)
-	}
-}
-
-Device (I2CB)
-{
-	Name (_HID, "AMD0010")
-	Name (_UID, 0x1)
-	Name (_CRS, ResourceTemplate()
-	{
-		IRQ (Edge, ActiveHigh, Exclusive) { 15 }
-		Memory32Fixed (ReadWrite, 0xFEDC3000, 0x1000)
-	})
-	Method (_STA, 0x0, NotSerialized)
-	{
-		Return (0x0F)
-	}
-}
-
-Device (I2CC) {
-	Name (_HID, "AMD0010")
-	Name (_UID, 0x0)
-	Name (_CRS, ResourceTemplate()
-	{
-		IRQ (Edge, ActiveHigh, Exclusive) { 6 }
-		Memory32Fixed (ReadWrite, 0xFEDC4000, 0x1000)
-	})
-
-	Method (_STA, 0x0, NotSerialized)
-	{
-		Return (0x0F)
-	}
-}
-
-Device (I2CD)
-{
-	Name (_HID, "AMD0010")
-	Name (_UID, 0x1)
-	Name (_CRS, ResourceTemplate() {
-		IRQ (Edge, ActiveHigh, Exclusive) { 14 }
-		Memory32Fixed(ReadWrite, 0xFEDC5000, 0x1000)
-	})
-	Method (_STA, 0x0, NotSerialized)
-	{
-		Return (0x0F)
-	}
-}
-- 
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