From 2f8a7046bb120d96022ada1e74545f859f97521f Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Tue, 18 May 2021 10:42:40 -0600 Subject: mb/google/brya/brya0: Manually probe fw_config for DB_LTE In order to use the USB WWAN module in USB mode (as opposed to PCIe), the PCIe RP must be turned off at the FSP level. The `probe` statement in the devicetree unfortunately takes effect too late, because the UPDs for disabling/enabling PCIE RP belong to FSP-M (romstage), whereas fw_config probing for devicetree is done in ramstage. Add a new variant-specific file which will handle manually setting the UPD based on FW_CONFIG instead. BUG=b:180166408 TEST=set CBI FW_CONFIG field to LTE_USB, see message in console, set field to LTE_PCIE, do not see message in console. Change-Id: Ica2f64ec99fa547e233012dc201577a14f6aa7d7 Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/54633 Reviewed-by: EricR Lai Tested-by: build bot (Jenkins) --- src/mainboard/google/brya/romstage.c | 2 ++ .../brya/variants/baseboard/include/baseboard/variants.h | 3 +++ src/mainboard/google/brya/variants/brya0/Makefile.inc | 2 ++ src/mainboard/google/brya/variants/brya0/overridetree.cb | 3 --- src/mainboard/google/brya/variants/brya0/variant.c | 14 ++++++++++++++ 5 files changed, 21 insertions(+), 3 deletions(-) create mode 100644 src/mainboard/google/brya/variants/brya0/Makefile.inc create mode 100644 src/mainboard/google/brya/variants/brya0/variant.c diff --git a/src/mainboard/google/brya/romstage.c b/src/mainboard/google/brya/romstage.c index 475bf61148..c3f8d229d6 100644 --- a/src/mainboard/google/brya/romstage.c +++ b/src/mainboard/google/brya/romstage.c @@ -17,4 +17,6 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) }; memcfg_init(&memupd->FspmConfig, mem_config, &spd_info, half_populated); + + variant_update_fspm_upds(memupd); } diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h index fb105e806a..1d1fe83ec2 100644 --- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h @@ -3,6 +3,7 @@ #ifndef __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__ +#include #include #include #include @@ -19,4 +20,6 @@ const struct mb_cfg *variant_memory_params(void); int variant_memory_sku(void); bool variant_is_half_populated(void); +void variant_update_fspm_upds(FSPM_UPD *memupd); + #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/brya/variants/brya0/Makefile.inc b/src/mainboard/google/brya/variants/brya0/Makefile.inc new file mode 100644 index 0000000000..b30586551f --- /dev/null +++ b/src/mainboard/google/brya/variants/brya0/Makefile.inc @@ -0,0 +1,2 @@ +romstage-y += variant.c +ramstage-y += variant.c diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 452e1d8789..ccc0384497 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -122,9 +122,6 @@ chip soc/intel/alderlake device generic 0 on end end end - device ref pcie_rp6 on - probe DB_LTE LTE_PCIE - end device ref pcie_rp8 on chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" diff --git a/src/mainboard/google/brya/variants/brya0/variant.c b/src/mainboard/google/brya/variants/brya0/variant.c new file mode 100644 index 0000000000..554371ddac --- /dev/null +++ b/src/mainboard/google/brya/variants/brya0/variant.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void variant_update_fspm_upds(FSPM_UPD *memupd) +{ + if (fw_config_probe(FW_CONFIG(DB_LTE, LTE_USB))) { + FSP_M_CONFIG *m_cfg = &memupd->FspmConfig; + printk(BIOS_INFO, "Disabling PCIe RP 6 UPD for USB WWAN\n"); + m_cfg->PcieRpEnableMask &= ~BIT(5); + } +} -- cgit v1.2.3