From 3465d2730ba130f5aed18cb356d09e7104af2280 Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Thu, 6 Feb 2020 15:31:04 +0530 Subject: src/intel: Define HFSTS3 register Changes: 1. Define HFSTS3 register across SoCs(apl/cnl/icl/tgl). 2. Define cse_is_hfs3_fw_sku_custom() which checks ME's Firmware SKU is Custom or not. TEST=Verified on hatch, soraka, bobba and iclrvp. Change-Id: I4188e58a4a08d87be2d84674e00ed1407fb8bf82 Signed-off-by: Sridhar Siricilla Reviewed-on: https://review.coreboot.org/c/coreboot/+/38798 Tested-by: build bot (Jenkins) Reviewed-by: Rizwan Qureshi --- src/soc/intel/apollolake/include/soc/me.h | 14 ++++++++++++++ src/soc/intel/cannonlake/include/soc/me.h | 14 ++++++++++++++ src/soc/intel/common/block/cse/cse.c | 7 +++++++ src/soc/intel/common/block/include/intelblocks/cse.h | 6 ++++++ src/soc/intel/icelake/include/soc/me.h | 14 ++++++++++++++ src/soc/intel/tigerlake/include/soc/me.h | 13 +++++++++++++ 6 files changed, 68 insertions(+) diff --git a/src/soc/intel/apollolake/include/soc/me.h b/src/soc/intel/apollolake/include/soc/me.h index 7ac4deecfa..e1916f622e 100644 --- a/src/soc/intel/apollolake/include/soc/me.h +++ b/src/soc/intel/apollolake/include/soc/me.h @@ -40,4 +40,18 @@ union me_hfsts1 { } __packed fields; }; +/* ME Host Firmware Status Register 3 */ +union me_hfsts3 { + u32 data; + struct { + u32 reserved_0: 4; + u32 fw_sku: 3; + u32 reserved_7: 2; + u32 reserved_9: 2; + u32 resered_11: 3; + u32 resered_14: 16; + u32 reserved_30: 2; + } __packed fields; +}; + #endif /* _APOLLOLAKE_ME_H_ */ diff --git a/src/soc/intel/cannonlake/include/soc/me.h b/src/soc/intel/cannonlake/include/soc/me.h index 041769b19a..ba4a11a64c 100644 --- a/src/soc/intel/cannonlake/include/soc/me.h +++ b/src/soc/intel/cannonlake/include/soc/me.h @@ -44,6 +44,20 @@ union me_hfsts1 { } __packed fields; }; +/* ME Host Firmware Status Register 3 */ +union me_hfsts3 { + u32 data; + struct { + u32 reserved_0: 4; + u32 fw_sku: 3; + u32 reserved_7: 2; + u32 reserved_9: 2; + u32 resered_11: 3; + u32 resered_14: 16; + u32 reserved_30: 2; + } __packed fields; +}; + void dump_me_status(void *unused); #endif /* _CANNONLAKE_ME_H_ */ diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index c82f3bdc7a..39c30e9cb3 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -270,6 +270,13 @@ bool cse_is_hfs1_com_soft_temp_disable(void) return cse_check_hfs1_com(ME_HFS1_COM_SOFT_TEMP_DISABLE); } +bool cse_is_hfs3_fw_sku_custom(void) +{ + union me_hfsts3 hfs3; + hfs3.data = me_read_config32(PCI_ME_HFSTS3); + return hfs3.fields.fw_sku == ME_HFS3_FW_SKU_CUSTOM; +} + /* Makes the host ready to communicate with CSE */ void cse_set_host_ready(void) { diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 6f8f4ff34c..af8d85272d 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -186,4 +186,10 @@ bool cse_is_hfs1_com_secover_mei_msg(void); */ bool cse_is_hfs1_com_soft_temp_disable(void); +/* + * Checks CSE's Firmware SKU is Custom or not. + * Returns true if CSE's Firmware SKU is Custom, otherwise false + */ +bool cse_is_hfs3_fw_sku_custom(void); + #endif // SOC_INTEL_COMMON_CSE_H diff --git a/src/soc/intel/icelake/include/soc/me.h b/src/soc/intel/icelake/include/soc/me.h index b1646a2716..1146fdf848 100644 --- a/src/soc/intel/icelake/include/soc/me.h +++ b/src/soc/intel/icelake/include/soc/me.h @@ -40,4 +40,18 @@ union me_hfsts1 { } __packed fields; }; +/* ME Host Firmware Status Register 3 */ +union me_hfsts3 { + u32 data; + struct { + u32 reserved_0: 4; + u32 fw_sku: 3; + u32 reserved_7: 2; + u32 reserved_9: 2; + u32 resered_11: 3; + u32 resered_14: 16; + u32 reserved_30: 2; + } __packed fields; +}; + #endif /* _ICELAKE_ME_H_ */ diff --git a/src/soc/intel/tigerlake/include/soc/me.h b/src/soc/intel/tigerlake/include/soc/me.h index 3baa0045bd..9bb41ca57b 100644 --- a/src/soc/intel/tigerlake/include/soc/me.h +++ b/src/soc/intel/tigerlake/include/soc/me.h @@ -40,4 +40,17 @@ union me_hfsts1 { } __packed fields; }; +/* ME Host Firmware Status Register 3 */ +union me_hfsts3 { + u32 data; + struct { + u32 reserved_0: 4; + u32 fw_sku: 3; + u32 reserved_7: 2; + u32 reserved_9: 2; + u32 resered_11: 3; + u32 resered_14: 16; + u32 reserved_30: 2; + } __packed fields; +}; #endif /* _TIGERLAKE_ME_H_ */ -- cgit v1.2.3