From 3d3f438937f9359ecb58f1c18a910a8302404ad5 Mon Sep 17 00:00:00 2001 From: Eric Biederman Date: Sat, 12 Jul 2003 01:48:30 +0000 Subject: - Use an SMBUS_IO_BASE value that will not conflict with an automatically assigned value git-svn-id: svn://svn.coreboot.org/coreboot/trunk@955 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/amd/amd8111/amd8111_early_smbus.c | 2 +- src/southbridge/amd/amd8111/amd8111_enable_rom.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/amd8111/amd8111_early_smbus.c b/src/southbridge/amd/amd8111/amd8111_early_smbus.c index 33f558896e..e67d414933 100644 --- a/src/southbridge/amd/amd8111/amd8111_early_smbus.c +++ b/src/southbridge/amd/amd8111/amd8111_early_smbus.c @@ -1,4 +1,4 @@ -#define SMBUS_IO_BASE 0x1000 +#define SMBUS_IO_BASE 0x0f00 #define SMBGSTATUS 0xe0 #define SMBGCTL 0xe2 diff --git a/src/southbridge/amd/amd8111/amd8111_enable_rom.c b/src/southbridge/amd/amd8111/amd8111_enable_rom.c index 4aea04ccf5..425108dc9a 100644 --- a/src/southbridge/amd/amd8111/amd8111_enable_rom.c +++ b/src/southbridge/amd/amd8111/amd8111_enable_rom.c @@ -7,7 +7,7 @@ static void amd8111_enable_rom(void) /* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */ /* Locate the amd8111 */ addr = pci_locate_device(PCI_ID(0x1022, 0x7468), 0); - + /* Set the 4MB enable bit bit */ byte = pci_read_config8(addr, 0x43); byte |= 0x80; -- cgit v1.2.3