From 3ec008bf40613776173251652c8c33d563299d73 Mon Sep 17 00:00:00 2001 From: Xiang Wang Date: Sun, 8 Jul 2018 10:13:52 +0800 Subject: riscv: add include/arch/smp/ directory MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replicate directory layout from x86 for SMP. Change-Id: I27aee55f24d96ba9e7d8f2e6653f6c9c5e85c66a Signed-off-by: Xiang Wang Reviewed-on: https://review.coreboot.org/27355 Reviewed-by: Jonathan Neuschäfer Tested-by: build bot (Jenkins) --- src/arch/riscv/include/arch/smp/atomic.h | 88 ++++++++++++++++++++++++++++++ src/arch/riscv/include/arch/smp/spinlock.h | 12 ++++ src/arch/riscv/include/atomic.h | 67 ----------------------- src/arch/riscv/include/mcall.h | 1 - src/arch/riscv/mcall.c | 1 - 5 files changed, 100 insertions(+), 69 deletions(-) create mode 100644 src/arch/riscv/include/arch/smp/atomic.h create mode 100644 src/arch/riscv/include/arch/smp/spinlock.h delete mode 100644 src/arch/riscv/include/atomic.h diff --git a/src/arch/riscv/include/arch/smp/atomic.h b/src/arch/riscv/include/arch/smp/atomic.h new file mode 100644 index 0000000000..de7fd19bd3 --- /dev/null +++ b/src/arch/riscv/include/arch/smp/atomic.h @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2013, The Regents of the University of California (Regents). + * Copyright (c) 2018, HardenedLinux. + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Regents nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, + * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING + * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED + * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE + * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. + */ + +#ifndef _RISCV_ATOMIC_H +#define _RISCV_ATOMIC_H + +#include + +typedef struct { volatile int counter; } atomic_t; + +#define disable_irqsave() clear_csr(mstatus, MSTATUS_MIE) +#define enable_irqrestore(flags) set_csr(mstatus, (flags) & MSTATUS_MIE) + +#define atomic_set(v, val) ((v)->counter = (val)) +#define atomic_read(v) ((v)->counter) + +#ifdef __riscv_atomic +# define atomic_add(v, inc) __sync_fetch_and_add(&((v)->counter), inc) +# define atomic_swap(v, swp) __sync_lock_test_and_set(&((v)->counter), swp) +# define atomic_cas(v, cmp, swp) __sync_val_compare_and_swap(&((v)->counter), \ + cmp, swp) +# define atomic_inc(v) atomic_add(v, 1) +# define atomic_dec(v) atomic_add(v, -1) +#else +static inline int atomic_add(atomic_t *v, int inc) +{ + long flags = disable_irqsave(); + int res = v->counter; + v->counter += inc; + enable_irqrestore(flags); + return res; +} + +static inline int atomic_swap(atomic_t *v, int swp) +{ + long flags = disable_irqsave(); + int res = v->counter; + v->counter = swp; + enable_irqrestore(flags); + return res; +} + +static inline int atomic_cas(atomic_t *v, int cmp, int swp) +{ + long flags = disable_irqsave(); + int res = v->counter; + v->counter = (res == cmp ? swp : res); + enable_irqrestore(flags); + return res; +} + +static inline int atomic_inc(atomic_t *v) +{ + return atomic_add(v, 1); +} + +static inline int atomic_dec(atomic_t *v) +{ + return atomic_add(v, -1); +} +#endif //__riscv_atomic + +#endif //_RISCV_ATOMIC_H diff --git a/src/arch/riscv/include/arch/smp/spinlock.h b/src/arch/riscv/include/arch/smp/spinlock.h new file mode 100644 index 0000000000..bdf8ec4584 --- /dev/null +++ b/src/arch/riscv/include/arch/smp/spinlock.h @@ -0,0 +1,12 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ diff --git a/src/arch/riscv/include/atomic.h b/src/arch/riscv/include/atomic.h deleted file mode 100644 index 15702e445f..0000000000 --- a/src/arch/riscv/include/atomic.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (c) 2013, The Regents of the University of California (Regents). - * All Rights Reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Regents nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, - * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING - * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS - * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED - * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE - * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. - */ - -#ifndef _RISCV_ATOMIC_H -#define _RISCV_ATOMIC_H - -#include - -#define disable_irqsave() clear_csr(mstatus, MSTATUS_MIE) -#define enable_irqrestore(flags) set_csr(mstatus, (flags) & MSTATUS_MIE) - -typedef struct { int lock; } spinlock_t; -#define SPINLOCK_INIT {0} - -#define atomic_set(ptr, val) (*(volatile typeof(*(ptr)) *)(ptr) = val) -#define atomic_read(ptr) (*(volatile typeof(*(ptr)) *)(ptr)) - -#ifdef __riscv_atomic -# define atomic_add(ptr, inc) __sync_fetch_and_add(ptr, inc) -# define atomic_swap(ptr, swp) __sync_lock_test_and_set(ptr, swp) -# define atomic_cas(ptr, cmp, swp) __sync_val_compare_and_swap(ptr, cmp, swp) -#else -# define atomic_add(ptr, inc) ({ \ - long flags = disable_irqsave(); \ - typeof(ptr) res = *(volatile typeof(ptr))(ptr); \ - *(volatile typeof(ptr))(ptr) = res + (inc); \ - enable_irqrestore(flags); \ - res; }) -# define atomic_swap(ptr, swp) ({ \ - long flags = disable_irqsave(); \ - typeof(*ptr) res = *(volatile typeof(ptr))(ptr); \ - *(volatile typeof(ptr))(ptr) = (swp); \ - enable_irqrestore(flags); \ - res; }) -# define atomic_cas(ptr, cmp, swp) ({ \ - long flags = disable_irqsave(); \ - typeof(ptr) res = *(volatile typeof(ptr))(ptr); \ - if (res == (cmp)) *(volatile typeof(ptr))(ptr) = (swp); \ - enable_irqrestore(flags); \ - res; }) -#endif - -#endif diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h index e4bc36f080..114808aae7 100644 --- a/src/arch/riscv/include/mcall.h +++ b/src/arch/riscv/include/mcall.h @@ -26,7 +26,6 @@ #ifndef __ASSEMBLER__ #include -#include #include typedef struct { diff --git a/src/arch/riscv/mcall.c b/src/arch/riscv/mcall.c index 030accfe1d..2e44fb76fe 100644 --- a/src/arch/riscv/mcall.c +++ b/src/arch/riscv/mcall.c @@ -27,7 +27,6 @@ #include #include -#include #include #include #include -- cgit v1.2.3