From 3f672323b5f5cd6eaf955a31ebd0f73685f1d257 Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Wed, 22 Nov 2017 13:48:12 -0800 Subject: soc/intel/common/block/gpio: Change group offset calculation Add group information for each gpio community and use it to calculate offset of a pad within its group. Original implementation assumed that the number of gpios in each group is same but that lead to a bug for cnl since numbers differ for each group. BUG=b:69616750 TEST=Need to test again on SKL,CNL,APL,GLK Change-Id: I02ab1d878bc83d32222be074bd2db5e23adaf580 Signed-off-by: Bora Guvendik Reviewed-on: https://review.coreboot.org/22571 Reviewed-by: Lijian Zhao Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/apollolake/gpio_apl.c | 30 ++++++++++++++++ src/soc/intel/apollolake/gpio_glk.c | 30 ++++++++++++++++ src/soc/intel/cannonlake/gpio.c | 40 +++++++++++++++++++++ src/soc/intel/common/block/gpio/gpio.c | 34 ++++++++++++++---- .../intel/common/block/include/intelblocks/gpio.h | 16 +++++++++ src/soc/intel/skylake/gpio.c | 41 ++++++++++++++++++++++ 6 files changed, 184 insertions(+), 7 deletions(-) diff --git a/src/soc/intel/apollolake/gpio_apl.c b/src/soc/intel/apollolake/gpio_apl.c index a774470fc5..265e613d61 100644 --- a/src/soc/intel/apollolake/gpio_apl.c +++ b/src/soc/intel/apollolake/gpio_apl.c @@ -27,6 +27,28 @@ static const struct reset_mapping rst_map[] = { { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, }; +static const struct pad_group apl_community_n_groups[] = { + INTEL_GPP(N_OFFSET, N_OFFSET, GPIO_31), /* NORTH 0 */ + INTEL_GPP(N_OFFSET, GPIO_32, TRST_B), /* NORTH 1 */ + INTEL_GPP(N_OFFSET, TMS, SVID0_CLK), /* NORTH 2 */ +}; + +static const struct pad_group apl_community_w_groups[] = { + INTEL_GPP(W_OFFSET, W_OFFSET, OSC_CLK_OUT_1),/* WEST 0 */ + INTEL_GPP(W_OFFSET, OSC_CLK_OUT_2, SUSPWRDNACK),/* WEST 1 */ +}; + +static const struct pad_group apl_community_sw_groups[] = { + INTEL_GPP(SW_OFFSET, SW_OFFSET, SMB_ALERTB), /* SOUTHWEST 0 */ + INTEL_GPP(SW_OFFSET, SMB_CLK, LPC_FRAMEB), /* SOUTHWEST 1 */ +}; + +static const struct pad_group apl_community_nw_groups[] = { + INTEL_GPP(NW_OFFSET, NW_OFFSET, PROCHOT_B), /* NORTHWEST 0 */ + INTEL_GPP(NW_OFFSET, PMIC_I2C_SCL, GPIO_106),/* NORTHWEST 1 */ + INTEL_GPP(NW_OFFSET, GPIO_109, GPIO_123), /* NORTHWEST 2 */ +}; + static const struct pad_community apl_gpio_communities[] = { { .port = PID_GPIO_SW, @@ -43,6 +65,8 @@ static const struct pad_community apl_gpio_communities[] = { .acpi_path = "\\_SB.GPO3", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = apl_community_sw_groups, + .num_groups = ARRAY_SIZE(apl_community_sw_groups), }, { .port = PID_GPIO_W, .first_pad = W_OFFSET, @@ -58,6 +82,8 @@ static const struct pad_community apl_gpio_communities[] = { .acpi_path = "\\_SB.GPO2", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = apl_community_w_groups, + .num_groups = ARRAY_SIZE(apl_community_w_groups), }, { .port = PID_GPIO_NW, .first_pad = NW_OFFSET, @@ -73,6 +99,8 @@ static const struct pad_community apl_gpio_communities[] = { .acpi_path = "\\_SB.GPO1", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = apl_community_nw_groups, + .num_groups = ARRAY_SIZE(apl_community_nw_groups), }, { .port = PID_GPIO_N, .first_pad = N_OFFSET, @@ -89,6 +117,8 @@ static const struct pad_community apl_gpio_communities[] = { .acpi_path = "\\_SB.GPO0", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = apl_community_n_groups, + .num_groups = ARRAY_SIZE(apl_community_n_groups), } }; diff --git a/src/soc/intel/apollolake/gpio_glk.c b/src/soc/intel/apollolake/gpio_glk.c index fd73270d22..a998118aa9 100644 --- a/src/soc/intel/apollolake/gpio_glk.c +++ b/src/soc/intel/apollolake/gpio_glk.c @@ -21,12 +21,34 @@ #include #include + static const struct reset_mapping rst_map[] = { { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 }, { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, }; +static const struct pad_group glk_community_audio_groups[] = { + INTEL_GPP(AUDIO_OFFSET, AUDIO_OFFSET, GPIO_175), /* AUDIO 0 */ +}; + +static const struct pad_group glk_community_nw_groups[] = { + INTEL_GPP(NW_OFFSET, NW_OFFSET, GPIO_31), /* NORTHWEST 0 */ + INTEL_GPP(NW_OFFSET, GPIO_32, GPIO_63), /* NORTHWEST 1 */ + INTEL_GPP(NW_OFFSET, GPIO_64, GPIO_214), /* NORTHWEST 2 */ +}; + +static const struct pad_group glk_community_scc_groups[] = { + INTEL_GPP(SCC_OFFSET, SCC_OFFSET, GPIO_206), /* SCC 0 */ + INTEL_GPP(SCC_OFFSET, GPIO_207, GPIO_209), /* SCC 1 */ +}; + +static const struct pad_group glk_community_n_groups[] = { + INTEL_GPP(N_OFFSET, N_OFFSET, GPIO_107), /* NORTH 0 */ + INTEL_GPP(N_OFFSET, GPIO_108, GPIO_139), /* NORTH 1 */ + INTEL_GPP(N_OFFSET, GPIO_140, GPIO_155), /* NORTH 2 */ +}; + static const struct pad_community glk_gpio_communities[] = { { .port = PID_GPIO_NW, @@ -43,6 +65,8 @@ static const struct pad_community glk_gpio_communities[] = { .acpi_path = "\\_SB.GPO0", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = glk_community_nw_groups, + .num_groups = ARRAY_SIZE(glk_community_nw_groups), }, { .port = PID_GPIO_N, .first_pad = N_OFFSET, @@ -58,6 +82,8 @@ static const struct pad_community glk_gpio_communities[] = { .acpi_path = "\\_SB.GPO1", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = glk_community_n_groups, + .num_groups = ARRAY_SIZE(glk_community_n_groups), }, { .port = PID_GPIO_AUDIO, .first_pad = AUDIO_OFFSET, @@ -73,6 +99,8 @@ static const struct pad_community glk_gpio_communities[] = { .acpi_path = "\\_SB.GPO2", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = glk_community_audio_groups, + .num_groups = ARRAY_SIZE(glk_community_audio_groups), }, { .port = PID_GPIO_SCC, .first_pad = SCC_OFFSET, @@ -89,6 +117,8 @@ static const struct pad_community glk_gpio_communities[] = { .acpi_path = "\\_SB.GPO3", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = glk_community_scc_groups, + .num_groups = ARRAY_SIZE(glk_community_scc_groups), }, }; diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c index cf10e4940f..0befba0b02 100644 --- a/src/soc/intel/cannonlake/gpio.c +++ b/src/soc/intel/cannonlake/gpio.c @@ -32,6 +32,36 @@ static const struct reset_mapping rst_map_com0[] = { { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 }, }; +static const struct pad_group cnl_community0_groups[] = { + INTEL_GPP(GPP_A0, GPP_A0, GPIO_RSVD_0), /* GPP_A */ + INTEL_GPP(GPP_A0, GPP_B0, GPIO_RSVD_2), /* GPP_B */ + INTEL_GPP(GPP_A0, GPP_G0, GPP_G7), /* GPP_G */ + INTEL_GPP(GPP_A0, GPIO_RSVD_3, GPIO_RSVD_11), /* SPI */ +}; + +static const struct pad_group cnl_community1_groups[] = { + INTEL_GPP(GPP_D0, GPP_D0, GPIO_RSVD_12), /* GPP_D */ + INTEL_GPP(GPP_D0, GPP_F0, GPP_F23), /* GPP_F */ + INTEL_GPP(GPP_D0, GPP_H0, GPP_H23), /* GPP_H */ + INTEL_GPP(GPP_D0, GPIO_RSVD_12, GPIO_RSVD_52), /* VGPIO */ +}; + +static const struct pad_group cnl_community2_groups[] = { + INTEL_GPP(GPD0, GPD0, GPD11), /* GPD */ +}; + +static const struct pad_group cnl_community3_groups[] = { + INTEL_GPP(HDA_BCLK, HDA_BCLK, SSP1_TXD), /* AZA */ + INTEL_GPP(HDA_BCLK, GPIO_RSVD_68, GPIO_RSVD_78), /* CPU */ +}; + +static const struct pad_group cnl_community4_groups[] = { + INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP_C */ + INTEL_GPP(GPP_C0, GPP_E0, GPP_E23), /* GPP_E */ + INTEL_GPP(GPP_C0, GPIO_RSVD_53, GPIO_RSVD_61), /* JTAG */ + INTEL_GPP(GPP_C0, GPIO_RSVD_62, GPIO_RSVD_67), /* HVMOS */ +}; + static const struct pad_community cnl_communities[] = { { /* GPP A, B, G, SPI */ .port = PID_GPIOCOM0, @@ -47,6 +77,8 @@ static const struct pad_community cnl_communities[] = { .acpi_path = "\\_SB.PCI0.GPIO", .reset_map = rst_map_com0, .num_reset_vals = ARRAY_SIZE(rst_map_com0), + .groups = cnl_community0_groups, + .num_groups = ARRAY_SIZE(cnl_community0_groups), }, { /* GPP D, F, H, VGPIO */ .port = PID_GPIOCOM1, .first_pad = GPP_D0, @@ -61,6 +93,8 @@ static const struct pad_community cnl_communities[] = { .acpi_path = "\\_SB.PCI0.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = cnl_community1_groups, + .num_groups = ARRAY_SIZE(cnl_community1_groups), }, { /* GPD */ .port = PID_GPIOCOM2, .first_pad = GPD0, @@ -75,6 +109,8 @@ static const struct pad_community cnl_communities[] = { .acpi_path = "\\_SB.PCI0.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = cnl_community2_groups, + .num_groups = ARRAY_SIZE(cnl_community2_groups), }, { /* AZA, CPU */ .port = PID_GPIOCOM3, .first_pad = HDA_BCLK, @@ -89,6 +125,8 @@ static const struct pad_community cnl_communities[] = { .acpi_path = "\\_SB.PCI0.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = cnl_community3_groups, + .num_groups = ARRAY_SIZE(cnl_community3_groups), }, { /* GPP C, E, JTAG, HVMOS */ .port = PID_GPIOCOM4, .first_pad = GPP_C0, @@ -103,6 +141,8 @@ static const struct pad_community cnl_communities[] = { .acpi_path = "\\_SB.PCI0.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = cnl_community4_groups, + .num_groups = ARRAY_SIZE(cnl_community4_groups), } }; diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index 6b6395544e..eea2554690 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -68,22 +68,42 @@ static inline size_t relative_pad_in_comm(const struct pad_community *comm, return gpio - comm->first_pad; } -static inline size_t gpio_group_index_scaled(const struct pad_community *comm, - unsigned int relative_pad, size_t scale) +/* find the group within the community that the pad is a part of */ +static inline size_t gpio_group_index(const struct pad_community *comm, + unsigned int relative_pad) { - return (relative_pad / comm->max_pads_per_group) * scale; + size_t i; + + assert(comm->groups != NULL); + + /* find the base pad number for this pad's group */ + for (i = 0; i < comm->num_groups; i++) { + if (relative_pad >= comm->groups[i].first_pad && + relative_pad < comm->groups[i].first_pad + + comm->groups[i].size) { + return i; + } + } + + assert(0); + + return i; } -static inline size_t gpio_group_index(const struct pad_community *comm, - unsigned int relative_pad) +static inline size_t gpio_group_index_scaled(const struct pad_community *comm, + unsigned int relative_pad, size_t scale) { - return gpio_group_index_scaled(comm, relative_pad, 1); + return gpio_group_index(comm, relative_pad) * scale; } static inline size_t gpio_within_group(const struct pad_community *comm, unsigned int relative_pad) { - return relative_pad % comm->max_pads_per_group; + size_t i; + + i = gpio_group_index(comm, relative_pad); + + return relative_pad - comm->groups[i].first_pad; } static inline uint32_t gpio_bitmask_within_group( diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h index 879d30b469..625ebef881 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio.h @@ -23,6 +23,12 @@ #ifndef __ACPI__ #include +#define INTEL_GPP(first_of_community, start_of_group, end_of_group) \ + { \ + .first_pad = (start_of_group) - (first_of_community), \ + .size = (end_of_group) - (start_of_group) + 1, \ + } + /* * Following should be defined in soc/gpio.h * GPIO_MISCCFG - offset to GPIO MISCCFG Register @@ -55,6 +61,14 @@ struct reset_mapping { uint32_t chipset; }; + +/* Structure describes the groups within each community */ +struct pad_group { + int first_pad; /* offset of first pad of the group relative + to the community */ + unsigned int size; /* Size of the group */ +}; + /* This structure will be used to describe a community or each group within a * community when multiple groups exist inside a community */ @@ -76,6 +90,8 @@ struct pad_community { const struct reset_mapping *reset_map; /* PADRSTCFG logical to chipset mapping */ size_t num_reset_vals; + const struct pad_group *groups; + size_t num_groups; }; /* diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index 9c9d041e4f..f67d4a3bb9 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -20,6 +20,7 @@ #include #include + static const struct reset_mapping rst_map[] = { { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30}, { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30}, @@ -33,6 +34,38 @@ static const struct reset_mapping rst_map_com2[] = { { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30}, }; +static const struct pad_group skl_community_com0_groups[] = { + INTEL_GPP(GPP_A0, GPP_A0, GPP_A23), /* GPP A */ + INTEL_GPP(GPP_A0, GPP_B0, GPP_B23), /* GPP B */ +}; + +static const struct pad_group skl_community_com1_groups[] = { + INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP C */ +#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) + INTEL_GPP(GPP_C0, GPP_D0, GPP_D23), /* GPP D */ + INTEL_GPP(GPP_C0, GPP_E0, GPP_E12), /* GPP E */ + INTEL_GPP(GPP_C0, GPP_F0, GPP_F23), /* GPP F */ + INTEL_GPP(GPP_C0, GPP_G0, GPP_G23), /* GPP G */ + INTEL_GPP(GPP_C0, GPP_H0, GPP_H23), /* GPP H */ +#else + INTEL_GPP(GPP_C0, GPP_D0, GPP_D23), /* GPP D */ + INTEL_GPP(GPP_C0, GPP_E0, GPP_E23), /* GPP E */ +#endif +}; + +static const struct pad_group skl_community_com3_groups[] = { +#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) + INTEL_GPP(GPP_I0, GPP_I0, GPP_I10), /* GPP I */ +#else + INTEL_GPP(GPP_F0, GPP_F0, GPP_F23), /* GPP F */ + INTEL_GPP(GPP_F0, GPP_G0, GPP_G7), /* GPP G */ +#endif +}; + +static const struct pad_group skl_community_com2_groups[] = { + INTEL_GPP(GPD0, GPD0, GPD11), /* GPP GDP */ +}; + static const struct pad_community skl_gpio_communities[] = { { .port = PID_GPIOCOM0, @@ -48,6 +81,8 @@ static const struct pad_community skl_gpio_communities[] = { .acpi_path = "\\_SB.PCI0.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = skl_community_com0_groups, + .num_groups = ARRAY_SIZE(skl_community_com0_groups), }, { .port = PID_GPIOCOM1, .first_pad = GPP_C0, @@ -66,6 +101,8 @@ static const struct pad_community skl_gpio_communities[] = { .acpi_path = "\\_SB.PCI0.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = skl_community_com1_groups, + .num_groups = ARRAY_SIZE(skl_community_com1_groups), }, { .port = PID_GPIOCOM3, #if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) @@ -85,6 +122,8 @@ static const struct pad_community skl_gpio_communities[] = { .acpi_path = "\\_SB.PCI0.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = skl_community_com3_groups, + .num_groups = ARRAY_SIZE(skl_community_com3_groups), }, { .port = PID_GPIOCOM2, .first_pad = GPD0, @@ -99,6 +138,8 @@ static const struct pad_community skl_gpio_communities[] = { .acpi_path = "\\_SB.PCI0.GPIO", .reset_map = rst_map_com2, .num_reset_vals = ARRAY_SIZE(rst_map_com2), + .groups = skl_community_com2_groups, + .num_groups = ARRAY_SIZE(skl_community_com2_groups), } }; -- cgit v1.2.3