From 400ce55566caa541304b2483e61bcc2df941998c Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 12 Oct 2018 10:54:30 +0200 Subject: cpu/amd: Use common AMD's MSR Phase 1. Due to the size of the effort, this CL is broken into several phases. Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/29065 Tested-by: build bot (Jenkins) Reviewed-by: Richard Spiegel --- src/cpu/amd/agesa/family12/fixme.c | 3 +- src/cpu/amd/agesa/family12/model_12_init.c | 12 ++-- src/cpu/amd/agesa/family14/fixme.c | 6 +- src/cpu/amd/agesa/family14/model_14_init.c | 12 ++-- src/cpu/amd/agesa/family15tn/fixme.c | 3 +- src/cpu/amd/agesa/family15tn/model_15_init.c | 18 +++--- src/cpu/amd/agesa/family15tn/udelay.c | 5 +- src/cpu/amd/agesa/family16kb/fixme.c | 3 +- src/cpu/amd/agesa/family16kb/model_16_init.c | 8 +-- src/cpu/amd/car/cache_as_ram.inc | 20 +++--- src/cpu/amd/car/disable_cache_as_ram.c | 17 ++--- src/cpu/amd/family_10h-family_15h/defaults.h | 61 +++++++++--------- src/cpu/amd/family_10h-family_15h/fidvid.c | 74 +++++++++++----------- src/cpu/amd/family_10h-family_15h/init_cpus.c | 45 ++++++------- .../amd/family_10h-family_15h/model_10xxx_init.c | 10 ++- .../amd/family_10h-family_15h/monotonic_timer.c | 5 +- src/cpu/amd/family_10h-family_15h/powernow_acpi.c | 16 +++-- src/cpu/amd/family_10h-family_15h/tsc_freq.c | 3 +- src/cpu/amd/pi/00630F01/fixme.c | 4 +- src/cpu/amd/pi/00630F01/model_15_init.c | 18 +++--- src/cpu/amd/pi/00630F01/udelay.c | 5 +- src/cpu/amd/pi/00660F01/fixme.c | 4 +- src/cpu/amd/pi/00660F01/model_15_init.c | 8 +-- src/cpu/amd/pi/00730F01/fixme.c | 4 +- src/cpu/amd/pi/00730F01/model_16_init.c | 8 +-- src/include/cpu/amd/amdfam12.h | 30 --------- src/include/cpu/amd/amdfam14.h | 30 --------- src/include/cpu/amd/amdfam15.h | 29 --------- src/include/cpu/amd/amdfam16.h | 34 ---------- src/include/cpu/amd/msr.h | 57 +++++++++++++++-- src/include/cpu/x86/msr.h | 2 + src/mainboard/advansus/a785e-i/romstage.c | 5 +- src/mainboard/amd/bimini_fam10/romstage.c | 5 +- src/mainboard/amd/mahogany_fam10/romstage.c | 5 +- .../amd/serengeti_cheetah_fam10/romstage.c | 5 +- src/mainboard/amd/tilapia_fam10/romstage.c | 5 +- src/mainboard/asus/kcma-d8/romstage.c | 5 +- src/mainboard/asus/kfsn4-dre/romstage.c | 5 +- src/mainboard/asus/kgpe-d16/romstage.c | 5 +- src/mainboard/asus/m4a78-em/romstage.c | 5 +- src/mainboard/asus/m4a785-m/romstage.c | 5 +- src/mainboard/asus/m5a88-v/romstage.c | 5 +- src/mainboard/avalue/eax-785e/romstage.c | 5 +- src/mainboard/gigabyte/ma785gm/romstage.c | 5 +- src/mainboard/gigabyte/ma785gmt/romstage.c | 5 +- src/mainboard/gigabyte/ma78gm/romstage.c | 5 +- src/mainboard/hp/dl165_g6_fam10/romstage.c | 5 +- src/mainboard/iei/kino-780am2-fam10/romstage.c | 5 +- src/mainboard/jetway/pa78vm5/romstage.c | 5 +- src/mainboard/msi/ms9652_fam10/romstage.c | 5 +- src/mainboard/supermicro/h8dmr_fam10/romstage.c | 5 +- src/mainboard/supermicro/h8qme_fam10/romstage.c | 5 +- src/mainboard/supermicro/h8scm_fam10/romstage.c | 5 +- src/mainboard/tyan/s2912_fam10/romstage.c | 5 +- src/northbridge/amd/agesa/family12/northbridge.c | 3 +- src/northbridge/amd/agesa/family14/northbridge.c | 6 +- src/northbridge/amd/agesa/family15tn/northbridge.c | 6 +- src/northbridge/amd/agesa/family16kb/northbridge.c | 6 +- src/northbridge/amd/amdfam10/northbridge.c | 3 +- src/northbridge/amd/amdht/AsPsDefs.h | 14 ---- src/northbridge/amd/amdmct/amddefs.h | 36 ----------- src/northbridge/amd/amdmct/mct/mct_d.c | 16 ++--- src/northbridge/amd/amdmct/mct/mctdqs_d.c | 7 +- src/northbridge/amd/amdmct/mct/mctsrc.c | 7 +- src/northbridge/amd/amdmct/mct/mcttmrl.c | 7 +- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 17 ++--- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 11 ++-- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 20 +++--- src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c | 5 +- src/northbridge/amd/pi/00630F01/northbridge.c | 16 ++--- src/northbridge/amd/pi/00660F01/northbridge.c | 13 ++-- src/northbridge/amd/pi/00730F01/northbridge.c | 13 ++-- src/soc/amd/stoneyridge/bootblock/bootblock.c | 1 + src/soc/amd/stoneyridge/cpu.c | 6 +- src/soc/amd/stoneyridge/finalize.c | 6 +- src/soc/amd/stoneyridge/mca.c | 12 ++-- src/soc/amd/stoneyridge/northbridge.c | 1 + src/soc/amd/stoneyridge/ramtop.c | 6 +- src/soc/amd/stoneyridge/tsc_freq.c | 2 +- src/southbridge/amd/rs780/early_setup.c | 5 +- src/southbridge/amd/sr5650/early_setup.c | 5 +- src/southbridge/amd/sr5650/sr5650.c | 3 +- 82 files changed, 412 insertions(+), 510 deletions(-) delete mode 100644 src/include/cpu/amd/amdfam12.h delete mode 100644 src/include/cpu/amd/amdfam14.h delete mode 100644 src/include/cpu/amd/amdfam16.h diff --git a/src/cpu/amd/agesa/family12/fixme.c b/src/cpu/amd/agesa/family12/fixme.c index d946e1bb13..084cae8456 100644 --- a/src/cpu/amd/agesa/family12/fixme.c +++ b/src/cpu/amd/agesa/family12/fixme.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include "amdlib.h" @@ -75,7 +76,7 @@ void amd_initmmio(void) Address MSR register. */ MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); + LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader); /* Enable Non-Post Memory in CPU */ PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1; diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c index c2f3495eca..c81b18ea72 100644 --- a/src/cpu/amd/agesa/family12/model_12_init.c +++ b/src/cpu/amd/agesa/family12/model_12_init.c @@ -15,6 +15,8 @@ #include #include +#include +#include #include #include #include @@ -23,13 +25,7 @@ #include #include #include -#include #include -#include - -#define MCG_CAP 0x179 -# define MCA_BANKS_MASK 0xff -#define MC0_STATUS 0x401 static void model_12_init(struct device *dev) { @@ -55,12 +51,12 @@ static void model_12_init(struct device *dev) disable_cache(); /* zero the machine check error status registers */ - msr = rdmsr(MCG_CAP); + msr = rdmsr(IA32_MCG_CAP); num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; for (i = 0; i < num_banks; i++) - wrmsr(MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC0_STATUS + (i * 4), msr); enable_cache(); diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index 7d595853e6..33e164354e 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -14,7 +14,7 @@ */ #include - +#include #include #include #include "amdlib.h" @@ -78,7 +78,7 @@ void amd_initmmio(void) Address MSR register. */ MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); + LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader); /* Set Ontario Link Data */ PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE0); @@ -96,7 +96,7 @@ void amd_initmmio(void) /* Set P-state 0 (1600 MHz) early to save a few ms of boot time */ MsrReg = 0; - LibAmdMsrWrite (0xC0010062, &MsrReg, &StdHeader); + LibAmdMsrWrite(PS_CTL_REG, &MsrReg, &StdHeader); } void amd_initenv(void) diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index b49d975761..3f0501e5cb 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -15,6 +15,8 @@ #include #include +#include +#include #include #include #include @@ -23,15 +25,9 @@ #include #include #include -#include -#include #include #include -#define MCG_CAP 0x179 -# define MCA_BANKS_MASK 0xff -#define MC0_STATUS 0x401 - static void model_14_init(struct device *dev) { u8 i; @@ -78,12 +74,12 @@ static void model_14_init(struct device *dev) x86_enable_cache(); /* zero the machine check error status registers */ - msr = rdmsr(MCG_CAP); + msr = rdmsr(IA32_MCG_CAP); num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; for (i = 0; i < num_banks; i++) - wrmsr(MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC0_STATUS + (i * 4), msr); /* Enable the local CPU APICs */ setup_lapic(); diff --git a/src/cpu/amd/agesa/family15tn/fixme.c b/src/cpu/amd/agesa/family15tn/fixme.c index 2eb96891a0..847f75393f 100644 --- a/src/cpu/amd/agesa/family15tn/fixme.c +++ b/src/cpu/amd/agesa/family15tn/fixme.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include "amdlib.h" @@ -71,7 +72,7 @@ void amd_initmmio(void) Address MSR register. */ MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); + LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader); /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index fdcb9a2332..d188bcc84b 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -15,8 +15,10 @@ #include #include -#include +#include +#include #include +#include #include #include #include @@ -24,8 +26,6 @@ #include #include #include -#include -#include #include #include @@ -73,12 +73,12 @@ static void model_15_init(struct device *dev) x86_enable_cache(); /* zero the machine check error status registers */ - msr = rdmsr(MCG_CAP); + msr = rdmsr(IA32_MCG_CAP); num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; for (i = 0; i < num_banks; i++) - wrmsr(MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC0_STATUS + (i * 4), msr); /* Enable the local CPU APICs */ setup_lapic(); @@ -108,14 +108,14 @@ static void model_15_init(struct device *dev) printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx); /* Set SMM base address for this CPU */ - msr = rdmsr(MSR_SMM_BASE); + msr = rdmsr(SMM_BASE_MSR); msr.lo = SMM_BASE - (cpu_idx * 0x400); - wrmsr(MSR_SMM_BASE, msr); + wrmsr(SMM_BASE_MSR, msr); /* Enable the SMM memory window */ - msr = rdmsr(MSR_SMM_MASK); + msr = rdmsr(SMM_MASK_MSR); msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */ - wrmsr(MSR_SMM_MASK, msr); + wrmsr(SMM_MASK_MSR, msr); } /* Write protect SMM space with SMMLOCK. */ diff --git a/src/cpu/amd/agesa/family15tn/udelay.c b/src/cpu/amd/agesa/family15tn/udelay.c index 3d40fc3b33..7ff4c5c7a8 100644 --- a/src/cpu/amd/agesa/family15tn/udelay.c +++ b/src/cpu/amd/agesa/family15tn/udelay.c @@ -21,6 +21,7 @@ */ #include +#include #include #include #include @@ -36,11 +37,11 @@ void udelay(uint32_t us) tsc_start = rdtscll(); /* Get the P-state. This determines which MSR to read */ - msr = rdmsr(0xc0010063); + msr = rdmsr(PS_STS_REG); pstate_idx = msr.lo & 0x07; /* Get FID and VID for current P-State */ - msr = rdmsr(0xc0010064 + pstate_idx); + msr = rdmsr(PSTATE_0_MSR + pstate_idx); /* Extract the FID and VID values */ fid = msr.lo & 0x3f; diff --git a/src/cpu/amd/agesa/family16kb/fixme.c b/src/cpu/amd/agesa/family16kb/fixme.c index 4ea52cc6e0..1f22307f1e 100644 --- a/src/cpu/amd/agesa/family16kb/fixme.c +++ b/src/cpu/amd/agesa/family16kb/fixme.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include "amdlib.h" @@ -71,7 +72,7 @@ void amd_initmmio(void) Address MSR register. */ MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); + LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader); /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index 1b5db23ff5..286bcc377b 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -15,6 +15,8 @@ #include #include +#include +#include #include #include #include @@ -23,8 +25,6 @@ #include #include #include -#include -#include #include #include @@ -71,12 +71,12 @@ static void model_16_init(struct device *dev) x86_enable_cache(); /* zero the machine check error status registers */ - msr = rdmsr(MCG_CAP); + msr = rdmsr(IA32_MCG_CAP); num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; for (i = 0; i < num_banks; i++) - wrmsr(MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC0_STATUS + (i * 4), msr); /* Enable the local CPU APICs */ setup_lapic(); diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index c773bd65bc..7cbf1dbcbb 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -17,6 +17,7 @@ #include #include +#include #include #define CacheSize CONFIG_DCACHE_RAM_SIZE @@ -27,9 +28,6 @@ /* For CAR with Fam10h. */ #define CacheSizeAPStack CONFIG_DCACHE_AP_STACK_SIZE -#define MSR_MCFG_BASE 0xC0010058 -#define MSR_BU_CFG2 0xC001102A - #define jmp_if_not_k8(x) comisd %xmm2, %xmm1; jae x #define jmp_if_k8(x) comisd %xmm2, %xmm1; jb x #define jmp_if_not_fam15h(x) comisd %xmm3, %xmm1; jb x @@ -130,13 +128,13 @@ CAR_FAM10_out: * Errata 193: Disable clean copybacks to L3 cache to allow cached ROM. * Re-enable it in after RAM is initialized and before CAR is disabled. */ - movl $MSR_BU_CFG2, %ecx + movl $BU_CFG2_MSR, %ecx rdmsr bts $15, %eax /* Set bit 15 in EDX:EAX (bit 15 in EAX). */ wrmsr /* Erratum 343, RevGuide for Fam10h, Pub#41322 Rev. 3.33 */ - movl $MSR_BU_CFG2, %ecx + movl $BU_CFG2_MSR, %ecx rdmsr bts $35-32, %edx /* Set bit 35 in EDX:EAX (bit 3 in EDX). */ wrmsr @@ -171,7 +169,7 @@ CAR_FAM10_errata_applied: #else #error "bad MMCONF_BUS_NUMBER value" #endif - movl $MSR_MCFG_BASE, %ecx + movl $MMIO_CONF_BASE, %ecx wrmsr #endif @@ -179,7 +177,7 @@ CAR_FAM10_out_post_errata: /* Fam15h APIC IDs do not depend on NB config bit 54 */ jmp_if_not_fam15h(skip_nb54_set) - movl $0xc001001f, %ecx /* NB_CFG_MSR */ + movl $NB_CFG_MSR, %ecx rdmsr bts $(54 - 32), %edx /* Set NB config bit 54 */ wrmsr @@ -227,7 +225,7 @@ skip_cu_check: jmp_if_not_fam15h(CAR_FAM15_errata_applied) /* Erratum 714, RevGuide for Fam15h, Pub#48063 Rev. 3.24 */ - movl $MSR_BU_CFG2, %ecx + movl $BU_CFG2_MSR, %ecx rdmsr bts $8, %eax /* Set bit 8 in EDX:EAX (bit 8 in EAX). */ wrmsr @@ -410,7 +408,7 @@ fam10_mtrr_setup_complete: post_code(0xa1) /* Disable conversion of INVD to WBINVD (INVDWBINVD = 0) */ - mov $0xc0010015, %ecx + mov $HWCR_MSR, %ecx rdmsr btr $4, %eax wrmsr @@ -522,7 +520,7 @@ CAR_FAM10_ap: * system with no obvious clues of what went wrong. * * So, need to get the NodeID and CoreID at first. - * If NB_CFG bit 54 is set just use initial APIC ID, otherwise need + * If NB_CFG_MSR bit 54 is set just use initial APIC ID, otherwise need * to reverse it. */ @@ -539,7 +537,7 @@ CAR_FAM10_ap: shrl $24, %ebx /* Get the nb cfg bit 54. */ - movl $0xc001001f, %ecx /* NB_CFG_MSR */ + movl $NB_CFG_MSR, %ecx rdmsr movl %edi, %ecx /* CoreID bits */ bt $(54 - 32), %edx diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c index a079ce49b1..5eda660775 100644 --- a/src/cpu/amd/car/disable_cache_as_ram.c +++ b/src/cpu/amd/car/disable_cache_as_ram.c @@ -21,6 +21,7 @@ #include #include +#include static __always_inline uint32_t amd_fam1x_cpu_family(void) { @@ -72,9 +73,9 @@ void disable_cache_as_ram_real(uint8_t skip_sharedc_config) } /* INVDWBINVD = 1 */ - msr = rdmsr(0xc0010015); + msr = rdmsr(HWCR_MSR); msr.lo |= (0x1 << 4); - wrmsr(0xc0010015, msr); + wrmsr(HWCR_MSR, msr); family = amd_fam1x_cpu_family(); @@ -83,15 +84,15 @@ void disable_cache_as_ram_real(uint8_t skip_sharedc_config) /* Family 15h or later */ /* DisSS = 0 */ - msr = rdmsr(0xc0011020); + msr = rdmsr(LS_CFG_MSR); msr.lo &= ~(0x1 << 28); - wrmsr(0xc0011020, msr); + wrmsr(LS_CFG_MSR, msr); if (!skip_sharedc_config) { /* DisSpecTlbRld = 0 */ - msr = rdmsr(0xc0011021); + msr = rdmsr(IC_CFG_MSR); msr.lo &= ~(0x1 << 9); - wrmsr(0xc0011021, msr); + wrmsr(IC_CFG_MSR, msr); /* Erratum 714: SpecNbReqDis = 0 */ msr = rdmsr(BU_CFG2_MSR); @@ -101,10 +102,10 @@ void disable_cache_as_ram_real(uint8_t skip_sharedc_config) /* DisSpecTlbRld = 0 */ /* DisHwPf = 0 */ - msr = rdmsr(0xc0011022); + msr = rdmsr(DC_CFG_MSR); msr.lo &= ~(0x1 << 4); msr.lo &= ~(0x1 << 13); - wrmsr(0xc0011022, msr); + wrmsr(DC_CFG_MSR, msr); } #endif } diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h index 50b3d07a0d..edf69f773d 100644 --- a/src/cpu/amd/family_10h-family_15h/defaults.h +++ b/src/cpu/amd/family_10h-family_15h/defaults.h @@ -16,6 +16,7 @@ #include #include +#include /* * Default MSR and errata settings. @@ -33,7 +34,7 @@ static const struct { 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF }, - { SYSCFG, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, + { SYSCFG_MSR, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, 3 << 21, 0x00000000, 3 << 21, 0x00000000 }, /* [MtrrTom2En]=1,[TOM2EnWB] = 1*/ @@ -65,92 +66,92 @@ static const struct { 1 << 10, 0x00000000, 1 << 10, 0x00000000 }, /* [GartTblWkEn]=1 */ - { DC_CFG, AMD_FAM10_ALL, AMD_PTYPE_SVR, + { DC_CFG_MSR, AMD_FAM10_ALL, AMD_PTYPE_SVR, 0x00000000, 0x00000004, 0x00000000, 0x0000000C }, /* Family 10h: [REQ_CTR] = 1 for Server */ - { DC_CFG, AMD_DR_Bx, AMD_PTYPE_SVR, + { DC_CFG_MSR, AMD_DR_Bx, AMD_PTYPE_SVR, 0x00000000, 0x00000000, 0x00000000, 0x00000C00 }, /* Erratum 326 */ - { NB_CFG, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_DC | AMD_PTYPE_MC, + { NB_CFG_MSR, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_DC | AMD_PTYPE_MC, 0x00000000, 1 << 22, 0x00000000, 1 << 22 }, /* [ApicInitIDLo]=1 */ - { NB_CFG, AMD_FAM15_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC, + { NB_CFG_MSR, AMD_FAM15_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC, 1 << 23, 0x00000000, 1 << 23, 0x00000000 }, /* Erratum 663: [bit 23]=1 */ - { BU_CFG2, AMD_DR_Bx, AMD_PTYPE_ALL, + { BU_CFG2_MSR, AMD_DR_Bx, AMD_PTYPE_ALL, 1 << 29, 0x00000000, 1 << 29, 0x00000000 }, /* For Bx Smash1GPages=1 */ - { DC_CFG, AMD_FAM10_ALL, AMD_PTYPE_ALL, + { DC_CFG_MSR, AMD_FAM10_ALL, AMD_PTYPE_ALL, 1 << 24, 0x00000000, 1 << 24, 0x00000000 }, /* Erratum #261 [DIS_PIGGY_BACK_SCRUB]=1 */ - { LS_CFG, AMD_DR_GT_B0, AMD_PTYPE_ALL, + { LS_CFG_MSR, AMD_DR_GT_B0, AMD_PTYPE_ALL, 0 << 1, 0x00000000, 1 << 1, 0x00000000 }, /* IDX_MATCH_ALL=0 */ - { IC_CFG, AMD_OR_C0, AMD_PTYPE_ALL, + { IC_CFG_MSR, AMD_OR_C0, AMD_PTYPE_ALL, 0x00000000, 1 << (39-32), 0x00000000, 1 << (39-32)}, /* C0 or above [DisLoopPredictor]=1 */ - { IC_CFG, AMD_OR_C0, AMD_PTYPE_ALL, + { IC_CFG_MSR, AMD_OR_C0, AMD_PTYPE_ALL, 0xf << 1, 0x00000000, 0xf << 1, 0x00000000}, /* C0 or above [DisIcWayFilter]=0xf */ - { BU_CFG, AMD_DR_LT_B3, AMD_PTYPE_ALL, + { BU_CFG_MSR, AMD_DR_LT_B3, AMD_PTYPE_ALL, 1 << 21, 0x00000000, - 1 << 21, 0x00000000 }, /* Erratum #254 DR B1 BU_CFG[21]=1 */ + 1 << 21, 0x00000000 }, /* Erratum #254 DR B1 BU_CFG_MSR[21]=1 */ - { BU_CFG, AMD_DR_LT_B3, AMD_PTYPE_ALL, + { BU_CFG_MSR, AMD_DR_LT_B3, AMD_PTYPE_ALL, 1 << 23, 0x00000000, - 1 << 23, 0x00000000 }, /* Erratum #309 BU_CFG[23]=1 */ + 1 << 23, 0x00000000 }, /* Erratum #309 BU_CFG_MSR[23]=1 */ - { BU_CFG, AMD_FAM15_ALL, AMD_PTYPE_ALL, + { BU_CFG_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL, 0 << 10, 0x00000000, 1 << 10, 0x00000000 }, /* [DcacheAgressivePriority]=0 */ /* CPUID_EXT_FEATURES */ - { CPUIDFEATURES, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_DC | AMD_PTYPE_MC, + { CPU_ID_FEATURES_MSR, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_DC | AMD_PTYPE_MC, 1 << 28, 0x00000000, 1 << 28, 0x00000000 }, /* [HyperThreadFeatEn]=1 */ - { CPUIDFEATURES, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_DC, + { CPU_ID_FEATURES_MSR, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_DC, 0x00000000, 1 << (33-32), 0x00000000, 1 << (33-32) }, /* [ExtendedFeatEn]=1 */ - { DE_CFG, AMD_OR_B2, AMD_PTYPE_ALL, + { DE_CFG_MSR, AMD_OR_B2, AMD_PTYPE_ALL, 1 << 10, 0x00000000, 1 << 10, 0x00000000 }, /* Bx [ResyncPredSingleDispDis]=1 */ - { BU_CFG2, AMD_DRBH_Cx, AMD_PTYPE_ALL, + { BU_CFG2_MSR, AMD_DRBH_Cx, AMD_PTYPE_ALL, 0x00000000, 1 << (35-32), 0x00000000, 1 << (35-32) }, /* Erratum 343 (set to 0 after CAR, in post_cache_as_ram()/model_10xxx_init() ) */ - { BU_CFG3, AMD_OR_B2, AMD_PTYPE_ALL, + { BU_CFG3_MSR, AMD_OR_B2, AMD_PTYPE_ALL, 0x00000000, 1 << (42-32), 0x00000000, 1 << (42-32)}, /* Bx [PwcDisableWalkerSharing]=1 */ - { BU_CFG3, AMD_OR_C0, AMD_PTYPE_ALL, + { BU_CFG3_MSR, AMD_OR_C0, AMD_PTYPE_ALL, 1 << 22, 0x00000000, 1 << 22, 0x00000000}, /* C0 or above [PfcDoubleStride]=1 */ - { EX_CFG, AMD_OR_C0, AMD_PTYPE_ALL, + { EX_CFG_MSR, AMD_OR_C0, AMD_PTYPE_ALL, 0x00000000, 1 << (54-32), 0x00000000, 1 << (54-32)}, /* C0 or above [LateSbzResync]=1 */ - { LS_CFG2, AMD_OR_C0, AMD_PTYPE_ALL, + { LS_CFG2_MSR, AMD_OR_C0, AMD_PTYPE_ALL, 1 << 23, 0x00000000, 1 << 23, 0x00000000}, /* C0 or above [DisScbThreshold]=1 */ - { LS_CFG2, AMD_OR_C0, AMD_PTYPE_ALL, + { LS_CFG2_MSR, AMD_OR_C0, AMD_PTYPE_ALL, 1 << 14, 0x00000000, 1 << 14, 0x00000000}, /* C0 or above [ForceSmcCheckFlowStDis]=1 */ - { LS_CFG2, AMD_OR_C0, AMD_PTYPE_ALL, + { LS_CFG2_MSR, AMD_OR_C0, AMD_PTYPE_ALL, 1 << 12, 0x00000000, 1 << 12, 0x00000000}, /* C0 or above [ForceBusLockDis]=1 */ @@ -170,19 +171,19 @@ static const struct { 0x00000010, 0x00000000, 0xffffffff, 0x00000000}, /* OsvwId4 = 0x1 */ - { BU_CFG2, AMD_DR_Dx, AMD_PTYPE_ALL, + { BU_CFG2_MSR, AMD_DR_Dx, AMD_PTYPE_ALL, 0x00000000, 1 << (50-32), 0x00000000, 1 << (50-32)}, /* D0 or Above, RdMmExtCfgQwEn*/ - { BU_CFG2, AMD_FAM15_ALL, AMD_PTYPE_ALL, + { BU_CFG2_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL, 0x00000000, 0x0 << (36-32), 0x00000000, 0x3 << (36-32)}, /* [ThrottleNbInterface]=0 */ - { BU_CFG2, AMD_FAM15_ALL, AMD_PTYPE_ALL, + { BU_CFG2_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL, 1 << 10, 0x00000000, 1 << 10, 0x00000000}, /* [VicResyncChkEn]=1 */ - { BU_CFG2, AMD_FAM15_ALL, AMD_PTYPE_ALL, + { BU_CFG2_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL, 1 << 11, 0x00000000, 1 << 11, 0x00000000}, /* Erratum 503: [bit 11]=1 */ @@ -198,7 +199,7 @@ static const struct { 0x00000000, 1 << (55 - 32), 0x00000000, 1 << (55 - 32)}, /* [PerfCtrExtCore]=1 */ - { IBS_OP_DATA3, AMD_FAM15_ALL, AMD_PTYPE_ALL, + { IBS_OP_DATA3_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL, 0 << 16, 0x00000000, 1 << 16, 0x00000000}, /* [IbsDcMabHit]=0 */ diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index e4bb9a3e08..91b9ad7560 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -89,6 +89,7 @@ b.- prep_fid_change(...) */ +#include #include #include @@ -146,12 +147,12 @@ static void applyBoostFIDOffset(pci_devfn_t dev, uint32_t nodeid) && ((cpuid_ecx(0x80000008) & NC_MASK) == 5) ) { u32 core = get_node_core_id_x().coreid; u32 asymetricBoostThisCore = ((pci_read_config32(dev, 0x10C) >> (core*2))) & 3; - msr_t msr = rdmsr(PS_REG_BASE); + msr_t msr = rdmsr(PSTATE_0_MSR); u32 cpuFid = msr.lo & PS_CPU_FID_MASK; cpuFid = cpuFid + asymetricBoostThisCore; msr.lo &= ~PS_CPU_FID_MASK; msr.lo |= cpuFid; - wrmsr(PS_REG_BASE , msr); + wrmsr(PSTATE_0_MSR, msr); } else if (is_fam15h()) { uint32_t dword = pci_read_config32(NODE_PCI(nodeid, 4), 0x15c); uint8_t boost_count = (dword >> 2) & 0x7; @@ -173,12 +174,12 @@ static void enableNbPState1(pci_devfn_t dev) u32 nbVid1 = (pci_read_config32(dev, 0x1F4) & NB_VID1_MASK) >> NB_VID1_SHIFT; u32 i; for (i = nbPState; i < NM_PS_REG; i++) { - msr_t msr = rdmsr(PS_REG_BASE + i); + msr_t msr = rdmsr(PSTATE_0_MSR + i); if (msr.hi & PS_EN_MASK ) { msr.hi |= NB_DID_M_ON; msr.lo &= NB_VID_MASK_OFF; msr.lo |= ( nbVid1 << NB_VID_POS); - wrmsr(PS_REG_BASE + i, msr); + wrmsr(PSTATE_0_MSR + i, msr); } } } @@ -189,10 +190,10 @@ static u8 setPStateMaxVal(pci_devfn_t dev) { u8 i, maxpstate=0; for (i = 0; i < NM_PS_REG; i++) { - msr_t msr = rdmsr(PS_REG_BASE + i); + msr_t msr = rdmsr(PSTATE_0_MSR + i); if (msr.hi & PS_IDD_VALUE_MASK) { msr.hi |= PS_EN_MASK; - wrmsr(PS_REG_BASE + i, msr); + wrmsr(PSTATE_0_MSR + i, msr); } if (msr.hi & PS_EN_MASK) { maxpstate = i; @@ -215,16 +216,16 @@ static void dualPlaneOnly(pci_devfn_t dev) && (cpuRev & (AMD_DR_Cx | AMD_DR_Ex))) { if ((pci_read_config32(dev, 0x1FC) & DUAL_PLANE_ONLY_MASK) && (pci_read_config32(dev, 0xA0) & PVI_MODE)) { - if (cpuid_edx(0x80000007) & CPB_MASK) { + if (cpuid_edx(CPUID_EXT_PM) & CPB_MASK) { // revision E only, but E is apparently not supported yet, therefore untested - msr_t minPstate = rdmsr(0xC0010065); - wrmsr(0xC0010065, rdmsr(0xC0010068)); - wrmsr(0xC0010068, minPstate); + msr_t minPstate = rdmsr(PSTATE_1_MSR); + wrmsr(PSTATE_1_MSR, rdmsr(PSTATE_4_MSR)); + wrmsr(PSTATE_4_MSR, minPstate); } else { msr_t msr; msr.lo=0; msr.hi=0; - wrmsr(0xC0010064, rdmsr(0xC0010068) ); - wrmsr(0xC0010068, msr); + wrmsr(PSTATE_0_MSR, rdmsr(PSTATE_4_MSR)); + wrmsr(PSTATE_4_MSR, msr); } //FIXME: CPTC2 and HTC_REG should get max per node, not per core ? @@ -307,7 +308,7 @@ static void recalculateVsSlamTimeSettingOnCorePre(pci_devfn_t dev) prep_fid_change, one might use F4x1[F0:E0] instead, but theoretically MSRC001_00[68:64] are equal to them after reset. */ - msr = rdmsr(0xC0010064); + msr = rdmsr(PSTATE_0_MSR); highVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F); if (!(msr.hi & 0x80000000)) { printk(BIOS_ERR,"P-state info in MSRC001_0064 is invalid !!!\n"); @@ -325,15 +326,16 @@ static void recalculateVsSlamTimeSettingOnCorePre(pci_devfn_t dev) } /* Get PSmax's index */ - msr = rdmsr(0xC0010061); + msr = rdmsr(PS_LIM_REG); bValue = (u8) ((msr.lo >> PS_MAX_VAL_SHFT) & BIT_MASK_3); /* Get PSmax's VID */ - msr = rdmsr(0xC0010064 + bValue); + msr = rdmsr(PSTATE_0_MSR + bValue); lowVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F); if (!(msr.hi & 0x80000000)) { - printk(BIOS_ERR,"P-state info in MSR%8x is invalid !!!\n",0xC0010064 + bValue); - lowVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0+(bValue*4)) + printk(BIOS_ERR, "P-state info in MSR%8x is invalid !!!\n", + PSTATE_0_MSR + bValue); + lowVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0+(bValue*4)) >> PS_CPU_VID_SHFT) & 0x7F); } @@ -644,7 +646,7 @@ void prep_fid_change(void) static void waitCurrentPstate(u32 target_pstate) { msr_t initial_msr = rdmsr(TSC_MSR); - msr_t pstate_msr = rdmsr(CUR_PSTATE_MSR); + msr_t pstate_msr = rdmsr(PS_STS_REG); msr_t tsc_msr; u8 timedout; @@ -655,7 +657,7 @@ static void waitCurrentPstate(u32 target_pstate) { * misunderstand this... */ u32 corrected_timeout = ((pstate_msr.lo==1) - && (!(rdmsr(0xC0010065).lo & NB_DID_M_ON)) ) ? + && (!(rdmsr(PSTATE_1_MSR).lo & NB_DID_M_ON))) ? WAIT_PSTATE_TIMEOUT*2 : WAIT_PSTATE_TIMEOUT; msr_t timeout; @@ -667,19 +669,19 @@ static void waitCurrentPstate(u32 target_pstate) { // assuming TSC ticks at 1.25 ns per tick (800 MHz) do { - pstate_msr = rdmsr(CUR_PSTATE_MSR); + pstate_msr = rdmsr(PS_STS_REG); tsc_msr = rdmsr(TSC_MSR); timedout = (tsc_msr.hi > timeout.hi) || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo )); } while ( (pstate_msr.lo != target_pstate) && (! timedout) ); if (pstate_msr.lo != target_pstate) { - msr_t limit_msr = rdmsr(0xc0010061); + msr_t limit_msr = rdmsr(PS_LIM_REG); printk(BIOS_ERR, "*** APIC ID %02x: timed out waiting for P-state %01x. Current P-state %01x P-state current limit MSRC001_0061=%08x %08x\n", cpuid_ebx(0x00000001) >> 24, target_pstate, pstate_msr.lo, limit_msr.hi, limit_msr.lo); do { // should we just go on instead ? - pstate_msr = rdmsr(CUR_PSTATE_MSR); + pstate_msr = rdmsr(PS_STS_REG); } while ( pstate_msr.lo != target_pstate ); } } @@ -689,10 +691,10 @@ static void set_pstate(u32 nonBoostedPState) { uint8_t skip_wait; // Transition P0 for calling core. - msr = rdmsr(0xC0010062); + msr = rdmsr(PS_CTL_REG); msr.lo = nonBoostedPState; - wrmsr(0xC0010062, msr); + wrmsr(PS_CTL_REG, msr); if (is_fam15h()) { /* Do not wait for the first (even) set of cores to transition on Family 15h systems */ @@ -718,7 +720,7 @@ static void UpdateSinglePlaneNbVid(void) /* copy higher voltage (lower VID) of NBVID & CPUVID to both */ for (i = 0; i < 5; i++) { - msr = rdmsr(PS_REG_BASE + i); + msr = rdmsr(PSTATE_0_MSR + i); nbVid = (msr.lo & PS_CPU_VID_M_ON) >> PS_CPU_VID_SHFT; cpuVid = (msr.lo & PS_NB_VID_M_ON) >> PS_NB_VID_SHFT; @@ -729,7 +731,7 @@ static void UpdateSinglePlaneNbVid(void) msr.lo = msr.lo & PS_BOTH_VID_OFF; msr.lo = msr.lo | (u32) ((nbVid) << PS_NB_VID_SHFT); msr.lo = msr.lo | (u32) ((nbVid) << PS_CPU_VID_SHFT); - wrmsr(PS_REG_BASE + i, msr); + wrmsr(PSTATE_0_MSR + i, msr); } } } @@ -751,16 +753,16 @@ static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid, u32 dev, u8 pviMode) * for SVI and Single-Plane PVI Systems */ - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); startup_pstate = (msr.hi >> (32 - 32)) & 0x07; /* Copy startup pstate to P1 and P0 MSRs. Set the maxvid for * this node in P0. Then transition to P1 for corex and P0 * for core0. These setting will be cleared by the warm reset */ - msr = rdmsr(0xC0010064 + startup_pstate); - wrmsr(0xC0010065, msr); - wrmsr(0xC0010064, msr); + msr = rdmsr(PSTATE_0_MSR + startup_pstate); + wrmsr(PSTATE_1_MSR, msr); + wrmsr(PSTATE_0_MSR, msr); /* missing step 2 from BDKG , F3xDC[PstateMaxVal] = * max(1,F3xDC[PstateMaxVal] ) because it would take @@ -773,7 +775,7 @@ static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid, u32 dev, u8 pviMode) msr.lo &= ~0xFE000000; // clear nbvid msr.lo |= (newNbVid << 25); - wrmsr(0xC0010064, msr); + wrmsr(PSTATE_0_MSR, msr); if (pviMode) { /* single plane*/ UpdateSinglePlaneNbVid(); @@ -944,14 +946,14 @@ static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll,u8 pviMode) /* write newNbVid to P-state Reg's NbVid if its NbDid=0 */ for (i = 0; i < 5; i++) { - msr = rdmsr(0xC0010064 + i); + msr = rdmsr(PSTATE_0_MSR + i); /* NbDid (bit 22 of P-state Reg) == 0 or NbVidUpdatedAll = 1 */ if ( (msr.hi & PS_IDD_VALUE_MASK) && (msr.hi & PS_EN_MASK) &&(((msr.lo & PS_NB_DID_MASK) == 0) || NbVidUpdatedAll)) { msr.lo &= PS_NB_VID_M_OFF; msr.lo |= (newNbVid & 0x7F) << PS_NB_VID_SHFT; - wrmsr(0xC0010064 + i, msr); + wrmsr(PSTATE_0_MSR + i, msr); } } @@ -962,7 +964,7 @@ static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll,u8 pviMode) UpdateSinglePlaneNbVid(); } /* For each core in the system, transition all cores to StartupPstate */ - msr = rdmsr(0xC0010071); + msr = rdmsr(MSR_COFVID_STS); StartupPstate = msr.hi & 0x07; /* Set and wait for StartupPstate to set. */ @@ -1027,9 +1029,9 @@ void init_fidvid_stage2(u32 apicid, u32 nodeid) if (!is_fam15h()) { /* Set TSC to tick at the P0 ndfid rate */ - msr = rdmsr(HWCR); + msr = rdmsr(HWCR_MSR); msr.lo |= 1 << 24; - wrmsr(HWCR, msr); + wrmsr(HWCR_MSR, msr); } } diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 51cf5104b4..1247e60283 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include "init_cpus.h" #if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE) @@ -39,7 +40,7 @@ #if IS_ENABLED(CONFIG_PCI_IO_CFG_EXT) static void set_EnableCf8ExtCfg(void) { - // set the NB_CFG[46]=1; + // set the NB_CFG_MSR[46]=1; msr_t msr; msr = rdmsr(NB_CFG_MSR); // EnableCf8ExtCfg: We need that to access CONFIG_PCI_IO_CFG_EXT 4K range @@ -332,9 +333,9 @@ static void STOP_CAR_AND_CPU(uint8_t skip_sharedc_config, uint32_t apicid) /* Family 10h or earlier */ /* Disable L2 IC to L3 connection (Only for CAR) */ - msr = rdmsr(BU_CFG2); + msr = rdmsr(BU_CFG2_MSR); msr.lo &= ~(1 << ClLinesToNbDis); - wrmsr(BU_CFG2, msr); + wrmsr(BU_CFG2_MSR, msr); } else { /* Family 15h or later * DRAM setup is delayed on Fam15 in order to prevent @@ -739,13 +740,13 @@ static void AMD_Errata298(void) } if (affectedRev) { - msr = rdmsr(HWCR); + msr = rdmsr(HWCR_MSR); msr.lo |= 0x08; /* Set TlbCacheDis bit[3] */ - wrmsr(HWCR, msr); + wrmsr(HWCR_MSR, msr); - msr = rdmsr(BU_CFG); + msr = rdmsr(BU_CFG_MSR); msr.lo |= 0x02; /* Set TlbForceMemTypeUc bit[1] */ - wrmsr(BU_CFG, msr); + wrmsr(BU_CFG_MSR, msr); msr = rdmsr(OSVW_ID_Length); msr.lo |= 0x01; /* OS Visible Workaround - MSR */ @@ -805,7 +806,7 @@ static void AMD_SetupPSIVID_d(u32 platform_type, u8 node) */ for (i = 4; i >= 0; i--) { - msr = rdmsr(PS_REG_BASE + i); + msr = rdmsr(PSTATE_0_MSR + i); /* Pstate valid? */ if (msr.hi & PS_EN_MASK) { dword = pci_read_config32(NODE_PCI(i, 3), 0xA0); @@ -1010,7 +1011,7 @@ void cpuSetAMDMSR(uint8_t node_id) enable_experimental_memory_speed_boost = !!nvram; uint32_t f3x1fc = pci_read_config32(NODE_PCI(node_id, 3), 0x1fc); - msr = rdmsr(FP_CFG); + msr = rdmsr(FP_CFG_MSR); msr.hi &= ~(0x7 << (42-32)); /* DiDtCfg4 */ msr.hi |= (((f3x1fc >> 17) & 0x7) << (42-32)); msr.hi &= ~(0x1 << (41-32)); /* DiDtCfg5 */ @@ -1027,19 +1028,19 @@ void cpuSetAMDMSR(uint8_t node_id) msr.lo |= (((f3x1fc >> 1) & 0x1f) << 18); msr.lo &= ~(0x1 << 16); /* DiDtMode */ msr.lo |= ((f3x1fc & 0x1) << 16); - wrmsr(FP_CFG, msr); + wrmsr(FP_CFG_MSR, msr); if (enable_experimental_memory_speed_boost) { - msr = rdmsr(BU_CFG3); + msr = rdmsr(BU_CFG3_MSR); msr.lo |= (0x3 << 20); /* PfcStrideMul = 0x3 */ - wrmsr(BU_CFG3, msr); + wrmsr(BU_CFG3_MSR, msr); } } #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB800) if (revision & (AMD_DR_GT_D0 | AMD_FAM15_ALL)) { /* Set up message triggered C1E */ - msr = rdmsr(0xc0010055); + msr = rdmsr(MSR_INTPEND); msr.lo &= ~0xffff; /* IOMsgAddr = ACPI_PM_EVT_BLK */ msr.lo |= ACPI_PM_EVT_BLK & 0xffff; msr.lo |= (0x1 << 29); /* BmStsClrOnHltEn = 1 */ @@ -1047,11 +1048,11 @@ void cpuSetAMDMSR(uint8_t node_id) msr.lo &= ~(0x1 << 28); /* C1eOnCmpHalt = 0 */ msr.lo &= ~(0x1 << 27); /* SmiOnCmpHalt = 0 */ } - wrmsr(0xc0010055, msr); + wrmsr(MSR_INTPEND, msr); - msr = rdmsr(0xc0010015); + msr = rdmsr(HWCR_MSR); msr.lo |= (0x1 << 12); /* HltXSpCycEn = 1 */ - wrmsr(0xc0010015, msr); + wrmsr(HWCR_MSR, msr); } if (revision & (AMD_DR_Ex | AMD_FAM15_ALL)) { @@ -1063,9 +1064,9 @@ void cpuSetAMDMSR(uint8_t node_id) if (enable_c_states) { /* Set up the C-state base address */ msr_t c_state_addr_msr; - c_state_addr_msr = rdmsr(0xc0010073); + c_state_addr_msr = rdmsr(MSR_CSTATE_ADDRESS); c_state_addr_msr.lo = ACPI_CPU_P_LVL2; /* CstateAddr = ACPI_CPU_P_LVL2 */ - wrmsr(0xc0010073, c_state_addr_msr); + wrmsr(MSR_CSTATE_ADDRESS, c_state_addr_msr); } } #else @@ -1079,9 +1080,9 @@ void cpuSetAMDMSR(uint8_t node_id) if (!enable_cpb) { /* Disable Core Performance Boost */ - msr = rdmsr(0xc0010015); + msr = rdmsr(HWCR_MSR); msr.lo |= (0x1 << 25); /* CpbDis = 1 */ - wrmsr(0xc0010015, msr); + wrmsr(HWCR_MSR, msr); } } @@ -1826,12 +1827,12 @@ static void cpuInitializeMCA(void) u8 i; if (cpuid_edx(1) & 0x4080) { /* MCE and MCA (edx[7] and edx[14]) */ - msr = rdmsr(MCG_CAP); + msr = rdmsr(IA32_MCG_CAP); if (msr.lo & MCG_CTL_P) { /* MCG_CTL_P bit is set? */ msr.lo &= 0xFF; msr.lo--; msr.lo <<= 2; /* multiply the count by 4 */ - reg = MC0_STA + msr.lo; + reg = IA32_MC0_STATUS + msr.lo; msr.lo = msr.hi = 0; for (i = 0; i < 4; i++) { wrmsr(reg, msr); diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c index 50406744bb..2374503287 100644 --- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c +++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c @@ -16,6 +16,8 @@ #include #include +#include +#include #include #include #include @@ -28,11 +30,7 @@ #include #include #include -#include #include -#include - -#define MC0_STATUS 0x401 static inline uint8_t is_gt_rev_d(void) { @@ -110,12 +108,12 @@ static void model_10xxx_init(struct device *dev) disable_cache(); /* zero the machine check error status registers */ - msr = rdmsr(MCG_CAP); + msr = rdmsr(IA32_MCG_CAP); num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; for (i = 0; i < num_banks; i++) - wrmsr(MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC0_STATUS + (i * 4), msr); enable_cache(); diff --git a/src/cpu/amd/family_10h-family_15h/monotonic_timer.c b/src/cpu/amd/family_10h-family_15h/monotonic_timer.c index 6bf046dedc..b1886eaca3 100644 --- a/src/cpu/amd/family_10h-family_15h/monotonic_timer.c +++ b/src/cpu/amd/family_10h-family_15h/monotonic_timer.c @@ -16,12 +16,11 @@ #include #include #include +#include #include #include #include - #include -#include static struct monotonic_counter { int initialized; @@ -62,7 +61,7 @@ static void init_timer(void) wrmsr(HWCR_MSR, msr); /* Get core Pstate 0 frequency in MHz */ - msr = rdmsr(0xC0010064 + boost_capable); + msr = rdmsr(PSTATE_0_MSR + boost_capable); cpufid = (msr.lo & 0x3f); cpudid = (msr.lo & 0x1c0) >> 6; mono_counter.core_frequency = (100 * (cpufid + 0x10)) / (0x01 << cpudid); diff --git a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c index 35f7952022..61da88cc49 100644 --- a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c +++ b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -111,7 +112,7 @@ static void write_cstates_for_core(int coreID) cstate.resource.space_id = ACPI_ADDRESS_SPACE_IO; cstate.resource.bit_width = 8; cstate.resource.bit_offset = 0; - cstate.resource.addrl = rdmsr(0xc0010073).lo + 1; + cstate.resource.addrl = rdmsr(MSR_CSTATE_ADDRESS).lo + 1; cstate.resource.addrh = 0; cstate.resource.resv = 1; } else { @@ -121,7 +122,7 @@ static void write_cstates_for_core(int coreID) cstate.resource.space_id = ACPI_ADDRESS_SPACE_IO; cstate.resource.bit_width = 8; cstate.resource.bit_offset = 0; - cstate.resource.addrl = rdmsr(0xc0010073).lo; + cstate.resource.addrl = rdmsr(MSR_CSTATE_ADDRESS).lo; cstate.resource.addrh = 0; cstate.resource.resv = 1; } @@ -268,7 +269,8 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP) if (fam15h) /* Set P_LVL2 P_BLK entry */ - *(((uint8_t *)pcontrol_blk) + 0x04) = (rdmsr(0xc0010073).lo + 1) & 0xff; + *(((uint8_t *)pcontrol_blk) + 0x04) = + (rdmsr(MSR_CSTATE_ADDRESS).lo + 1) & 0xff; uint8_t pviModeFlag; uint8_t Pstate_max; @@ -296,15 +298,15 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP) pviModeFlag = 0; /* Get PSmax's index */ - msr = rdmsr(0xC0010061); + msr = rdmsr(PS_LIM_REG); Pstate_max = (uint8_t) ((msr.lo >> PS_MAX_VAL_SHFT) & ((fam15h)?BIT_MASK_7:BIT_MASK_3)); /* Determine if all enabled Pstates have the same fidvid */ uint8_t i; - uint8_t cpufid_prev = (rdmsr(0xC0010064).lo & 0x3f); + uint8_t cpufid_prev = (rdmsr(PSTATE_0_MSR).lo & 0x3f); uint8_t all_enabled_cores_have_same_cpufid = 1; for (i = 1; i < Pstate_max; i++) { - cpufid = rdmsr(0xC0010064 + i).lo & 0x3f; + cpufid = rdmsr(PSTATE_0_MSR + i).lo & 0x3f; if (cpufid != cpufid_prev) { all_enabled_cores_have_same_cpufid = 0; break; @@ -318,7 +320,7 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP) /* Populate tables with all Pstate information */ for (Pstate_num = 0; Pstate_num < Pstate_max; Pstate_num++) { /* Get power state information */ - msr = rdmsr(0xC0010064 + Pstate_num + boost_count); + msr = rdmsr(PSTATE_0_MSR + Pstate_num + boost_count); cpufid = (msr.lo & 0x3f); cpudid = (msr.lo & 0x1c0) >> 6; cpuvid = (msr.lo & 0xfe00) >> 9; diff --git a/src/cpu/amd/family_10h-family_15h/tsc_freq.c b/src/cpu/amd/family_10h-family_15h/tsc_freq.c index 4aea1a02c9..63b4ac0e8a 100644 --- a/src/cpu/amd/family_10h-family_15h/tsc_freq.c +++ b/src/cpu/amd/family_10h-family_15h/tsc_freq.c @@ -15,6 +15,7 @@ #include #include +#include #include unsigned long tsc_freq_mhz(void) @@ -29,7 +30,7 @@ unsigned long tsc_freq_mhz(void) * to MHz. See also the Family 15h BKDG * Rev. 3.14 page 569. */ - msr = rdmsr(0xc0010064); + msr = rdmsr(PSTATE_0_MSR); cpufid = (msr.lo & 0x3f); cpudid = (msr.lo & 0x1c0) >> 6; diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c index 91450338aa..4feb1881cd 100644 --- a/src/cpu/amd/pi/00630F01/fixme.c +++ b/src/cpu/amd/pi/00630F01/fixme.c @@ -14,8 +14,8 @@ */ #include +#include #include - #include #include #include @@ -79,7 +79,7 @@ void amd_initmmio(void) */ MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); + LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader); /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c index 0269a1e260..503d5314ff 100644 --- a/src/cpu/amd/pi/00630F01/model_15_init.c +++ b/src/cpu/amd/pi/00630F01/model_15_init.c @@ -15,8 +15,10 @@ #include #include -#include +#include +#include #include +#include #include #include #include @@ -25,8 +27,6 @@ #include #include #include -#include -#include #include static void model_15_init(struct device *dev) @@ -70,12 +70,12 @@ static void model_15_init(struct device *dev) x86_enable_cache(); /* zero the machine check error status registers */ - msr = rdmsr(MCG_CAP); + msr = rdmsr(IA32_MCG_CAP); num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; for (i = 0; i < num_banks; i++) - wrmsr(MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC0_STATUS + (i * 4), msr); /* Enable the local CPU APICs */ setup_lapic(); @@ -105,14 +105,14 @@ static void model_15_init(struct device *dev) printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx); /* Set SMM base address for this CPU */ - msr = rdmsr(MSR_SMM_BASE); + msr = rdmsr(SMM_BASE_MSR); msr.lo = SMM_BASE - (cpu_idx * 0x400); - wrmsr(MSR_SMM_BASE, msr); + wrmsr(SMM_BASE_MSR, msr); /* Enable the SMM memory window */ - msr = rdmsr(MSR_SMM_MASK); + msr = rdmsr(SMM_MASK_MSR); msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */ - wrmsr(MSR_SMM_MASK, msr); + wrmsr(SMM_MASK_MSR, msr); } /* Write protect SMM space with SMMLOCK. */ diff --git a/src/cpu/amd/pi/00630F01/udelay.c b/src/cpu/amd/pi/00630F01/udelay.c index 5b08bedb1e..2cb53e9c20 100644 --- a/src/cpu/amd/pi/00630F01/udelay.c +++ b/src/cpu/amd/pi/00630F01/udelay.c @@ -21,6 +21,7 @@ */ #include +#include #include #include #include @@ -36,11 +37,11 @@ void udelay(uint32_t us) tsc_start = rdtscll(); /* Get the P-state. This determines which MSR to read */ - msr = rdmsr(0xc0010063); + msr = rdmsr(PS_STS_REG); pstate_idx = msr.lo & 0x07; /* Get FID and VID for current P-State */ - msr = rdmsr(0xc0010064 + pstate_idx); + msr = rdmsr(PSTATE_0_MSR + pstate_idx); /* Extract the FID and VID values */ fid = msr.lo & 0x3f; diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c index a4c574ced7..0bad4679ce 100644 --- a/src/cpu/amd/pi/00660F01/fixme.c +++ b/src/cpu/amd/pi/00660F01/fixme.c @@ -14,8 +14,8 @@ */ #include +#include #include - #include #include #include @@ -80,7 +80,7 @@ void amd_initmmio(void) */ MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); + LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader); /* For serial port */ PciData = 0xFF03FFD5; diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c index 424a6c06ff..3f3a1fda44 100644 --- a/src/cpu/amd/pi/00660F01/model_15_init.c +++ b/src/cpu/amd/pi/00660F01/model_15_init.c @@ -15,6 +15,8 @@ #include #include +#include +#include #include #include #include @@ -24,8 +26,6 @@ #include #include #include -#include -#include #include #include @@ -82,12 +82,12 @@ static void model_15_init(struct device *dev) x86_enable_cache(); /* zero the machine check error status registers */ - msr = rdmsr(MCG_CAP); + msr = rdmsr(IA32_MCG_CAP); num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; for (i = 0; i < num_banks; i++) - wrmsr(MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC0_STATUS + (i * 4), msr); /* Enable the local CPU APICs */ setup_lapic(); diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c index f6334a8a78..9f4c5289bb 100644 --- a/src/cpu/amd/pi/00730F01/fixme.c +++ b/src/cpu/amd/pi/00730F01/fixme.c @@ -14,8 +14,8 @@ */ #include +#include #include - #include #include #include @@ -80,7 +80,7 @@ void amd_initmmio(void) */ MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); + LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader); /* For serial port */ PciData = 0xFF03FFD5; diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index 1f2c30fd03..f5121d1a4f 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -15,6 +15,8 @@ #include #include +#include +#include #include #include #include @@ -24,8 +26,6 @@ #include #include #include -#include -#include #include static void model_16_init(struct device *dev) @@ -67,12 +67,12 @@ static void model_16_init(struct device *dev) x86_enable_cache(); /* zero the machine check error status registers */ - msr = rdmsr(MCG_CAP); + msr = rdmsr(IA32_MCG_CAP); num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; for (i = 0; i < num_banks; i++) - wrmsr(MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC0_STATUS + (i * 4), msr); /* Enable the local CPU APICs */ setup_lapic(); diff --git a/src/include/cpu/amd/amdfam12.h b/src/include/cpu/amd/amdfam12.h deleted file mode 100644 index 3838ce1b84..0000000000 --- a/src/include/cpu/amd/amdfam12.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef CPU_AMD_FAM12_H -#define CPU_AMD_FAM12_H - -#define HWCR_MSR 0xC0010015 -#define NB_CFG_MSR 0xC001001f -#define LS_CFG_MSR 0xC0011020 -#define IC_CFG_MSR 0xC0011021 -#define DC_CFG_MSR 0xC0011022 -#define BU_CFG_MSR 0xC0011023 -#define BU_CFG2_MSR 0xC001102A - -#define CPU_ID_FEATURES_MSR 0xC0011004 -#define CPU_ID_EXT_FEATURES_MSR 0xC0011005 - -#endif /* CPU_AMD_FAM12_H */ diff --git a/src/include/cpu/amd/amdfam14.h b/src/include/cpu/amd/amdfam14.h deleted file mode 100644 index ec5d34b9e9..0000000000 --- a/src/include/cpu/amd/amdfam14.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef CPU_AMD_FAM14_H -#define CPU_AMD_FAM14_H - -#define HWCR_MSR 0xC0010015 -#define NB_CFG_MSR 0xC001001f -#define LS_CFG_MSR 0xC0011020 -#define IC_CFG_MSR 0xC0011021 -#define DC_CFG_MSR 0xC0011022 -#define BU_CFG_MSR 0xC0011023 -#define BU_CFG2_MSR 0xC001102A - -#define CPU_ID_FEATURES_MSR 0xC0011004 -#define CPU_ID_EXT_FEATURES_MSR 0xC0011005 - -#endif /* CPU_AMD_FAM14_H */ diff --git a/src/include/cpu/amd/amdfam15.h b/src/include/cpu/amd/amdfam15.h index 271af8aef5..18feaffa45 100644 --- a/src/include/cpu/amd/amdfam15.h +++ b/src/include/cpu/amd/amdfam15.h @@ -19,9 +19,6 @@ #include #include -#define MCG_CAP 0x00000179 -# define MCA_BANKS_MASK 0xff -#define MC0_CTL 0x00000400 #define MC0_STATUS 0x00000401 # define MCA_STATUS_HI_VAL BIT(63 - 32) # define MCA_STATUS_HI_OVERFLOW BIT(62 - 32) @@ -189,30 +186,4 @@ static inline enum mca_err_code_types mca_err_type(msr_t reg) return MCA_ERRTYPE_UNKNOWN; } -#define MSR_SMM_BASE 0xC0010111 -#define MSR_TSEG_BASE 0xC0010112 -#define MSR_SMM_MASK 0xC0010113 -# define SMM_TSEG_VALID (1 << 1) -# define SMM_TSEG_WB (6 << 12) -#define HWCR_MSR 0xC0010015 -# define SMM_LOCK (1 << 0) -#define NB_CFG_MSR 0xC001001f - -#define MMIO_CONF_BASE 0xC0010058 -# define MMIO_BUS_RANGE_SHIFT 2 -# define MMIO_RANGE_EN (1 << 0) - -#define PSTATE_0_MSR 0xC0010064 - -#define LS_CFG_MSR 0xC0011020 -#define IC_CFG_MSR 0xC0011021 -#define DC_CFG_MSR 0xC0011022 -#define CU_CFG_MSR 0xC0011023 -#define CU_CFG2_MSR 0xC001102A - -#define CPU_ID_FEATURES_MSR 0xC0011004 -#define CPU_ID_EXT_FEATURES_MSR 0xC0011005 - -#define CORE_PERF_BOOST_CTRL 0x15C - #endif /* CPU_AMD_FAM15_H */ diff --git a/src/include/cpu/amd/amdfam16.h b/src/include/cpu/amd/amdfam16.h deleted file mode 100644 index 8b7503d906..0000000000 --- a/src/include/cpu/amd/amdfam16.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef CPU_AMD_FAM16_H -#define CPU_AMD_FAM16_H - -#define MCG_CAP 0x00000179 -# define MCA_BANKS_MASK 0xff -#define MC0_STATUS 0x00000401 -#define HWCR_MSR 0xC0010015 -#define NB_CFG_MSR 0xC001001f - -#define LS_CFG_MSR 0xC0011020 -#define IC_CFG_MSR 0xC0011021 -#define DC_CFG_MSR 0xC0011022 -#define CU_CFG_MSR 0xC0011023 -#define CU_CFG2_MSR 0xC001102A - -#define CPU_ID_FEATURES_MSR 0xC0011004 -#define CPU_ID_EXT_FEATURES_MSR 0xC0011005 - -#endif /* CPU_AMD_FAM16_H */ diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h index 614c576d03..46ec70d3c9 100644 --- a/src/include/cpu/amd/msr.h +++ b/src/include/cpu/amd/msr.h @@ -15,17 +15,65 @@ * GNU General Public License for more details. */ +/* This file applies to AMD64 products. + * The definitions come from the AMD64 Programmers Manual vol2 + * Revision 3.30 and/or the device's BKDG. + */ + #ifndef CPU_AMD_MSR_H #define CPU_AMD_MSR_H #include +#define CPUID_EXT_PM 0x80000007 +#define CPUID_MODEL 1 +#define MC4_MISC0 0x00000413 +#define MC4_MISC1 0xC0000408 +#define MC4_MISC2 0xC0000409 +#define FS_Base 0xC0000100 +#define HWCR_MSR 0xC0010015 +#define NB_CFG_MSR 0xC001001f +#define FidVidStatus 0xC0010042 +#define MC1_CTL_MASK 0xC0010045 +#define MC4_CTL_MASK 0xC0010048 +#define MSR_INTPEND 0xC0010055 +#define MMIO_CONF_BASE 0xC0010058 +#define MMIO_RANGE_EN (1 << 0) +#define MMIO_BUS_RANGE_SHIFT (1 << 1) + /* P-state Current Limit Register */ +#define PS_LIM_REG 0xC0010061 + /* P-state Maximum Value shift position */ +#define PS_MAX_VAL_SHFT 4 + /* P-state Control Register */ +#define PS_CTL_REG 0xC0010062 + /* P-state Control Register CMD Mask OFF */ +#define PS_CMD_MASK_OFF ~(7) + /* P-state Status Mask */ +#define PS_STS_MASK 7 + /* P-state Status Register */ +#define PS_STS_REG 0xC0010063 +#define PSTATE_0_MSR 0xC0010064 +#define PSTATE_1_MSR 0xC0010065 +#define PSTATE_2_MSR 0xC0010066 +#define PSTATE_3_MSR 0xC0010067 +#define PSTATE_4_MSR 0xC0010068 + +#define MSR_COFVID_STS 0xC0010071 +#define MSR_CSTATE_ADDRESS 0xC0010073 +#define OSVW_ID_Length 0xC0010140 +#define OSVW_Status 0xC0010141 + #define SMM_BASE_MSR 0xC0010111 #define SMM_ADDR_MSR 0xC0010112 #define SMM_MASK_MSR 0xC0010113 +#define SMM_LOCK (1 << 0) +#define SMM_TSEG_VALID (1 << 1) +#define SMM_TSEG_WB (6 << 12) -#define HWCR_MSR 0xC0010015 -#define NB_CFG_MSR 0xC001001f +#define CPU_ID_FEATURES_MSR 0xC0011004 +#define CPU_ID_EXT_FEATURES_MSR 0xC0011005 +#define CPU_ID_HYPER_EXT_FEATURES 0xC001100d +#define LOGICAL_CPUS_NUM_MSR 0xC001100d #define LS_CFG_MSR 0xC0011020 #define IC_CFG_MSR 0xC0011021 #define DC_CFG_MSR 0xC0011022 @@ -38,9 +86,6 @@ #define LS_CFG2_MSR 0xC001102D #define IBS_OP_DATA3_MSR 0xC0011037 -#define CPU_ID_FEATURES_MSR 0xC0011004 -#define CPU_ID_HYPER_EXT_FEATURES 0xC001100d -#define LOGICAL_CPUS_NUM_MSR 0xC001100d -#define CPU_ID_EXT_FEATURES_MSR 0xC0011005 +#define CORE_PERF_BOOST_CTRL 0x15c #endif /* CPU_AMD_MSR_H */ diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 62e56b7a28..032ce4ecb6 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -25,6 +25,8 @@ #define IA32_MPERF 0xe7 #define IA32_APERF 0xe8 #define IA32_MCG_CAP 0x179 +#define MCG_CTL_P (1 << 3) +#define MCA_BANKS_MASK 0xff #define IA32_PERF_STATUS 0x198 #define IA32_PERF_CTL 0x199 #define IA32_THERM_INTERRUPT 0x19b diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index e73a0e7cde..2a0a1d98a3 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include #include @@ -159,7 +160,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb800_early_setup(); #if IS_ENABLED(CONFIG_SET_FIDVID) - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); post_code(0x39); @@ -174,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 5ee1fd6ab8..f6bb70fe2c 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include @@ -151,7 +152,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb800_early_setup(); #if IS_ENABLED(CONFIG_SET_FIDVID) - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only @@ -169,7 +170,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 0e2db0402f..4a244eb376 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include #include @@ -156,7 +157,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_early_setup(); #if IS_ENABLED(CONFIG_SET_FIDVID) - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only @@ -174,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index ad3157fbf6..622784be51 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #include #include @@ -253,7 +254,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x38); #if IS_ENABLED(CONFIG_SET_FIDVID) - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only @@ -271,7 +272,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 89e72eb8f7..0e60fc5c75 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #include #include @@ -152,7 +153,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_early_setup(); #if IS_ENABLED(CONFIG_SET_FIDVID) - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only @@ -170,7 +171,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c index 1d616a6ae8..cda416981f 100644 --- a/src/mainboard/asus/kcma-d8/romstage.c +++ b/src/mainboard/asus/kcma-d8/romstage.c @@ -38,6 +38,7 @@ #include #include #include +#include #include #include #include @@ -475,7 +476,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } if (IS_ENABLED(CONFIG_SET_FIDVID)) { - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only need to be done once */ @@ -494,7 +495,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); } diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index 036f136f06..a6fd8b2291 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #include #include @@ -256,7 +257,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) wait_all_core0_started(); if (IS_ENABLED(CONFIG_SET_FIDVID)) { - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); post_code(0x39); @@ -270,7 +271,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); } diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 98bb1cab8e..cb4a1ec904 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include #include @@ -515,7 +516,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } if (IS_ENABLED(CONFIG_SET_FIDVID)) { - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only need to be done once */ @@ -534,7 +535,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); } diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 4e05f0f97b..4320525db4 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -38,6 +38,7 @@ #include #include #include +#include #include #include #include @@ -156,7 +157,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_early_setup(); #if IS_ENABLED(CONFIG_SET_FIDVID) - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only @@ -174,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index b4f6293635..44d8d51c00 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include #include @@ -157,7 +158,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_early_setup(); #if IS_ENABLED(CONFIG_SET_FIDVID) - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only @@ -175,7 +176,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index fb1a134ec9..56e15418c7 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include #include @@ -161,7 +162,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb800_early_setup(); #if IS_ENABLED(CONFIG_SET_FIDVID) - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); post_code(0x39); @@ -176,7 +177,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index d91776c4da..e9e865e28f 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include #include @@ -159,7 +160,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb800_early_setup(); #if IS_ENABLED(CONFIG_SET_FIDVID) - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); post_code(0x39); @@ -174,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 680d279077..7b30452349 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include @@ -152,7 +153,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_early_setup(); #if IS_ENABLED(CONFIG_SET_FIDVID) - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only @@ -170,7 +171,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 642f70bfd8..fef31f74b5 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include @@ -152,7 +153,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_early_setup(); #if IS_ENABLED(CONFIG_SET_FIDVID) - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only @@ -170,7 +171,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index 923cfbc9af..c09b170a2b 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include #include @@ -154,7 +155,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_early_setup(); #if IS_ENABLED(CONFIG_SET_FIDVID) - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only @@ -172,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index fc922f413e..6e65be23e9 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -43,6 +43,7 @@ #include #include #include +#include #include #include #include @@ -161,7 +162,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif #if IS_ENABLED(CONFIG_SET_FIDVID) - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only @@ -180,7 +181,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 5693cee564..b4612eed5e 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include #include @@ -154,7 +155,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_early_setup(); #if IS_ENABLED(CONFIG_SET_FIDVID) - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only @@ -172,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 10416964cf..28c3a5dea4 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include #include @@ -159,7 +160,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_early_setup(); #if IS_ENABLED(CONFIG_SET_FIDVID) - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only @@ -177,7 +178,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 7848e9e95c..8538d33a50 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include @@ -190,7 +191,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x38); #if IS_ENABLED(CONFIG_SET_FIDVID) - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only @@ -208,7 +209,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif init_timer(); /* Need to use TMICT to synchronize FID/VID. */ diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index d5506dfa42..3e58848e61 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include #include @@ -184,7 +185,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x38); #if IS_ENABLED(CONFIG_SET_FIDVID) - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); @@ -203,7 +204,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index f438400f37..6aa20bbc2a 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include #include @@ -236,7 +237,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x38); #if IS_ENABLED(CONFIG_SET_FIDVID) - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only @@ -254,7 +255,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index a3d3ceabb0..045adaeff9 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include #include @@ -168,7 +169,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_early_setup(); #if IS_ENABLED(CONFIG_SET_FIDVID) - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only @@ -186,7 +187,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 0b47f9d6f4..7c4fd5b4bc 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include @@ -185,7 +186,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x38); #if IS_ENABLED(CONFIG_SET_FIDVID) - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only @@ -203,7 +204,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index dbe88d59bc..1851118645 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -29,6 +29,7 @@ #include #include +#include #include #include "sb_cimx.h" @@ -306,7 +307,7 @@ static void read_resources(struct device *dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - mmconf_resource(dev, 0xc0010058); + mmconf_resource(dev, MMIO_CONF_BASE); printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index ea21c6952a..ae5b227bee 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -27,13 +27,11 @@ #include #include #include - #include +#include #include - #include #include - #include #define FX_DEVS 1 @@ -298,7 +296,7 @@ static void nb_read_resources(struct device *dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - mmconf_resource(dev, 0xc0010058); + mmconf_resource(dev, MMIO_CONF_BASE); } static void set_resource(struct device *dev, struct resource *resource, diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 76fd747c91..7248eb79a0 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -29,14 +29,12 @@ #include #include #include - #include +#include #include - #include #include #include - #include #include @@ -307,7 +305,7 @@ static void nb_read_resources(struct device *dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - mmconf_resource(dev, 0xc0010058); + mmconf_resource(dev, MMIO_CONF_BASE); } static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 6e0eabaa50..a42ee5cd51 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -27,15 +27,13 @@ #include #include #include - #include +#include #include - #include #include #include #include - #include #include @@ -306,7 +304,7 @@ static void read_resources(struct device *dev) * It is not honored by the coreboot resource allocator if it is in * the APIC_CLUSTER. */ - mmconf_resource(dev, 0xc0010058); + mmconf_resource(dev, MMIO_CONF_BASE); } static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index ff4f0a397a..4da5228666 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -28,7 +28,6 @@ #include #include #include - #include #include #include @@ -734,7 +733,7 @@ static void amdfam10_domain_read_resources(struct device *dev) pci_domain_read_resources(dev); /* We have MMCONF_SUPPORT, create the resource window. */ - mmconf_resource(dev, 0xc0010058); + mmconf_resource(dev, MMIO_CONF_BASE); /* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */ ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10); diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h index d4e6a29f42..7e6a63d857 100644 --- a/src/northbridge/amd/amdht/AsPsDefs.h +++ b/src/northbridge/amd/amdht/AsPsDefs.h @@ -21,19 +21,6 @@ #define APIC_BAR 0x1b /* APIC_BAR register */ #define APIC_BAR_BP 0x100 /* APIC_BAR BSP bit */ -#define PS_LIM_REG 0xC0010061 /* P-state Current Limit Register */ -#define PS_MAX_VAL_SHFT 4 /* P-state Maximum Value shift position */ - -#define PS_CTL_REG 0xC0010062 /* P-state Control Register */ -#define PS_CMD_MASK_OFF 0xfffffff8 /* P-state Control Register CMD Mask OFF */ - -#define PS_STS_REG 0xC0010063 /* P-state Status Register */ -#define PS_STS_MASK 0x7 /* P-state Status Mask */ - -#define PS_REG_BASE 0xC0010064 /* P-state Register base */ -#define PS_MAX_REG 0xC0010068 /* Maximum P-State Register */ -#define PS_MIN_REG 0xC0010064 /* Mimimum P-State Register */ - /* P-state register offset */ #define PS_REG0 0 /* offset for P0 */ #define PS_REG1 1 /* offset for P1 */ @@ -286,7 +273,6 @@ #define TSC_MSR 0x10 -#define CUR_PSTATE_MSR 0xc0010063 #define TSC_FREQ_SEL_SHIFT 24 #define TSC_FREQ_SEL_MASK (1 << TSC_FREQ_SEL_SHIFT) diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h index 977fd9c959..1a442082ff 100644 --- a/src/northbridge/amd/amdmct/amddefs.h +++ b/src/northbridge/amd/amdmct/amddefs.h @@ -120,42 +120,6 @@ #define HTPHY_DIRECT_MAP 0x20000000 #define HTPHY_DIRECT_OFFSET_MASK 0xE000FFFF - -/* - * Various AMD MSRs - */ -#define CPUID_EXT_PM 0x80000007 -#define CPUID_MODEL 1 -#define MCG_CAP 0x00000179 - #define MCG_CTL_P 8 - #define MCA_BANKS_MASK 0xff -#define MC0_CTL 0x00000400 -#define MC0_STA (MC0_CTL + 1) -#define MC4_MISC0 0x00000413 -#define MC4_MISC1 0xC0000408 -#define MC4_MISC2 0xC0000409 -#define FS_Base 0xC0000100 -#define SYSCFG 0xC0010010 -#define HWCR 0xC0010015 -#define NB_CFG 0xC001001F -#define FidVidStatus 0xC0010042 -#define MC1_CTL_MASK 0xC0010045 -#define MC4_CTL_MASK 0xC0010048 -#define OSVW_ID_Length 0xC0010140 -#define OSVW_Status 0xC0010141 -#define CPUIDFEATURES 0xC0011004 -#define LS_CFG 0xC0011020 -#define IC_CFG 0xC0011021 -#define DC_CFG 0xC0011022 -#define BU_CFG 0xC0011023 -#define FP_CFG 0xC0011028 -#define DE_CFG 0xC0011029 -#define BU_CFG2 0xC001102A -#define BU_CFG3 0xC001102B -#define EX_CFG 0xC001102C -#define LS_CFG2 0xC001102D -#define IBS_OP_DATA3 0xC0011037 - /* * Processor package types */ diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 4267e6d07c..2488dfc22b 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -33,9 +33,9 @@ * supported. */ -#include "mct_d.h" - #include +#include +#include "mct_d.h" static u8 ReconfigureDIMMspare_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); @@ -3686,7 +3686,7 @@ void mct_SetClToNB_D(struct MCTStatStruc *pMCTstat, // FIXME: Maybe check the CPUID? - not for now. // pDCTstat->LogicalCPUID; - msr = BU_CFG2; + msr = BU_CFG2_MSR; _RDMSR(msr, &lo, &hi); lo |= 1 << ClLinesToNbDis; _WRMSR(msr, lo, hi); @@ -3703,7 +3703,7 @@ void mct_ClrClToNB_D(struct MCTStatStruc *pMCTstat, // FIXME: Maybe check the CPUID? - not for now. // pDCTstat->LogicalCPUID; - msr = BU_CFG2; + msr = BU_CFG2_MSR; _RDMSR(msr, &lo, &hi); if (!pDCTstat->ClToNB_flag) lo &= ~(1 << ClLinesToNbDis); @@ -3721,7 +3721,7 @@ void mct_SetWbEnhWsbDis_D(struct MCTStatStruc *pMCTstat, // FIXME: Maybe check the CPUID? - not for now. // pDCTstat->LogicalCPUID; - msr = BU_CFG; + msr = BU_CFG_MSR; _RDMSR(msr, &lo, &hi); hi |= (1 << WbEnhWsbDis_D); _WRMSR(msr, lo, hi); @@ -3737,7 +3737,7 @@ void mct_ClrWbEnhWsbDis_D(struct MCTStatStruc *pMCTstat, // FIXME: Maybe check the CPUID? - not for now. // pDCTstat->LogicalCPUID; - msr = BU_CFG; + msr = BU_CFG_MSR; _RDMSR(msr, &lo, &hi); hi &= ~(1 << WbEnhWsbDis_D); _WRMSR(msr, lo, hi); @@ -3845,7 +3845,7 @@ static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat, return; } - addr = HWCR; + addr = HWCR_MSR; _RDMSR(addr, &lo, &hi); if (lo & (1<<17)) { /* save the old value */ wrap32dis = 1; @@ -3877,7 +3877,7 @@ static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat, } } if (!wrap32dis) { - addr = HWCR; + addr = HWCR_MSR; _RDMSR(addr, &lo, &hi); lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c index 9bb87bbb2a..39c11ce7da 100644 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c @@ -13,9 +13,10 @@ * GNU General Public License for more details. */ -#include "mct_d.h" #include +#include #include +#include "mct_d.h" static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u16 like, @@ -286,7 +287,7 @@ static void TrainDQSRdWrPos_D(struct MCTStatStruc *pMCTstat, cr4 |= (1<<9); /* OSFXSR enable SSE2 */ write_cr4(cr4); - addr = HWCR; + addr = HWCR_MSR; _RDMSR(addr, &lo, &hi); if (lo & (1<<17)) { _Wrap32Dis = 1; @@ -368,7 +369,7 @@ static void TrainDQSRdWrPos_D(struct MCTStatStruc *pMCTstat, mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC); } if (!_Wrap32Dis) { - addr = HWCR; + addr = HWCR_MSR; _RDMSR(addr, &lo, &hi); lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c index a29f8eb42e..4689c7b982 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc.c @@ -14,8 +14,9 @@ * GNU General Public License for more details. */ -#include "mct_d.h" #include +#include +#include "mct_d.h" /****************************************************************************** Description: Receiver En and DQS Timing Training feature for DDR 2 MCT @@ -170,7 +171,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, write_cr4(cr4); print_t("TrainRcvrEn: 2\n"); - msr = HWCR; + msr = HWCR_MSR; _RDMSR(msr, &lo, &hi); //FIXME: Why use SSEDIS if (lo & (1 << 17)) { /* save the old value */ @@ -443,7 +444,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, } if (!_Wrap32Dis) { - msr = HWCR; + msr = HWCR_MSR; _RDMSR(msr, &lo, &hi); lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(msr, lo, hi); diff --git a/src/northbridge/amd/amdmct/mct/mcttmrl.c b/src/northbridge/amd/amdmct/mct/mcttmrl.c index 4c6d8e6fee..192288a2c4 100644 --- a/src/northbridge/amd/amdmct/mct/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct/mcttmrl.c @@ -13,8 +13,9 @@ * GNU General Public License for more details. */ -#include "mct_d.h" #include +#include +#include "mct_d.h" /* * Description: Max Read Latency Training feature for DDR 2 MCT @@ -132,7 +133,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, cr4 |= (1<<9); /* OSFXSR enable SSE2 */ write_cr4(cr4); - addr = HWCR; + addr = HWCR_MSR; _RDMSR(addr, &lo, &hi); if (lo & (1<<17)) { /* save the old value */ _Wrap32Dis = 1; @@ -182,7 +183,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, } if (!_Wrap32Dis) { - addr = HWCR; + addr = HWCR_MSR; _RDMSR(addr, &lo, &hi); lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 7421c18a69..b94c68c931 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -32,18 +32,19 @@ * supported. */ -#include "mct_d_gcc.h" -#include "mct_d.h" #include #include #include #include #include #include +#include #include #include #include #include "s3utils.h" +#include "mct_d_gcc.h" +#include "mct_d.h" static u8 ReconfigureDIMMspare_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); @@ -7770,7 +7771,7 @@ void mct_SetClToNB_D(struct MCTStatStruc *pMCTstat, /* FIXME: Maybe check the CPUID? - not for now. */ /* pDCTstat->LogicalCPUID; */ - msr = BU_CFG2; + msr = BU_CFG2_MSR; _RDMSR(msr, &lo, &hi); lo |= 1 << ClLinesToNbDis; _WRMSR(msr, lo, hi); @@ -7786,7 +7787,7 @@ void mct_ClrClToNB_D(struct MCTStatStruc *pMCTstat, /* FIXME: Maybe check the CPUID? - not for now. */ /* pDCTstat->LogicalCPUID; */ - msr = BU_CFG2; + msr = BU_CFG2_MSR; _RDMSR(msr, &lo, &hi); if (!pDCTstat->ClToNB_flag) lo &= ~(1<LogicalCPUID; */ - msr = BU_CFG; + msr = BU_CFG_MSR; _RDMSR(msr, &lo, &hi); hi |= (1 << WbEnhWsbDis_D); _WRMSR(msr, lo, hi); @@ -7818,7 +7819,7 @@ void mct_ClrWbEnhWsbDis_D(struct MCTStatStruc *pMCTstat, /* FIXME: Maybe check the CPUID? - not for now. */ /* pDCTstat->LogicalCPUID; */ - msr = BU_CFG; + msr = BU_CFG_MSR; _RDMSR(msr, &lo, &hi); hi &= ~(1 << WbEnhWsbDis_D); _WRMSR(msr, lo, hi); @@ -8048,7 +8049,7 @@ static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat, return; } - addr = HWCR; + addr = HWCR_MSR; _RDMSR(addr, &lo, &hi); if (lo & (1<<17)) { /* save the old value */ wrap32dis = 1; @@ -8079,7 +8080,7 @@ static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat, } if (!wrap32dis) { - addr = HWCR; + addr = HWCR_MSR; _RDMSR(addr, &lo, &hi); lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 04299937d8..ce93472b9d 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -17,9 +17,10 @@ #include #include #include +#include +#include #include "mct_d.h" #include "mct_d_gcc.h" -#include static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u16 like, @@ -431,7 +432,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, cr4 |= (1<<9); /* OSFXSR enable SSE2 */ write_cr4(cr4); - addr = HWCR; + addr = HWCR_MSR; _RDMSR(addr, &lo, &hi); if (lo & (1<<17)) { _Wrap32Dis = 1; @@ -830,7 +831,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC); } if (!_Wrap32Dis) { - addr = HWCR; + addr = HWCR_MSR; _RDMSR(addr, &lo, &hi); lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); @@ -1648,7 +1649,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, cr4 |= (1<<9); /* OSFXSR enable SSE2 */ write_cr4(cr4); - addr = HWCR; + addr = HWCR_MSR; _RDMSR(addr, &lo, &hi); if (lo & (1<<17)) { _Wrap32Dis = 1; @@ -1861,7 +1862,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC); } if (!_Wrap32Dis) { - addr = HWCR; + addr = HWCR_MSR; _RDMSR(addr, &lo, &hi); lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index bae2e8998a..1db1b54307 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -22,9 +22,10 @@ #include #include #include +#include +#include #include "mct_d.h" #include "mct_d_gcc.h" -#include static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 Pass); @@ -661,14 +662,15 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, cr4 |= (1 << 9); /* OSFXSR enable SSE2 */ write_cr4(cr4); - msr = rdmsr(HWCR); + msr = rdmsr(HWCR_MSR); /* FIXME: Why use SSEDIS */ if (msr.lo & (1 << 17)) { /* save the old value */ _Wrap32Dis = 1; } msr.lo |= (1 << 17); /* HWCR.wrap32dis */ msr.lo &= ~(1 << 15); /* SSEDIS */ - wrmsr(HWCR, msr); /* Setting wrap32dis allows 64-bit memory references in real mode */ + wrmsr(HWCR_MSR, msr); /* Setting wrap32dis allows 64-bit memory + references in real mode */ _DisableDramECC = mct_DisableDimmEccEn_D(pMCTstat, pDCTstat); @@ -996,9 +998,9 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, } if (!_Wrap32Dis) { - msr = rdmsr(HWCR); + msr = rdmsr(HWCR_MSR); msr.lo &= ~(1<<17); /* restore HWCR.wrap32dis */ - wrmsr(HWCR, msr); + wrmsr(HWCR_MSR, msr); } if (!_SSE2) { cr4 = read_cr4(); @@ -1254,7 +1256,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, cr4 |= (1 << 9); /* OSFXSR enable SSE2 */ write_cr4(cr4); - msr = HWCR; + msr = HWCR_MSR; _RDMSR(msr, &lo, &hi); /* FIXME: Why use SSEDIS */ if (lo & (1 << 17)) { /* save the old value */ @@ -1498,7 +1500,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, } if (!_Wrap32Dis) { - msr = HWCR; + msr = HWCR_MSR; _RDMSR(msr, &lo, &hi); lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(msr, lo, hi); @@ -1613,7 +1615,7 @@ void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, cr4 |= (1 << 9); /* OSFXSR enable SSE2 */ write_cr4(cr4); - msr = HWCR; + msr = HWCR_MSR; _RDMSR(msr, &lo, &hi); /* FIXME: Why use SSEDIS */ if (lo & (1 << 17)) { /* save the old value */ @@ -1718,7 +1720,7 @@ void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, } if (!_Wrap32Dis) { - msr = HWCR; + msr = HWCR_MSR; _RDMSR(msr, &lo, &hi); lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(msr, lo, hi); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c index 039a747736..6c3db47542 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c @@ -21,6 +21,7 @@ #include #include #include +#include #include "mct_d.h" #include "mct_d_gcc.h" @@ -131,7 +132,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, cr4 |= (1<<9); /* OSFXSR enable SSE2 */ write_cr4(cr4); - addr = HWCR; + addr = HWCR_MSR; _RDMSR(addr, &lo, &hi); if (lo & (1<<17)) { /* save the old value */ _Wrap32Dis = 1; @@ -181,7 +182,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, } if (!_Wrap32Dis) { - addr = HWCR; + addr = HWCR_MSR; _RDMSR(addr, &lo, &hi); lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 8be2ac70fb..f6cb28565b 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -26,23 +26,23 @@ #include #include #include - #include #include #include #include +#include +#include +#include +#include +#include +#include #include #if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) #include #include #endif -#include "northbridge.h" -#include -#include -#include -#include -#include +#include "northbridge.h" #define MAX_NODE_NUMS MAX_NODES @@ -315,7 +315,7 @@ static void read_resources(struct device *dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - mmconf_resource(dev, 0xc0010058); + mmconf_resource(dev, MMIO_CONF_BASE); } static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index c073e7ad11..fb3610d1b9 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -26,11 +26,15 @@ #include #include #include - #include #include #include #include +#include +#include +#include +#include +#include #include #if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) #include @@ -38,11 +42,6 @@ #endif #include "northbridge.h" -#include -#include -#include -#include - #define MAX_NODE_NUMS MAX_NODES #if IS_ENABLED(CONFIG_EXT_CONF_SUPPORT) @@ -302,7 +301,7 @@ static void read_resources(struct device *dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - mmconf_resource(dev, 0xc0010058); + mmconf_resource(dev, MMIO_CONF_BASE); } static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index f4c39d6be1..7125e1e090 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -28,11 +28,15 @@ #include #include #include - #include #include #include #include +#include +#include +#include +#include +#include #include #if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) #include @@ -40,11 +44,6 @@ #endif #include "northbridge.h" -#include -#include -#include -#include - #define MAX_NODE_NUMS MAX_NODES typedef struct dram_base_mask { @@ -312,7 +311,7 @@ static void read_resources(struct device *dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - mmconf_resource(dev, 0xc0010058); + mmconf_resource(dev, MMIO_CONF_BASE); } static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index 479e0fc9f2..e9a5bd6116 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 92b2950ad3..c140fca7db 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -18,8 +18,8 @@ #include #include #include +#include #include -#include #include #include #include @@ -89,10 +89,10 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase, tseg_base.lo = relo_attrs.tseg_base; tseg_base.hi = 0; - wrmsr(MSR_TSEG_BASE, tseg_base); + wrmsr(SMM_ADDR_MSR, tseg_base); tseg_mask.lo = relo_attrs.tseg_mask; tseg_mask.hi = ((1 << (cpu_phys_address_size() - 32)) - 1); - wrmsr(MSR_SMM_MASK, tseg_mask); + wrmsr(SMM_MASK_MSR, tseg_mask); smm_state = (void *)(SMM_AMD64_SAVE_STATE_OFFSET + curr_smbase); smm_state->smbase = staggered_smbase; } diff --git a/src/soc/amd/stoneyridge/finalize.c b/src/soc/amd/stoneyridge/finalize.c index 21d203cdd2..45e659504b 100644 --- a/src/soc/amd/stoneyridge/finalize.c +++ b/src/soc/amd/stoneyridge/finalize.c @@ -15,7 +15,7 @@ #include #include -#include +#include #include #include #include @@ -30,9 +30,9 @@ static void per_core_finalize(void *unused) return; if (IS_ENABLED(CONFIG_SMM_TSEG)) { - mask = rdmsr(MSR_SMM_MASK); + mask = rdmsr(SMM_MASK_MSR); mask.lo |= SMM_TSEG_VALID; - wrmsr(MSR_SMM_MASK, mask); + wrmsr(SMM_MASK_MSR, mask); } hwcr.lo |= SMM_LOCK; diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index df2b9611bf..13e626e397 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -133,11 +133,11 @@ static void build_bert_mca_error(struct mca_bank *mci) if (!chk) goto failed; - ctx = cper_new_ia32x64_context_msr(status, x86_sec, MCG_CAP, 3); + ctx = cper_new_ia32x64_context_msr(status, x86_sec, IA32_MCG_CAP, 3); if (!ctx) goto failed; ctx = cper_new_ia32x64_context_msr(status, x86_sec, - MC0_CTL + (mci->bank * 4), 4); + IA32_MC0_CTL + (mci->bank * 4), 4); if (!ctx) goto failed; ctx = cper_new_ia32x64_context_msr(status, x86_sec, @@ -169,7 +169,7 @@ void check_mca(void) struct mca_bank mci; int num_banks; - cap = rdmsr(MCG_CAP); + cap = rdmsr(IA32_MCG_CAP); num_banks = cap.lo & MCA_BANKS_MASK; if (is_warm_reset()) { @@ -177,7 +177,7 @@ void check_mca(void) if (i == 3) /* Reserved in Family 15h */ continue; - mci.sts = rdmsr(MC0_STATUS + (i * 4)); + mci.sts = rdmsr(IA32_MC0_STATUS + (i * 4)); if (mci.sts.hi || mci.sts.lo) { int core = cpuid_ebx(1) >> 24; @@ -192,7 +192,7 @@ void check_mca(void) mci.misc = rdmsr(MC0_MISC + (i * 4)); printk(BIOS_WARNING, " MC%d_MISC = %08x_%08x\n", i, mci.misc.hi, mci.misc.lo); - mci.ctl = rdmsr(MC0_CTL + (i * 4)); + mci.ctl = rdmsr(IA32_MC0_CTL + (i * 4)); printk(BIOS_WARNING, " MC%d_CTL = %08x_%08x\n", i, mci.ctl.hi, mci.ctl.lo); mci.cmask = rdmsr(MC0_CTL_MASK + i); @@ -211,5 +211,5 @@ void check_mca(void) mci.sts.lo = 0; mci.sts.hi = 0; for (i = 0 ; i < num_banks ; i++) - wrmsr(MC0_STATUS + (i * 4), mci.sts); + wrmsr(IA32_MC0_STATUS + (i * 4), mci.sts); } diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 95c2a073cb..a2ae52c09e 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c index 72db8ec7e1..7439ab41a5 100644 --- a/src/soc/amd/stoneyridge/ramtop.c +++ b/src/soc/amd/stoneyridge/ramtop.c @@ -19,8 +19,8 @@ #include #include #include +#include #include -#include #include #include #include @@ -102,7 +102,7 @@ void smm_region_info(void **start, size_t *size) static void clear_tvalid(void) { msr_t hwcr = rdmsr(HWCR_MSR); - msr_t mask = rdmsr(MSR_SMM_MASK); + msr_t mask = rdmsr(SMM_MASK_MSR); int tvalid = !!(mask.lo & SMM_TSEG_VALID); if (hwcr.lo & SMM_LOCK) { @@ -114,7 +114,7 @@ static void clear_tvalid(void) } mask.lo &= ~SMM_TSEG_VALID; - wrmsr(MSR_SMM_MASK, mask); + wrmsr(SMM_MASK_MSR, mask); } int smm_subregion(int sub, void **start, size_t *size) diff --git a/src/soc/amd/stoneyridge/tsc_freq.c b/src/soc/amd/stoneyridge/tsc_freq.c index a8ed7c6a4c..89b0a7866e 100644 --- a/src/soc/amd/stoneyridge/tsc_freq.c +++ b/src/soc/amd/stoneyridge/tsc_freq.c @@ -17,8 +17,8 @@ #include #include +#include #include -#include #include #include #include diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c index ab75e5f57f..865b577279 100644 --- a/src/southbridge/amd/rs780/early_setup.c +++ b/src/southbridge/amd/rs780/early_setup.c @@ -18,6 +18,7 @@ #include #include #include +#include #include "rev.h" #include "rs780.h" @@ -317,10 +318,10 @@ static void k8_optimization(void) set_nbcfg_enable_bits(k8_f2, 0xA0, 3 << 2, 3 << 2); set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5); - msr = rdmsr(0xC001001F); + msr = rdmsr(NB_CFG_MSR); msr.lo &= ~(1 << 9); msr.hi &= ~(1 << 4); - wrmsr(0xC001001F, msr); + wrmsr(NB_CFG_MSR, msr); } #else #define k8_optimization() do {} while (0) diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c index 96adfb5bdd..543cb0efbf 100644 --- a/src/southbridge/amd/sr5650/early_setup.c +++ b/src/southbridge/amd/sr5650/early_setup.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include "sr5650.h" @@ -309,9 +310,9 @@ void fam10_optimization(void) return; printk(BIOS_INFO, "fam10_optimization()\n"); - msr = rdmsr(0xC001001F); + msr = rdmsr(NB_CFG_MSR); msr.hi |= 1 << 14; /* bit 46: EnableCf8ExtCfg */ - wrmsr(0xC001001F, msr); + wrmsr(NB_CFG_MSR, msr); cpu_f0 = PCI_DEV(0, 0x18, 0); cpu_f2 = PCI_DEV(0, 0x18, 2); diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index 1c2fe48407..1e85c48986 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -40,7 +41,7 @@ struct resource *sr5650_retrieve_cpu_mmio_resource() for (domain = all_devices; domain; domain = domain->next) { if (domain->bus->dev->path.type != DEVICE_PATH_DOMAIN) continue; - res = probe_resource(domain->bus->dev, 0xc0010058); + res = probe_resource(domain->bus->dev, MMIO_CONF_BASE); if (res) return res; } -- cgit v1.2.3