From 447a681d3fa4daf8f865ecb5643aaa0c2b05d966 Mon Sep 17 00:00:00 2001 From: Mathew King Date: Tue, 16 Mar 2021 13:04:26 -0600 Subject: mb/google/guybrush: Add eSPI GPIO back to init table GPIOs should be configured in ramstage even if they are configured in an earlier stage. BUG=b:180721208 TEST=builds Signed-off-by: Mathew King Change-Id: I9896db41dbe2812856357510bc4420482e73ab3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51547 Reviewed-by: Furquan Shaikh Reviewed-by: EricR Lai Tested-by: build bot (Jenkins) --- src/mainboard/google/guybrush/variants/baseboard/gpio.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index 9b8df52dfb..1cd8c23e0f 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -108,7 +108,14 @@ static const struct soc_amd_gpio base_gpio_table[] = { /* CLK_REQ0_L */ PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), /* GPIO_93 - GPIO_103: Not available */ - /* GPIO_104 - GPIO_108: eSPI configured in early stage */ + /* ESPI1_DATA0 */ + PAD_NF(GPIO_104, SPI2_DO_ESPI2_D0, PULL_NONE), + /* ESPI1_DATA1 */ + PAD_NF(GPIO_105, SPI2_DI_ESPI2_D1, PULL_NONE), + /* ESPI1_DATA2 */ + PAD_NF(GPIO_106, EMMC_SPI2_WP_L_ESPI2_D2, PULL_NONE), + /* ESPI1_DATA3 */ + PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE), /* RAM_ID_0 / DEV_BEEP_EN */ PAD_GPI(GPIO_109, PULL_NONE), /* GPIO_110 - GPIO_112: Not available */ -- cgit v1.2.3