From 4d5fd77cf82e95b74c80790389c3616de2b81411 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Fri, 13 Mar 2020 17:21:59 +0800 Subject: lib/spd_bin: Cleanup spd_get_banks Remove the switch case in spd_get_banks. The LPDDR4X adapt DDR4 attributes. Signed-off-by: Eric Lai Change-Id: Icfaefd1856d2350c6e5a91d233ccdb10d5259391 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39496 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/lib/spd_bin.c | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index f59e187037..4be0051844 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -76,22 +76,15 @@ static int spd_get_banks(const uint8_t spd[], int dram_type) static const int ddr3_banks[4] = { 8, 16, 32, 64 }; static const int ddr4_banks[10] = { 4, 8, -1, -1, 8, 16, -1, -1, 16, 32 }; int index = (spd[SPD_DENSITY_BANKS] >> 4) & 0xf; - switch (dram_type) { - /* DDR3 and LPDDR3_Intel have the same bank definition */ - case SPD_DRAM_DDR3: - case SPD_DRAM_LPDDR3_INTEL: - if (index >= ARRAY_SIZE(ddr3_banks)) - return -1; - return ddr3_banks[index]; - /* LPDDR3, LPDDR4 and DDR4 have the same bank definition */ - case SPD_DRAM_LPDDR3_JEDEC: - case SPD_DRAM_DDR4: - case SPD_DRAM_LPDDR4: + + if (use_ddr4_params(dram_type)) { if (index >= ARRAY_SIZE(ddr4_banks)) return -1; return ddr4_banks[index]; - default: - return -1; + } else { + if (index >= ARRAY_SIZE(ddr3_banks)) + return -1; + return ddr3_banks[index]; } } -- cgit v1.2.3