From 551bd92b2b33fb71e74eb8d22db3aea69280a9b7 Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Fri, 4 Dec 2020 02:24:31 +0530 Subject: soc/intel/jasperlake: Enables CSE Lite driver for JSL platform in the romstage This patch sets up cse_fw_sync() call in the romstage.The cse_fw_sync() must be called after DRAM initialization. BUG=b:174694480 Test=Verified on Drawlet Signed-off-by: Sridhar Siricilla Change-Id: I43030e77f6ede53c23e6c9e65d34db85c141e13a Reviewed-on: https://review.coreboot.org/c/coreboot/+/48280 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/intel/jasperlake/romstage/romstage.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/jasperlake/romstage/romstage.c b/src/soc/intel/jasperlake/romstage/romstage.c index 1fa6c2d180..6d34b438cf 100644 --- a/src/soc/intel/jasperlake/romstage/romstage.c +++ b/src/soc/intel/jasperlake/romstage/romstage.c @@ -135,6 +135,16 @@ void mainboard_romstage_entry(void) s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); pmc_set_disb(); - if (!s3wake) + if (!s3wake) { + + /* + * cse_fw_sync() must be called after DRAM initialization as + * HMRFPO_ENABLE HECI command (which is used by cse_fw_sync()) + * is expected to be executed after DRAM initialization. + */ + if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) + cse_fw_sync(); + save_dimm_info(); + } } -- cgit v1.2.3