From 5716b4c358121485e3b3511fe4b5fe37b83258f3 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Wed, 14 Nov 2018 13:27:05 +0100 Subject: siemens/mc_apl5: Add new mainboard variant mc_apl5 This mainboard is based on mc_apl1. In a first step, it contains a copy of mc_apl1 directory with minimum changes. Special adaptations for mc_apl5 mainboard will follow in separate commits. Change-Id: Icdbb116a822ffa7a3bfb7026a5d1164db56a0c46 Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/29635 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- src/mainboard/siemens/mc_apl1/Kconfig | 2 + src/mainboard/siemens/mc_apl1/Kconfig.name | 4 + .../siemens/mc_apl1/variants/mc_apl5/Kconfig | 12 ++ .../siemens/mc_apl1/variants/mc_apl5/Makefile.inc | 2 + .../siemens/mc_apl1/variants/mc_apl5/devicetree.cb | 119 ++++++++++++++ .../variants/mc_apl5/include/variant/ptn3460.h | 91 +++++++++++ .../siemens/mc_apl1/variants/mc_apl5/mainboard.c | 110 +++++++++++++ .../siemens/mc_apl1/variants/mc_apl5/ptn3460.c | 177 +++++++++++++++++++++ 8 files changed, 517 insertions(+) create mode 100644 src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig create mode 100644 src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc create mode 100644 src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb create mode 100644 src/mainboard/siemens/mc_apl1/variants/mc_apl5/include/variant/ptn3460.h create mode 100644 src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c create mode 100644 src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c diff --git a/src/mainboard/siemens/mc_apl1/Kconfig b/src/mainboard/siemens/mc_apl1/Kconfig index 19bd75a59c..7ec843ba03 100644 --- a/src/mainboard/siemens/mc_apl1/Kconfig +++ b/src/mainboard/siemens/mc_apl1/Kconfig @@ -20,6 +20,7 @@ config VARIANT_DIR default "mc_apl2" if BOARD_SIEMENS_MC_APL2 default "mc_apl3" if BOARD_SIEMENS_MC_APL3 default "mc_apl4" if BOARD_SIEMENS_MC_APL4 + default "mc_apl5" if BOARD_SIEMENS_MC_APL5 config DEVICETREE string @@ -31,6 +32,7 @@ config MAINBOARD_PART_NUMBER default "MC APL2" if BOARD_SIEMENS_MC_APL2 default "MC APL3" if BOARD_SIEMENS_MC_APL3 default "MC APL4" if BOARD_SIEMENS_MC_APL4 + default "MC APL5" if BOARD_SIEMENS_MC_APL5 config MAX_CPUS int diff --git a/src/mainboard/siemens/mc_apl1/Kconfig.name b/src/mainboard/siemens/mc_apl1/Kconfig.name index 592d8aafbe..3a5b6a343a 100644 --- a/src/mainboard/siemens/mc_apl1/Kconfig.name +++ b/src/mainboard/siemens/mc_apl1/Kconfig.name @@ -10,6 +10,10 @@ config BOARD_SIEMENS_MC_APL3 bool "-> MC APL3" select BOARD_SIEMENS_BASEBOARD_MC_APL1 +config BOARD_SIEMENS_MC_APL5 + bool "-> MC APL5" + select BOARD_SIEMENS_BASEBOARD_MC_APL1 + config BOARD_SIEMENS_MC_APL4 bool "-> MC APL4" select BOARD_SIEMENS_BASEBOARD_MC_APL1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig new file mode 100644 index 0000000000..196176c4fd --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig @@ -0,0 +1,12 @@ + +if BOARD_SIEMENS_MC_APL5 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select DRIVER_INTEL_I210 + select DRIVERS_I2C_RX6110SA + select DRIVER_SIEMENS_NC_FPGA + select NC_FPGA_NOTIFY_CB_READY + select APL_SKIP_SET_POWER_LIMITS + +endif # BOARD_SIEMENS_MC_APL5 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc new file mode 100644 index 0000000000..adf9aff0d4 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc @@ -0,0 +1,2 @@ +ramstage-y += mainboard.c +ramstage-y += ptn3460.c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb new file mode 100644 index 0000000000..f3e8a77143 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -0,0 +1,119 @@ +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + + register "sci_irq" = "SCIS_IRQ10" + + # Disable unused clkreq of PCIe root ports + register "pcie_rp_clkreq_pin[0]" = "3" # PCIe-PCI-Bridge + register "pcie_rp_clkreq_pin[1]" = "2" # FPGA + register "pcie_rp_clkreq_pin[2]" = "0" # MACPHY + register "pcie_rp_clkreq_pin[3]" = "1" # MACPHY + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0C16" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x28162828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181717" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10008" + + # 0:HS400(Default), 1:HS200, 2:DDR50 + register "emmc_host_max_speed" = "2" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Proximity Sensor | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_STANDARD + }, + }" + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 off end # - DPTF + device pci 00.2 off end # - NPK + device pci 02.0 on end # - Gen - Display + device pci 03.0 off end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 off end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 off end # - Shared SRAM + device pci 0e.0 off end # - Audio + device pci 11.0 on end # - ISH + device pci 12.0 on end # - SATA + device pci 13.0 on end # - RP 2 - PCIe A 0 - MACPHY + device pci 13.1 on end # - RP 3 - PCIe A 1 - MACPHY + device pci 13.2 off end # - RP 4 - PCIe-A 2 + device pci 13.3 off end # - RP 5 - PCIe-A 3 + device pci 14.0 on end # - RP 0 - PCIe-B 0 - PCIe-PCI-Bridge + device pci 14.1 on end # - RP 1 - PCIe-B 1 - FPGA + device pci 15.0 on end # - XHCI + device pci 15.1 off end # - XDCI + device pci 16.0 on # - I2C 0 + # Enable external RTC chip + chip drivers/i2c/rx6110sa + register "pmon_sampling" = "PMON_SAMPL_256_MS" + register "bks_on" = "0" + register "bks_off" = "1" + register "iocut_en" = "1" + register "set_user_date" = "1" + register "user_year" = "04" + register "user_month" = "07" + register "user_day" = "01" + register "user_weekday" = "4" + device i2c 0x32 on end # RTC RX6110 SA + end + end + device pci 16.1 off end # - I2C 1 + device pci 16.2 off end # - I2C 2 + device pci 16.3 off end # - I2C 3 + device pci 17.0 off end # - I2C 4 + device pci 17.1 off end # - I2C 5 + device pci 17.2 off end # - I2C 6 + device pci 17.3 on end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 + device pci 19.0 off end # - SPI 0 + device pci 19.1 off end # - SPI 1 + device pci 19.2 off end # - SPI 2 + device pci 1a.0 off end # - PWM + device pci 1b.0 off end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1d.0 off end # - UFS + device pci 1e.0 off end # - SDIO + device pci 1f.0 on end # - LPC + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/include/variant/ptn3460.h b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/include/variant/ptn3460.h new file mode 100644 index 0000000000..6ae3e2f75f --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/include/variant/ptn3460.h @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014-2017 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef PTN3460_H_ +#define PTN3460_H_ + +#include + +#define PTN_SLAVE_ADR 0x20 +#define PTN_I2C_CONTROLLER 0 + +#define PTN_EDID_OFF 0x00 +#define PTN_EDID_LEN 0x80 +#define PTN_CONFIG_OFF 0x80 +#define PTN_FLASH_CFG_OFF 0xE8 +#define PTN_FLASH_CFG_LEN 0x04 +#define PTN_MAX_EDID_NUM 6 + +/* Define some error codes that can be used. */ +#define PTN_NO_ERROR 0x00000000 +#define PTN_BUS_ERROR 0x10000000 +#define PTN_INVALID_EDID 0x20000000 + +struct ptn_3460_config { + /* DiplayPort interface control. */ + uint8_t dp_interface_ctrl; + /* LVDS interface control register 1. */ + uint8_t lvds_interface_ctrl1; + /* LVDS interface control register 2. */ + uint8_t lvds_interface_ctrl2; + /* LVDS interface control register 3. */ + uint8_t lvds_interface_ctrl3; + /* Select which EDID-block is emulated. */ + uint8_t edid_rom_emulation; + /* Select which EDID block to map to 0..0x7F. */ + uint8_t edid_rom_access_ctrl; + /* Smallest PWM frequency for back light. */ + uint8_t pwm_min[3]; + /* Biggest PWM frequency for back light. */ + uint8_t pwm_max[3]; + /* Fast link training control register. */ + uint8_t fast_link_ctrl; + /* Pin configuration control register 1. */ + uint8_t pin_cfg_ctrl1; + /* Pin configuration control register 2. */ + uint8_t pin_cfg_ctrl2; + /* Default PWM bit count in DPCD register. */ + uint8_t pwm_default; + /* Current PWM bit count in DPCD register. */ + uint16_t pwm_value; + /* Default PWM frequency in DPCD register. */ + uint8_t pwm_default_freq; + /* Panel T3 timing value. */ + uint8_t t3_timing; + /* Panel T12 timing value. */ + uint8_t t12_timing; + /* Back light control register. */ + uint8_t backlight_ctrl; + /* Panel T2 delay. */ + uint8_t t2_delay; + /* Panel T4 timing value. */ + uint8_t t4_timing; + /* Panel T5 delay. */ + uint8_t t5_delay; +} __packed; + +struct ptn_3460_flash { + /* Flash command (erase or erase and flash). */ + uint8_t cmd; + /* Magic number needed by the flash algorithm. */ + uint16_t magic; + /* Trigger for starting flash operation. */ + uint8_t trigger; +} __packed; + +int ptn3460_init(const char *hwi_block); +int ptn3460_write_edid(uint8_t edid_num, const uint8_t data[PTN_EDID_LEN]); +int ptn_select_edid(uint8_t edid_num); +#endif /* PTN3460_H_ */ diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c new file mode 100644 index 0000000000..6d22fd9826 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TX_DWORD3 0xa8c + +void variant_mainboard_final(void) +{ + int status; + struct device *dev = NULL; + + /* + * Set up the DP2LVDS converter. + * ptn3460_init() may only be executed after i2c bus init. + */ + status = ptn3460_init("hwinfo.hex"); + if (status) + printk(BIOS_ERR, "LCD: Set up PTN with status 0x%x\n", status); + else + printk(BIOS_INFO, "LCD: Set up PTN was successful.\n"); + + /* + * PIR6 register mapping for PCIe root ports + * INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA# + */ + pcr_write16(PID_ITSS, 0x314c, 0x0321); + + /* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */ + dev = dev_find_device(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2001, 0); + if (dev) + pci_write_config8(dev, 0xd8, 0x3e); + + /* Enable CLKRUN_EN for power gating LPC */ + lpc_enable_pci_clk_cntl(); + + /* + * Enable LPC PCE (Power Control Enable) by setting IOSF-SB port 0xD2 + * offset 0x341D bit3 and bit0. + * Enable LPC CCE (Clock Control Enable) by setting IOSF-SB port 0xD2 + * offset 0x341C bit [3:0]. + */ + pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN)); + + /* + * Correct the SATA transmit signal via the High Speed I/O Transmit + * Control Register 3. + * Bit [23:16] set the output voltage swing for TX line. + * The value 0x4a sets the swing level to 0.58 V. + */ + pcr_rmw32(PID_MODPHY, TX_DWORD3, (0x00 << 16), (0x4a << 16)); +} + +static void wait_for_legacy_dev(void *unused) +{ + uint32_t legacy_delay, us_since_boot; + struct stopwatch sw; + + /* Open main hwinfo block. */ + if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) + return; + + /* Get legacy delay parameter from hwinfo. */ + if (hwilib_get_field(LegacyDelay, (uint8_t *) &legacy_delay, + sizeof(legacy_delay)) != sizeof(legacy_delay)) + return; + + us_since_boot = get_us_since_boot(); + /* No need to wait if the time since boot is already long enough.*/ + if (us_since_boot > legacy_delay) + return; + stopwatch_init_msecs_expire(&sw, (legacy_delay - us_since_boot) / 1000); + printk(BIOS_NOTICE, "Wait remaining %d of %d us for legacy devices...", + legacy_delay - us_since_boot, legacy_delay); + stopwatch_wait_until_expired(&sw); + printk(BIOS_NOTICE, "done!\n"); +} + +static void finalize_boot(void *unused) +{ + /* Set coreboot ready LED. */ + gpio_output(CNV_RGI_DT, 1); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, wait_for_legacy_dev, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL); diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c new file mode 100644 index 0000000000..829af2a25b --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c @@ -0,0 +1,177 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014-2017 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +/** + * This function sets up the DP2LVDS-converter to be used with the appropriate + * lcd panel. + * + * @param *hwi_block Filename in CBFS of the block to use as HW-Info. + * @return 0 on success or HWI-Data/PTN error code. + */ +int ptn3460_init(const char *hwi_block) +{ + struct ptn_3460_config cfg; + int status; + uint8_t disp_con = 0, color_depth = 0; + uint8_t edid_data[PTN_EDID_LEN]; + int i; + + if (!hwi_block || hwilib_find_blocks(hwi_block) != CB_SUCCESS) { + printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", + hwi_block); + return 1; + } + /* Get all needed information from hwinfo block. */ + if (hwilib_get_field(Edid, edid_data, sizeof(edid_data)) != + sizeof(edid_data)) { + printk(BIOS_ERR, "LCD: No EDID data available in %s\n", + hwi_block); + return 1; + } + if ((hwilib_get_field(PF_DisplCon, &disp_con, sizeof(disp_con)) != + sizeof(disp_con))) { + printk(BIOS_ERR, "LCD: Missing panel features from %s\n", + hwi_block); + return 1; + } + if (hwilib_get_field(PF_Color_Depth, &color_depth, sizeof(color_depth)) + != sizeof(color_depth)) { + printk(BIOS_ERR, "LCD: Missing panel features from %s\n", + hwi_block); + return 1; + } + /* + * Here, all the desired information for setting up DP2LVDS converter + * is present. Inside the converter, table 6 will be used for the + * timings. + */ + status = ptn3460_write_edid(6, edid_data); + if (status) + return status; + /* Select this table to be emulated. */ + ptn_select_edid(6); + /* Read PTN configuration data. */ + status = i2c_read_bytes(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, + PTN_CONFIG_OFF, (uint8_t *)&cfg, + sizeof(cfg)); + if (status) + return (PTN_BUS_ERROR | status); + /* Set up configuration data according to the hwinfo block we get. */ + cfg.dp_interface_ctrl = 0; + cfg.lvds_interface_ctrl1 = 0x00; + if (disp_con == PF_DISPLCON_LVDS_DUAL) + /* Turn on dual LVDS lane and clock. */ + cfg.lvds_interface_ctrl1 |= 0x0b; + if (color_depth == PF_COLOR_DEPTH_6BIT) + /* Use 18 bits per pixel. */ + cfg.lvds_interface_ctrl1 |= 0x20; + + /* 1 % clock spreading, 300 mV LVDS swing. */ + cfg.lvds_interface_ctrl2 = 0x13; + /* No LVDS signal swap. */ + cfg.lvds_interface_ctrl3 = 0x00; + /* Delay T2 (VDD to LVDS active) by 16 ms. */ + cfg.t2_delay = 1; + /* 250 ms from LVDS to backlight active. */ + cfg.t3_timing = 10; + /* 1 second re-power delay. */ + cfg.t12_timing = 20; + /* 150 ms backlight off to LVDS inactive. */ + cfg.t4_timing = 3; + /* Delay T5 (LVDS to VDD inactive) by 16 ms. */ + cfg.t5_delay = 1; + /* Enable backlight control. */ + cfg.backlight_ctrl = 0; + + /* Write back configuration data to PTN3460. */ + for (i = 0; i < sizeof(struct ptn_3460_config); i++) { + status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, + PTN_CONFIG_OFF+i, + *(((uint8_t *)&cfg)+i)); + if (status) + return (PTN_BUS_ERROR | status); + } + + /* Read PTN configuration data. */ + status = i2c_read_bytes(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, + PTN_CONFIG_OFF, (uint8_t *)&cfg, sizeof(cfg)); + if (status) + return (PTN_BUS_ERROR | status); + + return PTN_NO_ERROR; +} + +/** + * This function writes one Extended Display Identification Data (EDID) + * structure to PTN3460. + * + * @param edid_num Number of EDID that must be written (0..6). + * @param *data Pointer to a buffer where data to write is stored in. + * @return 0 on success or error code. + */ +int ptn3460_write_edid(uint8_t edid_num, const uint8_t data[PTN_EDID_LEN]) +{ + int status; + int i; + + if (edid_num > PTN_MAX_EDID_NUM) + return PTN_INVALID_EDID; + + /* First enable access to the desired EDID table. */ + status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, + PTN_CONFIG_OFF + 5, edid_num); + if (status) + return (PTN_BUS_ERROR | status); + + /* Now we can simply write EDID-data to ptn3460. */ + for (i = 0; i < PTN_EDID_LEN; i++) { + status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, + PTN_EDID_OFF + i, data[i]); + if (status) + return (PTN_BUS_ERROR | status); + } + + return PTN_NO_ERROR; +} + +/** + * This function selects one of 7 EDID-tables inside PTN3460 which should be + * emulated on DisplayPort and turn emulation ON. + * + * @param edid_num Number of EDID to emulate (0..6). + * @return 0 on success or error code. + */ +int ptn_select_edid(uint8_t edid_num) +{ + int status; + uint8_t val; + + if (edid_num > PTN_MAX_EDID_NUM) + return PTN_INVALID_EDID; + /* Enable emulation of the desired EDID table. */ + val = (edid_num << 1) | 1; + status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, + PTN_CONFIG_OFF + 4, val); + if (status) + return (PTN_BUS_ERROR | status); + else + return PTN_NO_ERROR; +} -- cgit v1.2.3