From 5819eab5a660f915e0d18dd7d948d2af2a231aa0 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Thu, 7 May 2020 13:16:32 +0200 Subject: soc/intel/skylake: Add ability to set root port ASPM The default setting of the root port ASPM configuration can be overridden from the device tree by using a non zero value. BUG=N/A TEST=tested on facebook monolith Change-Id: I85c545d5eacb10f43b94228f1caf1163028645e0 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/41171 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/soc/intel/skylake/chip.c | 5 ++++- src/soc/intel/skylake/chip.h | 10 ++++++++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 4ad691cb2e..ce566cf7b5 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -182,8 +182,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) sizeof(params->PcieRpLtrEnable)); memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, sizeof(params->PcieRpHotPlug)); - for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) + for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i]; + if (config->PcieRpAspm[i]) + params->PcieRpAspm[i] = config->PcieRpAspm[i] - 1; + } /* * PcieRpClkSrcNumber UPD is set to clock source number(0-6) for diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index e279d335bd..eb6cf9d7bc 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -289,6 +289,16 @@ struct soc_intel_skylake_config { RpMaxPayload_256, } PcieRpMaxPayload[CONFIG_MAX_ROOT_PORTS]; + /* PCIE RP ASPM, ASPM support for the root port */ + enum { + AspmDefault, + AspmDisabled, + AspmL0s, + AspmL1, + AspmL0sL1, + AspmAutoConfig, + } PcieRpAspm[CONFIG_MAX_ROOT_PORTS]; + /* USB related */ struct usb2_port_config usb2_ports[16]; struct usb3_port_config usb3_ports[10]; -- cgit v1.2.3