From 61e4e1ab6fffb05f9f18eeeaa1cf3959492e8a13 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Tue, 30 Jan 2018 09:51:38 -0800 Subject: soc/intel/skylake: Fix common timer frequency The calculation to set up the PM timer emulation is using an incorrect common timer clock value that was copied from Apollolake. According to the PDG Skylake and Kabylake clocks are derived from a 24MHz XTAL, not 19.2MHz like Apollolake. Fixing this value results in the proper "correction value" to be programmed into the PM timer emulation MSR that matches the raw value that would be programmed by FSP. (if it were doing MpInit) Old PM timer correction value: 0x2fba2e25 New PM timer correction value: 0x262e8b51 Change-Id: Ib2bb3cb1938ae34cfa7aef177bef6fc24da73335 Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/23509 Reviewed-by: Aaron Durbin Reviewed-by: Subrata Banik Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/include/soc/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h index 8073fcdded..cc76b19cd5 100644 --- a/src/soc/intel/skylake/include/soc/cpu.h +++ b/src/soc/intel/skylake/include/soc/cpu.h @@ -40,8 +40,8 @@ #define C9_POWER 0xc8 #define C10_POWER 0xc8 -/* Common Timer Copy (CTC) frequency - 19.2MHz. */ -#define CTC_FREQ 19200000 +/* Common Timer Copy (CTC) frequency - 24MHz. */ +#define CTC_FREQ 24000000 #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ (((1 << ((base)*5)) * (limit)) / 1000) -- cgit v1.2.3