From 6220eec18816f816cae28c07c6afcaf1673d83c6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 29 Nov 2016 16:26:14 +0200 Subject: intel/fsp_rangeley: Switch to MMCONF_SUPPORT_DEFAULT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Boards with this chipset do not have any reference of MMCONF_BASE_ADDRESS being written to chipset registers. Either board support is already broken or FSP takes care of this early and Kconfig lacks the notice that this parameter must match with the chosen FSP binary. CPU bootblock associated with this chipset uses exclusive PCI IO access already. Untested. Change-Id: I07d20d81266ff6aaa6384d20a806d52fd4568e08 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/17547 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/northbridge/intel/fsp_rangeley/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/fsp_rangeley/Kconfig b/src/northbridge/intel/fsp_rangeley/Kconfig index 6a9dbe944c..506a913729 100644 --- a/src/northbridge/intel/fsp_rangeley/Kconfig +++ b/src/northbridge/intel/fsp_rangeley/Kconfig @@ -17,7 +17,7 @@ config NORTHBRIDGE_INTEL_FSP_RANGELEY bool select CPU_INTEL_FSP_MODEL_406DX - select MMCONF_SUPPORT + select MMCONF_SUPPORT_DEFAULT if NORTHBRIDGE_INTEL_FSP_RANGELEY -- cgit v1.2.3