From 62682e79a72bbc25c5c3ef937b347c8ae32a136c Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 12 May 2021 01:17:35 +0200 Subject: soc/amd/cezanne/chip.h: add DPTC and tablet mode options Signed-off-by: Felix Held Change-Id: I39218b79a79f1ccaf1a58408c6bb5161acea64aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/54073 Reviewed-by: Jason Glenesk Reviewed-by: Martin Roth Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/soc/amd/cezanne/chip.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index 244f2ba303..e770670e05 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -75,6 +75,14 @@ struct soc_amd_cezanne_config { uint32_t telemetry_vddcrsocfull_scale_current_mA; uint32_t telemetry_vddcrsocoffset; + /* Enable dptc for tablet mode (0 = disable, 1 = enable) */ + uint8_t dptc_enable; + + /* STAPM Configuration for tablet mode (need enable dptc_enable first) */ + uint32_t fast_ppt_limit_tablet_mode_mW; + uint32_t slow_ppt_limit_tablet_mode_mW; + uint32_t sustained_power_limit_tablet_mode_mW; + uint32_t thermctl_limit_tablet_mode_degreeC; }; #endif /* CEZANNE_CHIP_H */ -- cgit v1.2.3