From 6403167d290da235a732bd2d6157aa2124fb403a Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Sat, 21 Apr 2018 14:45:32 -0600 Subject: compiler.h: add __weak macro Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Justin TerAvest --- src/arch/arm/stages.c | 3 ++- src/arch/arm64/arm_tf.c | 3 ++- src/arch/arm64/boot.c | 3 ++- src/arch/arm64/transition.c | 3 ++- src/arch/x86/acpi.c | 5 +++-- src/arch/x86/acpi_s3.c | 3 ++- src/arch/x86/acpigen.c | 9 +++++---- src/arch/x86/cbmem.c | 7 ++++--- src/arch/x86/mpspec.c | 3 ++- src/arch/x86/pirq_routing.c | 3 ++- src/arch/x86/postcar.c | 3 ++- src/arch/x86/smbios.c | 23 +++++++++++----------- src/arch/x86/timestamp.c | 3 ++- src/commonlib/storage/sdhci.c | 13 ++++++------ src/console/die.c | 3 ++- src/console/post.c | 3 ++- src/cpu/intel/microcode/microcode.c | 3 ++- src/cpu/x86/smm/smihandler.c | 15 +++++++------- src/cpu/x86/smm/smm_module_handler.c | 15 +++++++------- src/device/pci_rom.c | 3 ++- src/drivers/amd/agesa/romstage.c | 3 ++- src/drivers/amd/agesa/state_machine.c | 15 +++++++------- src/drivers/elog/gsmi.c | 5 +++-- src/drivers/i2c/tpm/cr50.c | 3 ++- src/drivers/intel/fsp1_1/car.c | 9 +++++---- src/drivers/intel/fsp1_1/raminit.c | 7 ++++--- src/drivers/intel/fsp1_1/ramstage.c | 9 +++++---- src/drivers/intel/fsp1_1/romstage.c | 23 +++++++++++----------- src/drivers/intel/fsp2_0/graphics.c | 2 +- src/drivers/intel/fsp2_0/hob_display.c | 6 +++--- src/drivers/intel/fsp2_0/memory_init.c | 4 ++-- src/drivers/intel/fsp2_0/notify.c | 3 ++- src/drivers/intel/fsp2_0/upd_display.c | 5 +++-- src/drivers/intel/wifi/wifi.c | 2 +- src/drivers/spi/spi-generic.c | 3 ++- src/drivers/spi/tpm/tpm.c | 3 ++- src/ec/google/chromeec/crosec_proto.c | 3 ++- src/include/compiler.h | 1 + src/lib/boot_device.c | 3 ++- src/lib/bootblock.c | 9 +++++---- src/lib/cbfs.c | 3 ++- src/lib/cbmem_common.c | 3 ++- src/lib/coreboot_table.c | 11 ++++++----- src/lib/fallback_boot.c | 3 ++- src/lib/gpio.c | 5 +++-- src/lib/hardwaremain.c | 3 ++- src/lib/imd_cbmem.c | 3 ++- src/lib/prog_loaders.c | 7 ++++--- src/lib/prog_ops.c | 7 ++++--- src/lib/reset.c | 7 ++++--- src/lib/timer.c | 3 ++- src/lib/timestamp.c | 4 ++-- src/lib/wrdd.c | 3 ++- src/mainboard/google/cyan/romstage.c | 3 ++- src/mainboard/google/cyan/spd/spd.c | 3 ++- src/mainboard/google/kahlee/mainboard.c | 3 ++- src/mainboard/google/kahlee/romstage.c | 3 ++- .../kahlee/variants/baseboard/OemCustomize.c | 3 ++- .../google/kahlee/variants/baseboard/gpio.c | 11 ++++++----- .../google/kahlee/variants/baseboard/memory.c | 5 +++-- .../google/octopus/variants/baseboard/boardid.c | 3 ++- .../google/octopus/variants/baseboard/gpio.c | 9 +++++---- .../google/octopus/variants/baseboard/memory.c | 5 +++-- .../google/octopus/variants/baseboard/nhlt.c | 3 ++- src/mainboard/google/poppy/ramstage.c | 3 ++- .../google/poppy/variants/baseboard/gpio.c | 9 +++++---- .../google/poppy/variants/baseboard/memory.c | 5 +++-- .../google/poppy/variants/baseboard/nhlt.c | 5 +++-- src/mainboard/google/reef/mainboard.c | 9 +++++---- .../google/reef/variants/baseboard/gpio.c | 9 +++++---- .../google/reef/variants/baseboard/memory.c | 5 +++-- .../google/reef/variants/baseboard/nhlt.c | 3 ++- src/mainboard/google/zoombini/memory.c | 5 +++-- .../google/zoombini/variants/baseboard/boardid.c | 3 ++- .../google/zoombini/variants/baseboard/gpio.c | 7 ++++--- .../google/zoombini/variants/baseboard/nhlt.c | 3 ++- .../intel/cannonlake_rvp/variants/baseboard/gpio.c | 7 ++++--- .../intel/cannonlake_rvp/variants/baseboard/nhlt.c | 3 ++- src/mainboard/intel/galileo/vboot.c | 3 ++- src/mainboard/intel/glkrvp/chromeos.c | 3 ++- .../intel/glkrvp/variants/baseboard/boardid.c | 3 ++- .../intel/glkrvp/variants/baseboard/gpio.c | 9 +++++---- .../intel/glkrvp/variants/baseboard/memory.c | 5 +++-- .../intel/glkrvp/variants/baseboard/nhlt.c | 3 ++- src/mainboard/siemens/mc_apl1/gpio.c | 5 +++-- src/northbridge/amd/pi/agesawrapper.c | 3 ++- src/security/vboot/bootmode.c | 11 ++++++----- src/security/vboot/vboot_common.c | 3 ++- src/security/vboot/vboot_logic.c | 7 ++++--- src/security/vboot/verstage.c | 3 ++- src/soc/amd/common/block/pi/agesawrapper.c | 5 +++-- src/soc/amd/common/block/pi/def_callouts.c | 3 ++- src/soc/amd/stoneyridge/BiosCallOuts.c | 5 +++-- src/soc/amd/stoneyridge/romstage.c | 3 ++- src/soc/amd/stoneyridge/usb.c | 5 +++-- src/soc/intel/apollolake/chip.c | 3 ++- src/soc/intel/apollolake/romstage.c | 5 +++-- src/soc/intel/baytrail/gpio.c | 3 ++- src/soc/intel/baytrail/southcluster.c | 3 ++- src/soc/intel/braswell/acpi.c | 3 ++- src/soc/intel/braswell/chip.c | 3 ++- src/soc/intel/braswell/gpio.c | 4 ++-- src/soc/intel/braswell/southcluster.c | 3 ++- src/soc/intel/broadwell/romstage/romstage.c | 3 ++- src/soc/intel/cannonlake/chip.c | 3 ++- src/soc/intel/cannonlake/romstage/romstage.c | 3 ++- src/soc/intel/common/acpi_wake_source.c | 3 ++- src/soc/intel/common/block/acpi/acpi.c | 9 +++++---- src/soc/intel/common/block/cpu/mp_init.c | 5 +++-- src/soc/intel/common/block/ebda/ebda.c | 3 ++- src/soc/intel/common/block/graphics/graphics.c | 3 ++- src/soc/intel/common/block/gspi/gspi.c | 3 ++- src/soc/intel/common/block/lpc/lpc.c | 5 +++-- src/soc/intel/common/block/pmc/pmc.c | 5 +++-- src/soc/intel/common/block/pmc/pmclib.c | 9 +++++---- src/soc/intel/common/block/rtc/rtc.c | 3 ++- src/soc/intel/common/block/smm/smihandler.c | 13 ++++++------ src/soc/intel/common/block/sram/sram.c | 3 ++- .../intel/common/block/systemagent/systemagent.c | 9 +++++---- src/soc/intel/common/block/uart/uart.c | 7 ++++--- src/soc/intel/common/block/xdci/xdci.c | 3 ++- src/soc/intel/common/block/xhci/xhci.c | 3 ++- src/soc/intel/common/vbt.c | 3 ++- src/soc/intel/denverton_ns/acpi.c | 3 ++- src/soc/intel/denverton_ns/fiamux.c | 3 ++- src/soc/intel/denverton_ns/romstage.c | 5 +++-- src/soc/intel/fsp_baytrail/gpio.c | 3 ++- src/soc/intel/quark/gpio_i2c.c | 3 ++- src/soc/intel/skylake/acpi.c | 3 ++- src/soc/intel/skylake/chip_fsp20.c | 3 ++- src/soc/intel/skylake/romstage/romstage_fsp20.c | 3 ++- src/soc/nvidia/tegra210/bootblock.c | 3 ++- src/soc/nvidia/tegra210/funitcfg.c | 3 ++- src/soc/nvidia/tegra210/romstage.c | 3 ++- src/southbridge/amd/sb700/sata.c | 5 +++-- src/southbridge/intel/common/smihandler.c | 5 +++-- src/southbridge/via/vt8237r/ide.c | 3 ++- 137 files changed, 408 insertions(+), 277 deletions(-) diff --git a/src/arch/arm/stages.c b/src/arch/arm/stages.c index 2beaacd1f8..1fae88637a 100644 --- a/src/arch/arm/stages.c +++ b/src/arch/arm/stages.c @@ -26,11 +26,12 @@ #include #include +#include /** * generic stage entry point. override this if board specific code is needed. */ -__attribute__((weak)) void stage_entry(void) +__weak void stage_entry(void) { main(); } diff --git a/src/arch/arm64/arm_tf.c b/src/arch/arm64/arm_tf.c index 69e83c10fe..a172d42ab3 100644 --- a/src/arch/arm64/arm_tf.c +++ b/src/arch/arm64/arm_tf.c @@ -21,6 +21,7 @@ #include #include #include +#include #include /* @@ -36,7 +37,7 @@ static entry_point_info_t bl32_ep_info; static entry_point_info_t bl33_ep_info; static bl31_params_t bl31_params; -void __attribute__((weak)) *soc_get_bl31_plat_params(bl31_params_t *params) +void __weak *soc_get_bl31_plat_params(bl31_params_t *params) { /* Default weak implementation. */ return NULL; diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c index d498cd9362..3804515392 100644 --- a/src/arch/arm64/boot.c +++ b/src/arch/arm64/boot.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -78,7 +79,7 @@ int arch_supports_bounce_buffer(void) } /* Generic stage entry point. Can be overridden by board/SoC if needed. */ -__attribute__((weak)) void stage_entry(void) +__weak void stage_entry(void) { main(); } diff --git a/src/arch/arm64/transition.c b/src/arch/arm64/transition.c index 9edc011420..8c5beb0b4f 100644 --- a/src/arch/arm64/transition.c +++ b/src/arch/arm64/transition.c @@ -17,6 +17,7 @@ #include #include #include +#include #include /* Litte-endian, No XN-forced, Instr cache disabled, @@ -27,7 +28,7 @@ SCTLR_CACHE_DISABLE | SCTLR_SAE_DISABLE | SCTLR_RES1 | \ SCTLR_ICE_DISABLE | SCTLR_WXN_DISABLE | SCTLR_LITTLE_END) -void __attribute__((weak)) exc_dispatch(struct exc_state *exc_state, uint64_t id) +void __weak exc_dispatch(struct exc_state *exc_state, uint64_t id) { /* Default weak implementation does nothing. */ } diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 601b6f0aa4..3b4896b118 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -44,6 +44,7 @@ #include #include #include +#include #include #include #include @@ -971,7 +972,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) } #endif -unsigned long __attribute__((weak)) fw_cfg_acpi_tables(unsigned long start) +unsigned long __weak fw_cfg_acpi_tables(unsigned long start) { return 0; } @@ -1238,7 +1239,7 @@ void acpi_save_gnvs(u32 gnvs_address) *gnvs = gnvs_address; } -__attribute__((weak)) int acpi_get_gpe(int gpe) +__weak int acpi_get_gpe(int gpe) { return -1; /* implemented by SOC */ } diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index bb8c3c5a8a..f6ed1089cf 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -218,7 +219,7 @@ static void acpi_jump_to_wakeup(void *vector) acpi_do_wakeup((uintptr_t)vector, source, target, size); } -void __attribute__((weak)) mainboard_suspend_resume(void) +void __weak mainboard_suspend_resume(void) { } diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index fc6cc66f8f..10a4e1ee8f 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -1504,28 +1505,28 @@ void acpigen_write_rom(void *bios, const size_t length) /* Soc-implemented functions -- weak definitions. */ -int __attribute__((weak)) acpigen_soc_read_rx_gpio(unsigned int gpio_num) +int __weak acpigen_soc_read_rx_gpio(unsigned int gpio_num) { printk(BIOS_ERR, "ERROR: %s not implemented\n", __func__); acpigen_write_debug_string("read_rx_gpio not available"); return -1; } -int __attribute__((weak)) acpigen_soc_get_tx_gpio(unsigned int gpio_num) +int __weak acpigen_soc_get_tx_gpio(unsigned int gpio_num) { printk(BIOS_ERR, "ERROR: %s not implemented\n", __func__); acpigen_write_debug_string("get_tx_gpio not available"); return -1; } -int __attribute__((weak)) acpigen_soc_set_tx_gpio(unsigned int gpio_num) +int __weak acpigen_soc_set_tx_gpio(unsigned int gpio_num) { printk(BIOS_ERR, "ERROR: %s not implemented\n", __func__); acpigen_write_debug_string("set_tx_gpio not available"); return -1; } -int __attribute__((weak)) acpigen_soc_clear_tx_gpio(unsigned int gpio_num) +int __weak acpigen_soc_clear_tx_gpio(unsigned int gpio_num) { printk(BIOS_ERR, "ERROR: %s not implemented\n", __func__); acpigen_write_debug_string("clear_tx_gpio not available"); diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c index 6a353bd324..ef53553777 100644 --- a/src/arch/x86/cbmem.c +++ b/src/arch/x86/cbmem.c @@ -14,17 +14,18 @@ #include #include #include +#include #include #if IS_ENABLED(CONFIG_LATE_CBMEM_INIT) -void __attribute__((weak)) backup_top_of_low_cacheable(uintptr_t ramtop) +void __weak backup_top_of_low_cacheable(uintptr_t ramtop) { /* Do nothing. Chipset may have implementation to save ramtop in NVRAM. */ } -uintptr_t __attribute__((weak)) restore_top_of_low_cacheable(void) +uintptr_t __weak restore_top_of_low_cacheable(void) { return 0; } @@ -43,7 +44,7 @@ void set_late_cbmem_top(uintptr_t ramtop) } /* Top of CBMEM is at highest usable DRAM address below 4GiB. */ -uintptr_t __attribute__((weak)) restore_cbmem_top(void) +uintptr_t __weak restore_cbmem_top(void) { if (IS_ENABLED(CONFIG_LATE_CBMEM_INIT) && ENV_ROMSTAGE) if (!acpi_is_wakeup_s3()) diff --git a/src/arch/x86/mpspec.c b/src/arch/x86/mpspec.c index d41abaff5a..05605adf2e 100644 --- a/src/arch/x86/mpspec.c +++ b/src/arch/x86/mpspec.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -523,7 +524,7 @@ void *mptable_finalize(struct mp_config_table *mc) return smp_next_mpe_entry(mc); } -unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) +unsigned long __weak write_smp_table(unsigned long addr) { struct drivers_generic_ioapic_config *ioapic_config; struct mp_config_table *mc; diff --git a/src/arch/x86/pirq_routing.c b/src/arch/x86/pirq_routing.c index 892201e57c..96117fc43f 100644 --- a/src/arch/x86/pirq_routing.c +++ b/src/arch/x86/pirq_routing.c @@ -15,12 +15,13 @@ * GNU General Public License for more details. */ #include +#include #include #include #include #include -void __attribute__((weak)) pirq_assign_irqs(const unsigned char pirq[CONFIG_MAX_PIRQ_LINKS]) +void __weak pirq_assign_irqs(const unsigned char pirq[CONFIG_MAX_PIRQ_LINKS]) { } diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c index 7b5be6e9f0..6497b73e10 100644 --- a/src/arch/x86/postcar.c +++ b/src/arch/x86/postcar.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -24,7 +25,7 @@ * Systems without a native coreboot cache-as-ram teardown may implement * this to use an alternate method. */ -__attribute__((weak)) void late_car_teardown(void) { /* do nothing */ } +__weak void late_car_teardown(void) { /* do nothing */ } void main(void) { diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index bb4bc1abd1..25a41b53aa 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -330,7 +331,7 @@ static int create_smbios_type17_for_dimm(struct dimm_info *dimm, return t->length + smbios_string_table_len(t->eos); } -const char *__attribute__((weak)) smbios_mainboard_bios_version(void) +const char *__weak smbios_mainboard_bios_version(void) { if (strlen(CONFIG_LOCALVERSION)) return CONFIG_LOCALVERSION; @@ -397,53 +398,53 @@ static int smbios_write_type0(unsigned long *current, int handle) #if !IS_ENABLED(CONFIG_SMBIOS_PROVIDED_BY_MOBO) -const char *__attribute__((weak)) smbios_mainboard_serial_number(void) +const char *__weak smbios_mainboard_serial_number(void) { return CONFIG_MAINBOARD_SERIAL_NUMBER; } -const char *__attribute__((weak)) smbios_mainboard_version(void) +const char *__weak smbios_mainboard_version(void) { return CONFIG_MAINBOARD_VERSION; } -const char *__attribute__((weak)) smbios_mainboard_manufacturer(void) +const char *__weak smbios_mainboard_manufacturer(void) { return CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; } -const char *__attribute__((weak)) smbios_mainboard_product_name(void) +const char *__weak smbios_mainboard_product_name(void) { return CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME; } -void __attribute__((weak)) smbios_mainboard_set_uuid(u8 *uuid) +void __weak smbios_mainboard_set_uuid(u8 *uuid) { /* leave all zero */ } #endif -const char *__attribute__((weak)) smbios_mainboard_asset_tag(void) +const char *__weak smbios_mainboard_asset_tag(void) { return ""; } -u8 __attribute__((weak)) smbios_mainboard_feature_flags(void) +u8 __weak smbios_mainboard_feature_flags(void) { return 0; } -const char *__attribute__((weak)) smbios_mainboard_location_in_chassis(void) +const char *__weak smbios_mainboard_location_in_chassis(void) { return ""; } -smbios_board_type __attribute__((weak)) smbios_mainboard_board_type(void) +smbios_board_type __weak smbios_mainboard_board_type(void) { return SMBIOS_BOARD_TYPE_UNKNOWN; } -const char *__attribute__((weak)) smbios_mainboard_sku(void) +const char *__weak smbios_mainboard_sku(void) { return ""; } diff --git a/src/arch/x86/timestamp.c b/src/arch/x86/timestamp.c index 711c38e23b..b0aac9c1ab 100644 --- a/src/arch/x86/timestamp.c +++ b/src/arch/x86/timestamp.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include @@ -21,7 +22,7 @@ uint64_t timestamp_get(void) return rdtscll(); } -unsigned long __attribute__((weak)) tsc_freq_mhz(void) +unsigned long __weak tsc_freq_mhz(void) { /* Default to not knowing TSC frequency. cbmem will have to fallback * on trying to determine it in userspace. */ diff --git a/src/commonlib/storage/sdhci.c b/src/commonlib/storage/sdhci.c index bac510e12a..a5508ee032 100644 --- a/src/commonlib/storage/sdhci.c +++ b/src/commonlib/storage/sdhci.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -38,7 +39,7 @@ || (CONFIG_SDHCI_ADMA_IN_ROMSTAGE && ENV_ROMSTAGE) \ || ENV_POSTCAR || ENV_RAMSTAGE) -__attribute__((weak)) void *dma_malloc(size_t length_in_bytes) +__weak void *dma_malloc(size_t length_in_bytes) { return malloc(length_in_bytes); } @@ -278,20 +279,20 @@ static int sdhci_send_command_bounced(struct sd_mmc_ctrlr *ctrlr, return CARD_COMM_ERR; } -__attribute__((weak)) void sdhc_log_command(struct mmc_command *cmd) +__weak void sdhc_log_command(struct mmc_command *cmd) { } -__attribute__((weak)) void sdhc_log_command_issued(void) +__weak void sdhc_log_command_issued(void) { } -__attribute__((weak)) void sdhc_log_response(uint32_t entries, +__weak void sdhc_log_response(uint32_t entries, uint32_t *response) { } -__attribute__((weak)) void sdhc_log_ret(int ret) +__weak void sdhc_log_ret(int ret) { } @@ -715,7 +716,7 @@ static int sdhci_pre_init(struct sdhci_ctrlr *sdhci_ctrlr) return 0; } -__attribute__((weak)) void soc_sd_mmc_controller_quirks(struct sd_mmc_ctrlr +__weak void soc_sd_mmc_controller_quirks(struct sd_mmc_ctrlr *ctrlr) { } diff --git a/src/console/die.c b/src/console/die.c index 79babeceee..3f5ca45068 100644 --- a/src/console/die.c +++ b/src/console/die.c @@ -15,6 +15,7 @@ */ #include +#include #include #include @@ -27,7 +28,7 @@ * EC is capable of controlling LEDs or a buzzer the method can be overwritten * in EC directory instead. */ -__attribute__ ((weak)) void die_notify(void) +__weak void die_notify(void) { } diff --git a/src/console/post.c b/src/console/post.c index e7e914759d..1caa4b550a 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -16,6 +16,7 @@ #include #include +#include #include #include #include @@ -29,7 +30,7 @@ /* Some mainboards have very nice features beyond just a simple display. * They can override this function. */ -void __attribute__((weak)) mainboard_post(uint8_t value) +void __weak mainboard_post(uint8_t value) { } diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 59c3b8ab2f..272edb56b2 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -24,6 +24,7 @@ #else #include #endif +#include #include #include #include @@ -209,7 +210,7 @@ void intel_update_microcode_from_cbfs(void) } #if ENV_RAMSTAGE -__attribute__((weak)) int soc_skip_ucode_update(u32 currrent_patch_id, +__weak int soc_skip_ucode_update(u32 currrent_patch_id, u32 new_patch_id) { return 0; diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index fa5658e25e..d888e4410b 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -15,6 +15,7 @@ */ #include +#include #include #include #include @@ -208,13 +209,13 @@ void smi_handler(u32 smm_revision) * entries in the modules make sense. Without default implementations the * weak relocations w/o a symbol have a 0 address which is where the modules * are linked at. */ -int __attribute__((weak)) mainboard_io_trap_handler(int smif) { return 0; } -void __attribute__((weak)) cpu_smi_handler(unsigned int node, +int __weak mainboard_io_trap_handler(int smif) { return 0; } +void __weak cpu_smi_handler(unsigned int node, smm_state_save_area_t *state_save) {} -void __attribute__((weak)) northbridge_smi_handler(unsigned int node, +void __weak northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) {} -void __attribute__((weak)) southbridge_smi_handler(unsigned int node, +void __weak southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) {} -void __attribute__((weak)) mainboard_smi_gpi(u32 gpi_sts) {} -int __attribute__((weak)) mainboard_smi_apmc(u8 data) { return 0; } -void __attribute__((weak)) mainboard_smi_sleep(u8 slp_typ) {} +void __weak mainboard_smi_gpi(u32 gpi_sts) {} +int __weak mainboard_smi_apmc(u8 data) { return 0; } +void __weak mainboard_smi_sleep(u8 slp_typ) {} diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index c622e45c3d..c2001ec9e2 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -182,10 +183,10 @@ RMODULE_ENTRY(smm_handler_start); * entries in the modules make sense. Without default implementations the * weak relocations w/o a symbol have a 0 address which is where the modules * are linked at. */ -int __attribute__((weak)) mainboard_io_trap_handler(int smif) { return 0; } -void __attribute__((weak)) cpu_smi_handler(void) {} -void __attribute__((weak)) northbridge_smi_handler() {} -void __attribute__((weak)) southbridge_smi_handler() {} -void __attribute__((weak)) mainboard_smi_gpi(u32 gpi_sts) {} -int __attribute__((weak)) mainboard_smi_apmc(u8 data) { return 0; } -void __attribute__((weak)) mainboard_smi_sleep(u8 slp_typ) {} +int __weak mainboard_io_trap_handler(int smif) { return 0; } +void __weak cpu_smi_handler(void) {} +void __weak northbridge_smi_handler() {} +void __weak southbridge_smi_handler() {} +void __weak mainboard_smi_gpi(u32 gpi_sts) {} +int __weak mainboard_smi_apmc(u8 data) { return 0; } +void __weak mainboard_smi_sleep(u8 slp_typ) {} diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 15b0c4c23f..299f7c8bf7 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -19,6 +19,7 @@ #include #include +#include #include #include #include @@ -29,7 +30,7 @@ #include /* Rmodules don't like weak symbols. */ -u32 __attribute__((weak)) map_oprom_vendev(u32 vendev) { return vendev; } +u32 __weak map_oprom_vendev(u32 vendev) { return vendev; } struct rom_header *pci_rom_probe(struct device *dev) { diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index bd502b6bad..197a007a21 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -43,7 +44,7 @@ void asmlinkage early_all_cores(void) amd_initmmio(); } -void __attribute__((weak)) platform_once(struct sysinfo *cb) +void __weak platform_once(struct sysinfo *cb) { board_BeforeAgesa(cb); } diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index fdd2e6eeac..b73c1244d8 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -374,24 +375,24 @@ BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, amd_bs_post_device, #endif /* ENV_RAMSTAGE */ /* Empty stubs for cases board does not need to override anything. */ -void __attribute__((weak)) +void __weak board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) { } -void __attribute__((weak)) +void __weak board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) { } -void __attribute__((weak)) +void __weak board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) { } -void __attribute__((weak)) +void __weak board_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) { } -void __attribute__((weak)) +void __weak board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) { } -AGESA_STATUS __attribute__((weak)) +AGESA_STATUS __weak fchs3earlyrestore(AMD_CONFIG_PARAMS *StdHeader) { return AGESA_SUCCESS; } -AGESA_STATUS __attribute__((weak)) +AGESA_STATUS __weak fchs3laterestore(AMD_CONFIG_PARAMS *StdHeader) { return AGESA_SUCCESS; diff --git a/src/drivers/elog/gsmi.c b/src/drivers/elog/gsmi.c index 42bfd0f183..cced4a1293 100644 --- a/src/drivers/elog/gsmi.c +++ b/src/drivers/elog/gsmi.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -48,12 +49,12 @@ struct gsmi_clear_eventlog_param { u32 data_type; } __packed; -void __attribute__((weak)) elog_gsmi_cb_platform_log_wake_source(void) +void __weak elog_gsmi_cb_platform_log_wake_source(void) { /* Default weak implementation, does nothing. */ } -void __attribute__((weak)) elog_gsmi_cb_mainboard_log_wake_source(void) +void __weak elog_gsmi_cb_mainboard_log_wake_source(void) { /* Default weak implementation, does nothing. */ } diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index 96e00379c8..3c2f5bd198 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -31,6 +31,7 @@ #include #include +#include #include #include #include @@ -58,7 +59,7 @@ struct tpm_inf_dev { static struct tpm_inf_dev g_tpm_dev CAR_GLOBAL; -__attribute__((weak)) int tis_plat_irq_status(void) +__weak int tis_plat_irq_status(void) { static int warning_displayed CAR_GLOBAL; diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index e1a9b9db6c..686a4c8c7e 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -100,18 +101,18 @@ asmlinkage void after_cache_as_ram(void *chipset_context) after_cache_as_ram_stage(); } -void __attribute__((weak)) car_mainboard_pre_console_init(void) +void __weak car_mainboard_pre_console_init(void) { } -void __attribute__((weak)) car_soc_pre_console_init(void) +void __weak car_soc_pre_console_init(void) { } -void __attribute__((weak)) car_mainboard_post_console_init(void) +void __weak car_mainboard_post_console_init(void) { } -void __attribute__((weak)) car_soc_post_console_init(void) +void __weak car_soc_post_console_init(void) { } diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 2bdac0a340..e5714ae140 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -296,7 +297,7 @@ void raminit(struct romstage_params *params) } /* Initialize the UPD parameters for MemoryInit */ -__attribute__((weak)) void mainboard_memory_init_params( +__weak void mainboard_memory_init_params( struct romstage_params *params, MEMORY_INIT_UPD *upd_ptr) { @@ -304,7 +305,7 @@ __attribute__((weak)) void mainboard_memory_init_params( } /* Display the UPD parameters for MemoryInit */ -__attribute__((weak)) void soc_display_memory_init_params( +__weak void soc_display_memory_init_params( const MEMORY_INIT_UPD *old, MEMORY_INIT_UPD *new) { printk(BIOS_SPEW, "UPD values for MemoryInit:\n"); @@ -312,7 +313,7 @@ __attribute__((weak)) void soc_display_memory_init_params( } /* Initialize the UPD parameters for MemoryInit */ -__attribute__((weak)) void soc_memory_init_params( +__weak void soc_memory_init_params( struct romstage_params *params, MEMORY_INIT_UPD *upd) { diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 563a030220..a4609df573 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -28,7 +29,7 @@ #include /* SOC initialization after FSP silicon init */ -__attribute__((weak)) void soc_after_silicon_init(void) +__weak void soc_after_silicon_init(void) { } @@ -215,13 +216,13 @@ void intel_silicon_init(void) } /* Initialize the UPD parameters for SiliconInit */ -__attribute__((weak)) void mainboard_silicon_init_params( +__weak void mainboard_silicon_init_params( SILICON_INIT_UPD *params) { }; /* Display the UPD parameters for SiliconInit */ -__attribute__((weak)) void soc_display_silicon_init_params( +__weak void soc_display_silicon_init_params( const SILICON_INIT_UPD *old, SILICON_INIT_UPD *new) { printk(BIOS_SPEW, "UPD values for SiliconInit:\n"); @@ -229,6 +230,6 @@ __attribute__((weak)) void soc_display_silicon_init_params( } /* Initialize the UPD parameters for SiliconInit */ -__attribute__((weak)) void soc_silicon_init_params(SILICON_INIT_UPD *params) +__weak void soc_silicon_init_params(SILICON_INIT_UPD *params) { } diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 88401f0b4b..ba08cdc42b 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -185,13 +186,13 @@ void after_cache_as_ram_stage(void) } /* Initialize the power state */ -__attribute__((weak)) struct chipset_power_state *fill_power_state(void) +__weak struct chipset_power_state *fill_power_state(void) { return NULL; } /* Board initialization before and after RAM is enabled */ -__attribute__((weak)) void mainboard_romstage_entry( +__weak void mainboard_romstage_entry( struct romstage_params *params) { post_code(0x31); @@ -201,7 +202,7 @@ __attribute__((weak)) void mainboard_romstage_entry( } /* Save the DIMM information for SMBIOS table 17 */ -__attribute__((weak)) void mainboard_save_dimm_info( +__weak void mainboard_save_dimm_info( struct romstage_params *params) { int channel; @@ -330,7 +331,7 @@ __attribute__((weak)) void mainboard_save_dimm_info( } /* Add any mainboard specific information */ -__attribute__((weak)) void mainboard_add_dimm_info( +__weak void mainboard_add_dimm_info( struct romstage_params *params, struct memory_info *mem_info, int channel, int dimm, int index) @@ -338,44 +339,44 @@ __attribute__((weak)) void mainboard_add_dimm_info( } /* Get the memory configuration data */ -__attribute__((weak)) int mrc_cache_get_current(int type, uint32_t version, +__weak int mrc_cache_get_current(int type, uint32_t version, struct region_device *rdev) { return -1; } /* Save the memory configuration data */ -__attribute__((weak)) int mrc_cache_stash_data(int type, uint32_t version, +__weak int mrc_cache_stash_data(int type, uint32_t version, const void *data, size_t size) { return -1; } /* Transition RAM from off or self-refresh to active */ -__attribute__((weak)) void raminit(struct romstage_params *params) +__weak void raminit(struct romstage_params *params) { post_code(0x34); die("ERROR - No RAM initialization specified!\n"); } /* Display the memory configuration */ -__attribute__((weak)) void report_memory_config(void) +__weak void report_memory_config(void) { } /* Choose top of stack and setup MTRRs */ -__attribute__((weak)) void *setup_stack_and_mtrrs(void) +__weak void *setup_stack_and_mtrrs(void) { die("ERROR - Must specify top of stack!\n"); return NULL; } /* SOC initialization after RAM is enabled */ -__attribute__((weak)) void soc_after_ram_init(struct romstage_params *params) +__weak void soc_after_ram_init(struct romstage_params *params) { } /* SOC initialization before RAM is enabled */ -__attribute__((weak)) void soc_pre_ram_init(struct romstage_params *params) +__weak void soc_pre_ram_init(struct romstage_params *params) { } diff --git a/src/drivers/intel/fsp2_0/graphics.c b/src/drivers/intel/fsp2_0/graphics.c index f1219ea15c..ae1442ee9d 100644 --- a/src/drivers/intel/fsp2_0/graphics.c +++ b/src/drivers/intel/fsp2_0/graphics.c @@ -124,7 +124,7 @@ int fill_lb_framebuffer(struct lb_framebuffer *framebuffer) return 0; } -__attribute__((weak)) uintptr_t fsp_soc_get_igd_bar(void) +__weak uintptr_t fsp_soc_get_igd_bar(void) { return 0; } diff --git a/src/drivers/intel/fsp2_0/hob_display.c b/src/drivers/intel/fsp2_0/hob_display.c index d9838e9462..977facbfc6 100644 --- a/src/drivers/intel/fsp2_0/hob_display.c +++ b/src/drivers/intel/fsp2_0/hob_display.c @@ -157,7 +157,7 @@ const char *fsp_get_guid_name(const uint8_t *guid) return "Unknown GUID"; } -__attribute__((weak)) const char *soc_get_hob_type_name( +__weak const char *soc_get_hob_type_name( const struct hob_header *hob) { return NULL; @@ -173,7 +173,7 @@ void fsp_print_guid_extension_hob(const struct hob_header *hob) printk(BIOS_SPEW, ": %s\n", fsp_get_guid_name(res->owner_guid)); } -__attribute__((weak)) const char *soc_get_guid_name(const uint8_t *guid) +__weak const char *soc_get_guid_name(const uint8_t *guid) { return NULL; } @@ -212,6 +212,6 @@ void fsp_display_hobs(void) } } -__attribute__((weak)) void soc_display_hob(const struct hob_header *hob) +__weak void soc_display_hob(const struct hob_header *hob) { } diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 0abe121aa6..30987ce500 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -307,13 +307,13 @@ static enum cb_err fsp_fill_common_arch_params(FSPM_ARCH_UPD *arch_upd, return CB_SUCCESS; } -__attribute__((weak)) +__weak uint8_t fsp_memory_mainboard_version(void) { return 0; } -__attribute__((weak)) +__weak uint8_t fsp_memory_soc_version(void) { return 0; diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index 34a4262049..6d6d623be4 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -12,6 +12,7 @@ #include #include +#include #include #include #include @@ -87,7 +88,7 @@ BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, fsp_notify_dummy, BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_dummy, (void *) READY_TO_BOOT); -__attribute__((weak)) void platform_fsp_notify_status( +__weak void platform_fsp_notify_status( enum fsp_notify_phase phase) { } diff --git a/src/drivers/intel/fsp2_0/upd_display.c b/src/drivers/intel/fsp2_0/upd_display.c index 8df48659fa..415505e1dd 100644 --- a/src/drivers/intel/fsp2_0/upd_display.c +++ b/src/drivers/intel/fsp2_0/upd_display.c @@ -10,6 +10,7 @@ */ #include +#include #include #include #include @@ -50,7 +51,7 @@ static void fspm_display_arch_params(const FSPM_ARCH_UPD *old, } /* Display the UPD parameters for MemoryInit */ -__attribute__((weak)) void soc_display_fspm_upd_params( +__weak void soc_display_fspm_upd_params( const FSPM_UPD *fspm_old_upd, const FSPM_UPD *fspm_new_upd) { @@ -67,7 +68,7 @@ void fspm_display_upd_values(const FSPM_UPD *old, } /* Display the UPD parameters for SiliconInit */ -__attribute__((weak)) void soc_display_fsps_upd_params( +__weak void soc_display_fsps_upd_params( const FSPS_UPD *fsps_old_upd, const FSPS_UPD *fsps_new_upd) { diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c index 57bd9b090a..1cf89cf14e 100644 --- a/src/drivers/intel/wifi/wifi.c +++ b/src/drivers/intel/wifi/wifi.c @@ -64,7 +64,7 @@ static int smbios_write_wifi(struct device *dev, int *handle, } #endif -__attribute__((weak)) +__weak int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits) { return -1; diff --git a/src/drivers/spi/spi-generic.c b/src/drivers/spi/spi-generic.c index 6d7fcdc021..f1b11aedf7 100644 --- a/src/drivers/spi/spi-generic.c +++ b/src/drivers/spi/spi-generic.c @@ -15,6 +15,7 @@ */ #include +#include #include #include @@ -116,7 +117,7 @@ unsigned int spi_crop_chunk(const struct spi_slave *slave, unsigned int cmd_len, return min(ctrlr_max, buf_len); } -void __attribute__((weak)) spi_init(void) +void __weak spi_init(void) { /* Default weak implementation - do nothing. */ } diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index c0fee46dc7..3206ba1fa4 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -17,6 +17,7 @@ #include #include +#include #include #include #include @@ -64,7 +65,7 @@ void tpm2_get_info(struct tpm2_info *info) *info = car_get_var(g_tpm_info); } -__attribute__((weak)) int tis_plat_irq_status(void) +__weak int tis_plat_irq_status(void) { static int warning_displayed CAR_GLOBAL; diff --git a/src/ec/google/chromeec/crosec_proto.c b/src/ec/google/chromeec/crosec_proto.c index a63cfada5d..1a8ffb93c5 100644 --- a/src/ec/google/chromeec/crosec_proto.c +++ b/src/ec/google/chromeec/crosec_proto.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -23,7 +24,7 @@ #include "ec_message.h" /* Common utilities */ -void * __attribute__((weak)) crosec_get_buffer(size_t size, int req) +void * __weak crosec_get_buffer(size_t size, int req) { printk(BIOS_DEBUG, "crosec_get_buffer() implementation required.\n"); return NULL; diff --git a/src/include/compiler.h b/src/include/compiler.h index a830239009..e088eb1a51 100644 --- a/src/include/compiler.h +++ b/src/include/compiler.h @@ -25,5 +25,6 @@ #define __aligned(x) __attribute__((aligned(x))) #define __always_unused __attribute__((unused)) #define __must_check __attribute__((warn_unused_result)) +#define __weak __attribute__((weak)) #endif diff --git a/src/lib/boot_device.c b/src/lib/boot_device.c index e7968f4fa9..c5afce7161 100644 --- a/src/lib/boot_device.c +++ b/src/lib/boot_device.c @@ -14,8 +14,9 @@ */ #include +#include -void __attribute__((weak)) boot_device_init(void) +void __weak boot_device_init(void) { /* Provide weak do-nothing init. */ } diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index 2e228c6d32..bee28459ef 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -16,6 +16,7 @@ #include #include +#include #include #include #include @@ -25,10 +26,10 @@ DECLARE_OPTIONAL_REGION(timestamp); -__attribute__((weak)) void bootblock_mainboard_early_init(void) { /* no-op */ } -__attribute__((weak)) void bootblock_soc_early_init(void) { /* do nothing */ } -__attribute__((weak)) void bootblock_soc_init(void) { /* do nothing */ } -__attribute__((weak)) void bootblock_mainboard_init(void) { /* do nothing */ } +__weak void bootblock_mainboard_early_init(void) { /* no-op */ } +__weak void bootblock_soc_early_init(void) { /* do nothing */ } +__weak void bootblock_soc_init(void) { /* do nothing */ } +__weak void bootblock_mainboard_init(void) { /* do nothing */ } asmlinkage void bootblock_main_with_timestamp(uint64_t base_timestamp) { diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 9e81bd3a3a..2dcd429361 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -308,7 +309,7 @@ static int cbfs_master_header_props(struct cbfs_props *props) /* This struct is marked as weak to allow a particular platform to * override the master header logic. This implementation should work for most * devices. */ -const struct cbfs_locator __attribute__((weak)) cbfs_master_header_locator = { +const struct cbfs_locator __weak cbfs_master_header_locator = { .name = "Master Header Locator", .locate = cbfs_master_header_props, }; diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c index 166ec87013..2451fca8c7 100644 --- a/src/lib/cbmem_common.c +++ b/src/lib/cbmem_common.c @@ -14,6 +14,7 @@ */ #include #include +#include #include #include #include @@ -37,7 +38,7 @@ void cbmem_run_init_hooks(int is_recovery) } } -void __attribute__((weak)) cbmem_fail_resume(void) +void __weak cbmem_fail_resume(void) { } diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index e786443cf6..2970215034 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -16,6 +16,7 @@ */ #include +#include #include #include #include @@ -244,9 +245,9 @@ static inline void lb_vboot_handoff(struct lb_header *header) {} #endif /* CONFIG_VBOOT */ #endif /* CONFIG_CHROMEOS */ -__attribute__((weak)) uint32_t board_id(void) { return UNDEFINED_STRAPPING_ID; } -__attribute__((weak)) uint32_t ram_code(void) { return UNDEFINED_STRAPPING_ID; } -__attribute__((weak)) uint32_t sku_id(void) { return UNDEFINED_STRAPPING_ID; } +__weak uint32_t board_id(void) { return UNDEFINED_STRAPPING_ID; } +__weak uint32_t ram_code(void) { return UNDEFINED_STRAPPING_ID; } +__weak uint32_t sku_id(void) { return UNDEFINED_STRAPPING_ID; } static void lb_board_id(struct lb_header *header) { @@ -441,7 +442,7 @@ static void lb_record_version_timestamp(struct lb_header *header) rec->timestamp = coreboot_version_timestamp; } -void __attribute__((weak)) lb_board(struct lb_header *header) { /* NOOP */ } +void __weak lb_board(struct lb_header *header) { /* NOOP */ } /* * It's possible that the system is using a SPI flash as the boot device, @@ -449,7 +450,7 @@ void __attribute__((weak)) lb_board(struct lb_header *header) { /* NOOP */ } * case don't provide any information as the correct information is * not known. */ -void __attribute__((weak)) lb_spi_flash(struct lb_header *header) { /* NOOP */ } +void __weak lb_spi_flash(struct lb_header *header) { /* NOOP */ } static struct lb_forward *lb_forward(struct lb_header *header, struct lb_header *next_header) diff --git a/src/lib/fallback_boot.c b/src/lib/fallback_boot.c index 443f209b1d..a079910262 100644 --- a/src/lib/fallback_boot.c +++ b/src/lib/fallback_boot.c @@ -1,8 +1,9 @@ #include +#include #include /* Implement platform specific override. */ -void __attribute__((weak)) set_boot_successful(void) { } +void __weak set_boot_successful(void) { } void boot_successful(void) { diff --git a/src/lib/gpio.c b/src/lib/gpio.c index 48db262a11..b52d7b0c5f 100644 --- a/src/lib/gpio.c +++ b/src/lib/gpio.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -168,13 +169,13 @@ int _gpio_base3_value(const gpio_t gpio[], int num_gpio, int binary_first) } /* Default handler for ACPI path is to return NULL */ -__attribute__((weak)) const char *gpio_acpi_path(gpio_t gpio) +__weak const char *gpio_acpi_path(gpio_t gpio) { return NULL; } /* Default handler returns 0 because type of gpio_t is unknown */ -__attribute__((weak)) uint16_t gpio_acpi_pin(gpio_t gpio) +__weak uint16_t gpio_acpi_pin(gpio_t gpio) { return 0; } diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 0deab4bd0b..6fd55d7758 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -115,7 +116,7 @@ static struct boot_state boot_states[] = { BS_INIT_ENTRY(BS_PAYLOAD_BOOT, bs_payload_boot), }; -void __attribute__((weak)) arch_bootstate_coreboot_exit(void) { } +void __weak arch_bootstate_coreboot_exit(void) { } static boot_state_t bs_pre_device(void *arg) { diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index 5713c2c328..cc1294f353 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -109,7 +110,7 @@ void cbmem_initialize_empty(void) cbmem_initialize_empty_id_size(0, 0); } -void __attribute__((weak)) cbmem_top_init(void) +void __weak cbmem_top_init(void) { } diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 128869b2ba..8a6d6afafa 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -71,9 +72,9 @@ fail: halt(); } -void __attribute__((weak)) stage_cache_add(int stage_id, +void __weak stage_cache_add(int stage_id, const struct prog *stage) {} -void __attribute__((weak)) stage_cache_load_stage(int stage_id, +void __weak stage_cache_load_stage(int stage_id, struct prog *stage) {} static void ramstage_cache_invalid(void) @@ -164,7 +165,7 @@ fail: static struct prog global_payload = PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/payload"); -void __attribute__((weak)) mirror_payload(struct prog *payload) +void __weak mirror_payload(struct prog *payload) { } diff --git a/src/lib/prog_ops.c b/src/lib/prog_ops.c index 44a32d19bf..5e670d34c0 100644 --- a/src/lib/prog_ops.c +++ b/src/lib/prog_ops.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include /* For each segment of a program loaded this function is called*/ @@ -23,13 +24,13 @@ void prog_segment_loaded(uintptr_t start, size_t size, int flags) arch_segment_loaded(start, size, flags); } -void __attribute__((weak)) platform_segment_loaded(uintptr_t start, +void __weak platform_segment_loaded(uintptr_t start, size_t size, int flags) { /* do nothing */ } -void __attribute__((weak)) arch_segment_loaded(uintptr_t start, size_t size, +void __weak arch_segment_loaded(uintptr_t start, size_t size, int flags) { /* do nothing */ @@ -41,7 +42,7 @@ void prog_run(struct prog *prog) arch_prog_run(prog); } -void __attribute__((weak)) platform_prog_run(struct prog *prog) +void __weak platform_prog_run(struct prog *prog) { /* do nothing */ } diff --git a/src/lib/reset.c b/src/lib/reset.c index 703118a6f5..2c9529277e 100644 --- a/src/lib/reset.c +++ b/src/lib/reset.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -27,10 +28,10 @@ __attribute__((noreturn)) static void __hard_reset(void) { } /* Not all platforms implement all reset types. Fall back to hard_reset. */ -__attribute__((weak)) void do_global_reset(void) { __hard_reset(); } -__attribute__((weak)) void do_soft_reset(void) { __hard_reset(); } +__weak void do_global_reset(void) { __hard_reset(); } +__weak void do_soft_reset(void) { __hard_reset(); } -__attribute__((weak)) void soc_reset_prepare(enum reset_type rt) { /* no-op */ } +__weak void soc_reset_prepare(enum reset_type rt) { /* no-op */ } void global_reset(void) { diff --git a/src/lib/timer.c b/src/lib/timer.c index adc0d07cef..625bfc0a77 100644 --- a/src/lib/timer.c +++ b/src/lib/timer.c @@ -13,12 +13,13 @@ * GNU General Public License for more details. */ +#include #include #include #include #include -__attribute__((weak)) void init_timer(void) { /* do nothing */ } +__weak void init_timer(void) { /* do nothing */ } void udelay(unsigned int usec) { diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 2ab725372b..bf49365c86 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -361,7 +361,7 @@ ROMSTAGE_CBMEM_INIT_HOOK(timestamp_sync_cache_to_cbmem) RAMSTAGE_CBMEM_INIT_HOOK(timestamp_sync_cache_to_cbmem) /* Provide default timestamp implementation using monotonic timer. */ -uint64_t __attribute__((weak)) timestamp_get(void) +uint64_t __weak timestamp_get(void) { struct mono_time t1, t2; @@ -375,7 +375,7 @@ uint64_t __attribute__((weak)) timestamp_get(void) } /* Like timestamp_get() above this matches up with microsecond granularity. */ -int __attribute__((weak)) timestamp_tick_freq_mhz(void) +int __weak timestamp_tick_freq_mhz(void) { return 1; } diff --git a/src/lib/wrdd.c b/src/lib/wrdd.c index da082f8163..a8390cf732 100644 --- a/src/lib/wrdd.c +++ b/src/lib/wrdd.c @@ -14,9 +14,10 @@ * GNU General Public License for more details. */ +#include #include -uint16_t __attribute__((weak)) wifi_regulatory_domain(void) +uint16_t __weak wifi_regulatory_domain(void) { return WRDD_DEFAULT_REGULATORY_DOMAIN; } diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c index 5b4bcc0ebe..e56e3d2e1a 100644 --- a/src/mainboard/google/cyan/romstage.c +++ b/src/mainboard/google/cyan/romstage.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -47,7 +48,7 @@ void mainboard_memory_init_params(struct romstage_params *params, variant_memory_init_params(memory_params); } -__attribute__ ((weak)) +__weak void variant_memory_init_params(MEMORY_INIT_UPD *memory_params) { } diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c index a3db2ed6f4..97e14eb758 100644 --- a/src/mainboard/google/cyan/spd/spd.c +++ b/src/mainboard/google/cyan/spd/spd.c @@ -16,6 +16,7 @@ #include #include +#include #include #include #include @@ -28,7 +29,7 @@ #include #include "spd_util.h" -__attribute__ ((weak)) uint8_t get_ramid(void) +__weak uint8_t get_ramid(void) { gpio_t spd_gpios[] = { GP_SW_80, /* SATA_GP3, RAMID0 */ diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index cd37c90f28..f1df8817e7 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -225,7 +226,7 @@ struct chip_operations mainboard_ops = { }; /* Variants may override this function so see definitions in variants/ */ -uint8_t __attribute__((weak)) variant_board_sku(void) +uint8_t __weak variant_board_sku(void) { return 0; } diff --git a/src/mainboard/google/kahlee/romstage.c b/src/mainboard/google/kahlee/romstage.c index 4cd2d40831..50e9931a73 100644 --- a/src/mainboard/google/kahlee/romstage.c +++ b/src/mainboard/google/kahlee/romstage.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -22,7 +23,7 @@ int mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len) return variant_mainboard_read_spd(spdAddress, buf, len); } -void __attribute__((weak)) variant_romstage_entry(int s3_resume) +void __weak variant_romstage_entry(int s3_resume) { /* By default, don't do anything */ } diff --git a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c index c9ce900e22..6ed516f7c6 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c +++ b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -236,7 +237,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieNoBayhub = { * **/ /*---------------------------------------------------------------------------*/ -VOID __attribute__((weak)) OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly) +VOID __weak OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly) { InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex; InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus; diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index 8f4ba5c26f..cc75f29113 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -485,7 +486,7 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_GPI(GPIO_135, PULL_UP), }; -const __attribute__((weak)) +const __weak struct soc_amd_gpio *variant_early_gpio_table(size_t *size) { if (board_id() < 2) { @@ -497,7 +498,7 @@ struct soc_amd_gpio *variant_early_gpio_table(size_t *size) } } -const __attribute__((weak)) +const __weak struct soc_amd_gpio *variant_gpio_table(size_t *size) { if (board_id() < 2) { @@ -565,13 +566,13 @@ static const struct sci_source gpe_table[] = { }, }; -const __attribute__((weak)) struct sci_source *get_gpe_table(size_t *num) +const __weak struct sci_source *get_gpe_table(size_t *num) { *num = ARRAY_SIZE(gpe_table); return gpe_table; } -int __attribute__((weak)) variant_get_xhci_oc_map(uint16_t *map) +int __weak variant_get_xhci_oc_map(uint16_t *map) { *map = USB_OC0 << OC_PORT0_SHIFT; /* USB-C Port0/4 = OC0 */ *map |= USB_OC1 << OC_PORT1_SHIFT; /* USB-C Port1/5 = OC1 */ @@ -580,7 +581,7 @@ int __attribute__((weak)) variant_get_xhci_oc_map(uint16_t *map) return 0; } -int __attribute__((weak)) variant_get_ehci_oc_map(uint16_t *map) +int __weak variant_get_ehci_oc_map(uint16_t *map) { *map = USB_OC_DISABLE_ALL; return 0; diff --git a/src/mainboard/google/kahlee/variants/baseboard/memory.c b/src/mainboard/google/kahlee/variants/baseboard/memory.c index b8ec917633..280140ba4d 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/memory.c +++ b/src/mainboard/google/kahlee/variants/baseboard/memory.c @@ -14,13 +14,14 @@ */ #include +#include #include #include /* src/include/gpio.h */ #include #include #include -uint8_t __attribute__((weak)) variant_memory_sku(void) +uint8_t __weak variant_memory_sku(void) { gpio_t pads[] = { [3] = MEM_CONFIG3, @@ -32,7 +33,7 @@ uint8_t __attribute__((weak)) variant_memory_sku(void) return gpio_base2_value(pads, ARRAY_SIZE(pads)); } -int __attribute__((weak)) variant_mainboard_read_spd(uint8_t spdAddress, +int __weak variant_mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len) { struct region_device spd_rdev; diff --git a/src/mainboard/google/octopus/variants/baseboard/boardid.c b/src/mainboard/google/octopus/variants/baseboard/boardid.c index 67b753e663..198baaa4aa 100644 --- a/src/mainboard/google/octopus/variants/baseboard/boardid.c +++ b/src/mainboard/google/octopus/variants/baseboard/boardid.c @@ -13,10 +13,11 @@ * GNU General Public License for more details. */ +#include #include #include -uint8_t __attribute__((weak)) variant_board_id(void) +uint8_t __weak variant_board_id(void) { return google_chromeec_get_board_version(); } diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index 6c01c49144..8863bbbba1 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -16,6 +16,7 @@ #include #include #include +#include /* * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing' @@ -254,7 +255,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_210, 0, DEEP, NONE, HIZCRx0, DISPUPD), }; -const struct pad_config *__attribute__((weak)) variant_gpio_table(size_t *num) +const struct pad_config *__weak variant_gpio_table(size_t *num) { *num = ARRAY_SIZE(gpio_table); return gpio_table; @@ -280,7 +281,7 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ }; -const struct pad_config *__attribute__((weak)) +const struct pad_config *__weak variant_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); @@ -291,7 +292,7 @@ variant_early_gpio_table(size_t *num) static const struct pad_config sleep_gpio_table[] = { }; -const struct pad_config *__attribute__((weak)) +const struct pad_config *__weak variant_sleep_gpio_table(size_t *num) { *num = ARRAY_SIZE(sleep_gpio_table); @@ -302,7 +303,7 @@ static const struct cros_gpio cros_gpios[] = { CROS_GPIO_WP_AH(PAD_SCC(GPIO_PCH_WP), GPIO_COMM_SCC_NAME), }; -const struct cros_gpio *__attribute__((weak)) variant_cros_gpios(size_t *num) +const struct cros_gpio *__weak variant_cros_gpios(size_t *num) { *num = ARRAY_SIZE(cros_gpios); return cros_gpios; diff --git a/src/mainboard/google/octopus/variants/baseboard/memory.c b/src/mainboard/google/octopus/variants/baseboard/memory.c index 303241fc4b..4c1d359aee 100644 --- a/src/mainboard/google/octopus/variants/baseboard/memory.c +++ b/src/mainboard/google/octopus/variants/baseboard/memory.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -133,12 +134,12 @@ static const struct lpddr4_cfg lp4cfg = { .swizzle_config = &baseboard_lpddr4_swizzle, }; -const struct lpddr4_cfg *__attribute__((weak)) variant_lpddr4_config(void) +const struct lpddr4_cfg *__weak variant_lpddr4_config(void) { return &lp4cfg; } -size_t __attribute__((weak)) variant_memory_sku(void) +size_t __weak variant_memory_sku(void) { gpio_t pads[] = { [3] = MEM_CONFIG3, [2] = MEM_CONFIG2, diff --git a/src/mainboard/google/octopus/variants/baseboard/nhlt.c b/src/mainboard/google/octopus/variants/baseboard/nhlt.c index 4fc216ed51..94403a8c35 100644 --- a/src/mainboard/google/octopus/variants/baseboard/nhlt.c +++ b/src/mainboard/google/octopus/variants/baseboard/nhlt.c @@ -14,11 +14,12 @@ */ #include +#include #include #include #include -void __attribute__((weak)) variant_nhlt_init(struct nhlt *nhlt) +void __weak variant_nhlt_init(struct nhlt *nhlt) { /* 2 Channel DMIC array. */ if (!nhlt_soc_add_dmic_array(nhlt, 2)) diff --git a/src/mainboard/google/poppy/ramstage.c b/src/mainboard/google/poppy/ramstage.c index c038b4186e..ea15aea988 100644 --- a/src/mainboard/google/poppy/ramstage.c +++ b/src/mainboard/google/poppy/ramstage.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include @@ -29,7 +30,7 @@ void mainboard_silicon_init_params(FSP_SIL_UPD *params) gpio_configure_pads(pads, num); } -void __attribute__((weak)) variant_devtree_update(void) +void __weak variant_devtree_update(void) { /* Override dev tree settings per board */ } diff --git a/src/mainboard/google/poppy/variants/baseboard/gpio.c b/src/mainboard/google/poppy/variants/baseboard/gpio.c index 2fea253624..25202e6139 100644 --- a/src/mainboard/google/poppy/variants/baseboard/gpio.c +++ b/src/mainboard/google/poppy/variants/baseboard/gpio.c @@ -16,6 +16,7 @@ #include #include #include +#include /* Pad configuration in ramstage */ /* Leave eSPI pins untouched from default settings */ @@ -371,13 +372,13 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), }; -const struct pad_config * __attribute__((weak)) variant_gpio_table(size_t *num) +const struct pad_config * __weak variant_gpio_table(size_t *num) { *num = ARRAY_SIZE(gpio_table); return gpio_table; } -const struct pad_config * __attribute__((weak)) +const struct pad_config * __weak variant_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); @@ -385,7 +386,7 @@ const struct pad_config * __attribute__((weak)) } /* override specific gpio by sku id */ -const struct pad_config * __attribute__((weak)) +const struct pad_config * __weak variant_sku_gpio_table(size_t *num) { *num = 0; @@ -397,7 +398,7 @@ static const struct cros_gpio cros_gpios[] = { CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), }; -const struct cros_gpio * __attribute__((weak)) variant_cros_gpios(size_t *num) +const struct cros_gpio * __weak variant_cros_gpios(size_t *num) { *num = ARRAY_SIZE(cros_gpios); return cros_gpios; diff --git a/src/mainboard/google/poppy/variants/baseboard/memory.c b/src/mainboard/google/poppy/variants/baseboard/memory.c index 8134f1a36e..95f2b9567c 100644 --- a/src/mainboard/google/poppy/variants/baseboard/memory.c +++ b/src/mainboard/google/poppy/variants/baseboard/memory.c @@ -14,6 +14,7 @@ */ #include +#include #include #include @@ -37,7 +38,7 @@ static const u16 rcomp_resistor[] = { 200, 81, 162 }; /* Rcomp target */ static const u16 rcomp_target[] = { 100, 40, 40, 23, 40 }; -void __attribute__((weak)) variant_memory_params(struct memory_params *p) +void __weak variant_memory_params(struct memory_params *p) { p->type = MEMORY_LPDDR3; p->dq_map = dq_map; @@ -50,7 +51,7 @@ void __attribute__((weak)) variant_memory_params(struct memory_params *p) p->rcomp_target_size = sizeof(rcomp_target); } -int __attribute__((weak)) variant_memory_sku(void) +int __weak variant_memory_sku(void) { gpio_t spd_gpios[] = { GPIO_MEM_CONFIG_0, diff --git a/src/mainboard/google/poppy/variants/baseboard/nhlt.c b/src/mainboard/google/poppy/variants/baseboard/nhlt.c index 81557e41ea..927cb242da 100644 --- a/src/mainboard/google/poppy/variants/baseboard/nhlt.c +++ b/src/mainboard/google/poppy/variants/baseboard/nhlt.c @@ -14,11 +14,12 @@ */ #include +#include #include #include #include -void __attribute__((weak)) variant_nhlt_init(struct nhlt *nhlt) +void __weak variant_nhlt_init(struct nhlt *nhlt) { /* 2 Channel DMIC array. */ if (nhlt_soc_add_dmic_array(nhlt, 2)) @@ -37,7 +38,7 @@ void __attribute__((weak)) variant_nhlt_init(struct nhlt *nhlt) printk(BIOS_ERR, "Couldn't add Realtek RT5663.\n"); } -void __attribute__((weak)) variant_nhlt_oem_overrides(const char **oem_id, +void __weak variant_nhlt_oem_overrides(const char **oem_id, const char **oem_table_id, uint32_t *oem_revision) { diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index 7f5a1b3857..6831d57790 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -30,7 +31,7 @@ #include /* override specific gpio by sku id */ -const struct pad_config __attribute__((weak)) +const struct pad_config __weak *variant_sku_gpio_table(size_t *num) { *num = 0; @@ -73,7 +74,7 @@ uint8_t sku_strapping_value(void) return gpio_base3_value(board_sku_gpios, num); } -uint8_t __attribute__((weak)) variant_board_sku(void) +uint8_t __weak variant_board_sku(void) { static int board_sku_num = -1; @@ -84,7 +85,7 @@ uint8_t __attribute__((weak)) variant_board_sku(void) } /* Set variant board sku to ec by sku id */ -void __attribute__((weak)) variant_board_ec_set_skuid(void) +void __weak variant_board_ec_set_skuid(void) { } @@ -97,7 +98,7 @@ const char *smbios_mainboard_sku(void) return sku_str; } -void __attribute__((weak)) variant_nhlt_oem_overrides(const char **oem_id, +void __weak variant_nhlt_oem_overrides(const char **oem_id, const char **oem_table_id, uint32_t *oem_revision) { diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c index 7440cf8f2c..3cd765b359 100644 --- a/src/mainboard/google/reef/variants/baseboard/gpio.c +++ b/src/mainboard/google/reef/variants/baseboard/gpio.c @@ -16,6 +16,7 @@ #include #include #include +#include /* * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing' @@ -345,7 +346,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_73, UP_20K, DEEP), /* GP_CAMERASB11 */ }; -const struct pad_config * __attribute__((weak)) variant_gpio_table(size_t *num) +const struct pad_config * __weak variant_gpio_table(size_t *num) { *num = ARRAY_SIZE(gpio_table); return gpio_table; @@ -362,7 +363,7 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */ }; -const struct pad_config * __attribute__((weak)) +const struct pad_config * __weak variant_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); @@ -375,7 +376,7 @@ static const struct pad_config sleep_gpio_table[] = { PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP), /* NFC_INT_L */ }; -const struct pad_config * __attribute__((weak)) +const struct pad_config * __weak variant_sleep_gpio_table(u8 slp_typ, size_t *num) { *num = ARRAY_SIZE(sleep_gpio_table); @@ -388,7 +389,7 @@ static const struct cros_gpio cros_gpios[] = { CROS_GPIO_PE_AH(PAD_N(GPIO_SHIP_MODE), GPIO_COMM_N_NAME), }; -const struct cros_gpio * __attribute__((weak)) variant_cros_gpios(size_t *num) +const struct cros_gpio * __weak variant_cros_gpios(size_t *num) { *num = ARRAY_SIZE(cros_gpios); return cros_gpios; diff --git a/src/mainboard/google/reef/variants/baseboard/memory.c b/src/mainboard/google/reef/variants/baseboard/memory.c index 50e93c7d19..364c0ee093 100644 --- a/src/mainboard/google/reef/variants/baseboard/memory.c +++ b/src/mainboard/google/reef/variants/baseboard/memory.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -137,12 +138,12 @@ static const struct lpddr4_cfg lp4cfg = { .swizzle_config = &baseboard_lpddr4_swizzle, }; -const struct lpddr4_cfg * __attribute__((weak)) variant_lpddr4_config(void) +const struct lpddr4_cfg * __weak variant_lpddr4_config(void) { return &lp4cfg; } -size_t __attribute__((weak)) variant_memory_sku(void) +size_t __weak variant_memory_sku(void) { gpio_t pads[] = { [3] = MEM_CONFIG3, [2] = MEM_CONFIG2, diff --git a/src/mainboard/google/reef/variants/baseboard/nhlt.c b/src/mainboard/google/reef/variants/baseboard/nhlt.c index b9357962df..188766954e 100644 --- a/src/mainboard/google/reef/variants/baseboard/nhlt.c +++ b/src/mainboard/google/reef/variants/baseboard/nhlt.c @@ -14,13 +14,14 @@ */ #include +#include #include #include #include #include #include -void __attribute__((weak)) variant_nhlt_init(struct nhlt *nhlt) +void __weak variant_nhlt_init(struct nhlt *nhlt) { /* 1-dmic configuration */ if (IS_ENABLED(CONFIG_NHLT_DMIC_1CH_16B) && diff --git a/src/mainboard/google/zoombini/memory.c b/src/mainboard/google/zoombini/memory.c index 115886e475..e1f525590f 100644 --- a/src/mainboard/google/zoombini/memory.c +++ b/src/mainboard/google/zoombini/memory.c @@ -15,6 +15,7 @@ #include #include +#include #include #include @@ -81,12 +82,12 @@ static const struct lpddr4_cfg baseboard_lpddr4_cfg = { .ect = 0, }; -const struct lpddr4_cfg *__attribute__((weak)) variant_lpddr4_config(void) +const struct lpddr4_cfg *__weak variant_lpddr4_config(void) { return &baseboard_lpddr4_cfg; } -size_t __attribute__((weak)) variant_memory_sku(void) +size_t __weak variant_memory_sku(void) { const gpio_t pads[] = { [3] = GPIO_MEM_CONFIG_3, [2] = GPIO_MEM_CONFIG_2, diff --git a/src/mainboard/google/zoombini/variants/baseboard/boardid.c b/src/mainboard/google/zoombini/variants/baseboard/boardid.c index 1cb084ac50..c8a5cf1073 100644 --- a/src/mainboard/google/zoombini/variants/baseboard/boardid.c +++ b/src/mainboard/google/zoombini/variants/baseboard/boardid.c @@ -14,9 +14,10 @@ */ #include +#include #include -uint8_t __attribute__((weak)) variant_board_id(void) +uint8_t __weak variant_board_id(void) { return google_chromeec_get_board_version(); } diff --git a/src/mainboard/google/zoombini/variants/baseboard/gpio.c b/src/mainboard/google/zoombini/variants/baseboard/gpio.c index 47894d020f..f8c84b44e1 100644 --- a/src/mainboard/google/zoombini/variants/baseboard/gpio.c +++ b/src/mainboard/google/zoombini/variants/baseboard/gpio.c @@ -15,6 +15,7 @@ #include #include +#include /* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { @@ -255,13 +256,13 @@ static const struct pad_config early_gpio_table[] = { INVERT), /* H1_PCH_INT_ODL */ }; -const struct pad_config *__attribute__((weak)) variant_gpio_table(size_t *num) +const struct pad_config *__weak variant_gpio_table(size_t *num) { *num = ARRAY_SIZE(gpio_table); return gpio_table; } -const struct pad_config *__attribute__((weak)) +const struct pad_config *__weak variant_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); @@ -272,7 +273,7 @@ static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), }; -const struct cros_gpio *__attribute__((weak)) variant_cros_gpios(size_t *num) +const struct cros_gpio *__weak variant_cros_gpios(size_t *num) { *num = ARRAY_SIZE(cros_gpios); return cros_gpios; diff --git a/src/mainboard/google/zoombini/variants/baseboard/nhlt.c b/src/mainboard/google/zoombini/variants/baseboard/nhlt.c index 0741b0d62f..ffaa6e5c96 100644 --- a/src/mainboard/google/zoombini/variants/baseboard/nhlt.c +++ b/src/mainboard/google/zoombini/variants/baseboard/nhlt.c @@ -14,11 +14,12 @@ */ #include +#include #include #include #include -void __attribute__((weak)) variant_nhlt_init(struct nhlt *nhlt) +void __weak variant_nhlt_init(struct nhlt *nhlt) { /* 1-dmic configuration */ if (IS_ENABLED(CONFIG_NHLT_DMIC_1CH_16B) && diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c index 44632e910d..fa9d0e9419 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c @@ -16,6 +16,7 @@ #include #include #include +#include /* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { @@ -297,13 +298,13 @@ static const struct pad_config early_gpio_table[] = { }; -const struct pad_config *__attribute__((weak)) variant_gpio_table(size_t *num) +const struct pad_config *__weak variant_gpio_table(size_t *num) { *num = ARRAY_SIZE(gpio_table); return gpio_table; } -const struct pad_config *__attribute__((weak)) +const struct pad_config *__weak variant_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); @@ -314,7 +315,7 @@ static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), }; -const struct cros_gpio * __attribute__((weak)) variant_cros_gpios(size_t *num) +const struct cros_gpio * __weak variant_cros_gpios(size_t *num) { *num = ARRAY_SIZE(cros_gpios); return cros_gpios; diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c index 9fb9be5184..6f3629e599 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c +++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c @@ -14,11 +14,12 @@ */ #include +#include #include #include #include -void __attribute__((weak)) variant_nhlt_init(struct nhlt *nhlt) +void __weak variant_nhlt_init(struct nhlt *nhlt) { /* 1-dmic configuration */ if (IS_ENABLED(CONFIG_NHLT_DMIC_1CH_16B) && diff --git a/src/mainboard/intel/galileo/vboot.c b/src/mainboard/intel/galileo/vboot.c index 469ec4e093..8242754a49 100644 --- a/src/mainboard/intel/galileo/vboot.c +++ b/src/mainboard/intel/galileo/vboot.c @@ -14,6 +14,7 @@ #include #include +#include #include #include #include @@ -74,7 +75,7 @@ void verstage_mainboard_init(void) reg_script_run(script); } -void __attribute__((weak)) vboot_platform_prepare_reboot(void) +void __weak vboot_platform_prepare_reboot(void) { const struct reg_script *script; diff --git a/src/mainboard/intel/glkrvp/chromeos.c b/src/mainboard/intel/glkrvp/chromeos.c index 05e8c6017a..76c83e1151 100644 --- a/src/mainboard/intel/glkrvp/chromeos.c +++ b/src/mainboard/intel/glkrvp/chromeos.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -55,7 +56,7 @@ void mainboard_chromeos_acpi_generate(void) chromeos_acpi_gpio_generate(gpios, num); } -int __attribute__((weak)) get_lid_switch(void) +int __weak get_lid_switch(void) { return -1; } diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c b/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c index 1f30f4ea63..530c06a993 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c @@ -14,9 +14,10 @@ */ #include +#include #include -uint8_t __attribute__((weak)) variant_board_id(void) +uint8_t __weak variant_board_id(void) { if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) return google_chromeec_get_board_version(); diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c index 96821d6704..7ff68a4826 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c @@ -16,6 +16,7 @@ #include #include #include +#include /* * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing' @@ -250,7 +251,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF_IOSSTATE(GPIO_209, DN_20K, DEEP, NF1, HIZCRx0),/*EMMC0_STROBE*/ }; -const struct pad_config * __attribute__((weak)) variant_gpio_table(size_t *num) +const struct pad_config * __weak variant_gpio_table(size_t *num) { *num = ARRAY_SIZE(gpio_table); return gpio_table; @@ -262,7 +263,7 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_178, UP_20K, DEEP, NF1), /* SMB_DATA */ }; -const struct pad_config * __attribute__((weak)) +const struct pad_config * __weak variant_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); @@ -277,7 +278,7 @@ static const struct pad_config sleep_gpio_table[] = { #endif }; -const struct pad_config * __attribute__((weak)) +const struct pad_config * __weak variant_sleep_gpio_table(size_t *num) { *num = ARRAY_SIZE(sleep_gpio_table); @@ -291,7 +292,7 @@ static const struct cros_gpio cros_gpios[] = { #endif }; -const struct cros_gpio * __attribute__((weak)) variant_cros_gpios(size_t *num) +const struct cros_gpio * __weak variant_cros_gpios(size_t *num) { *num = ARRAY_SIZE(cros_gpios); return cros_gpios; diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/memory.c b/src/mainboard/intel/glkrvp/variants/baseboard/memory.c index be00ecd577..56fac2a068 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/memory.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/memory.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -133,12 +134,12 @@ static const struct lpddr4_cfg lp4cfg = { .swizzle_config = &baseboard_lpddr4_swizzle, }; -const struct lpddr4_cfg * __attribute__((weak)) variant_lpddr4_config(void) +const struct lpddr4_cfg * __weak variant_lpddr4_config(void) { return &lp4cfg; } -size_t __attribute__((weak)) variant_memory_sku(void) +size_t __weak variant_memory_sku(void) { return 0; } diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c b/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c index 45cbc8f8c2..51da3addb5 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c @@ -14,11 +14,12 @@ */ #include +#include #include #include #include -void __attribute__((weak)) variant_nhlt_init(struct nhlt *nhlt) +void __weak variant_nhlt_init(struct nhlt *nhlt) { /* 1-dmic configuration */ if (IS_ENABLED(CONFIG_NHLT_DMIC_1CH_16B) && diff --git a/src/mainboard/siemens/mc_apl1/gpio.c b/src/mainboard/siemens/mc_apl1/gpio.c index b872b8d832..636d35682b 100644 --- a/src/mainboard/siemens/mc_apl1/gpio.c +++ b/src/mainboard/siemens/mc_apl1/gpio.c @@ -16,6 +16,7 @@ #include #include +#include #include "brd_gpio.h" /* @@ -363,7 +364,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(SVID0_CLK, UP_20K, DEEP, NF1), /* SVID0_CLK */ }; -const struct pad_config *__attribute__((weak)) brd_gpio_table(size_t *num) +const struct pad_config *__weak brd_gpio_table(size_t *num) { *num = ARRAY_SIZE(gpio_table); return gpio_table; @@ -406,7 +407,7 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(LPC_FRAMEB, UP_20K, DEEP, NF1), /* LPC_FRAME_N */ }; -const struct pad_config *__attribute__((weak)) +const struct pad_config *__weak brd_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index d9123172f7..a66917b697 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -25,7 +26,7 @@ #include #include -void __attribute__((weak)) OemPostParams(AMD_POST_PARAMS *PostParams) {} +void __weak OemPostParams(AMD_POST_PARAMS *PostParams) {} #define FILECODE UNASSIGNED_FILE_FILECODE diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index 05098b4304..70d311843b 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -141,18 +142,18 @@ int vboot_recovery_mode_enabled(void) return !!vboot_check_recovery_request(); } -int __attribute__((weak)) clear_recovery_mode_switch(void) +int __weak clear_recovery_mode_switch(void) { // Weak implementation. Nothing to do. return 0; } -void __attribute__((weak)) log_recovery_mode_switch(void) +void __weak log_recovery_mode_switch(void) { // Weak implementation. Nothing to do. } -int __attribute__((weak)) get_recovery_mode_retrain_switch(void) +int __weak get_recovery_mode_retrain_switch(void) { return 0; } @@ -175,12 +176,12 @@ int vboot_developer_mode_enabled(void) * TODO: Create flash protection interface which implements get_write_protect_state. * get_recovery_mode_switch should be implemented as default function. */ -int __attribute__((weak)) get_write_protect_state(void) +int __weak get_write_protect_state(void) { return 0; } -int __attribute__((weak)) get_recovery_mode_switch(void) +int __weak get_recovery_mode_switch(void) { return 0; } diff --git a/src/security/vboot/vboot_common.c b/src/security/vboot/vboot_common.c index 3ef90706ed..11320d218e 100644 --- a/src/security/vboot/vboot_common.c +++ b/src/security/vboot/vboot_common.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -101,7 +102,7 @@ int vboot_handoff_get_recovery_reason(void) } /* ============================ VBOOT REBOOT ============================== */ -void __attribute__((weak)) vboot_platform_prepare_reboot(void) +void __weak vboot_platform_prepare_reboot(void) { } diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index c76739ac51..9221a12ca2 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -95,21 +96,21 @@ int vb2ex_read_resource(struct vb2_context *ctx, } /* No-op stubs that can be overridden by SoCs with hardware crypto support. */ -__attribute__((weak)) +__weak int vb2ex_hwcrypto_digest_init(enum vb2_hash_algorithm hash_alg, uint32_t data_size) { return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED; } -__attribute__((weak)) +__weak int vb2ex_hwcrypto_digest_extend(const uint8_t *buf, uint32_t size) { BUG(); /* Should never get called if init() returned an error. */ return VB2_ERROR_UNKNOWN; } -__attribute__((weak)) +__weak int vb2ex_hwcrypto_digest_finalize(uint8_t *digest, uint32_t digest_size) { BUG(); /* Should never get called if init() returned an error. */ diff --git a/src/security/vboot/verstage.c b/src/security/vboot/verstage.c index c2441840d7..fd75250bb4 100644 --- a/src/security/vboot/verstage.c +++ b/src/security/vboot/verstage.c @@ -15,11 +15,12 @@ #include #include +#include #include #include #include -void __attribute__((weak)) verstage_mainboard_init(void) +void __weak verstage_mainboard_init(void) { /* Default empty implementation. */ } diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 36b669ba18..f72810fed9 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -28,8 +29,8 @@ #include #include -void __attribute__((weak)) SetMemParams(AMD_POST_PARAMS *PostParams) {} -void __attribute__((weak)) OemPostParams(AMD_POST_PARAMS *PostParams) {} +void __weak SetMemParams(AMD_POST_PARAMS *PostParams) {} +void __weak OemPostParams(AMD_POST_PARAMS *PostParams) {} /* ACPI table pointers returned by AmdInitLate */ static void *DmiTable; diff --git a/src/soc/amd/common/block/pi/def_callouts.c b/src/soc/amd/common/block/pi/def_callouts.c index fec1776da2..d419fcf6b6 100644 --- a/src/soc/amd/common/block/pi/def_callouts.c +++ b/src/soc/amd/common/block/pi/def_callouts.c @@ -15,6 +15,7 @@ */ #include +#include #include #include #include @@ -155,7 +156,7 @@ AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINTN FchData, return pVbiosImageInfo->ImagePtr ? AGESA_SUCCESS : AGESA_WARNING; } -AGESA_STATUS __attribute__((weak)) platform_PcieSlotResetControl(UINT32 Func, +AGESA_STATUS __weak platform_PcieSlotResetControl(UINT32 Func, UINTN Data, VOID *ConfigPtr) { printk(BIOS_WARNING, "Warning - AGESA callout: %s not supported\n", diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c index f30ed3cb01..c6eef1a32f 100644 --- a/src/soc/amd/stoneyridge/BiosCallOuts.c +++ b/src/soc/amd/stoneyridge/BiosCallOuts.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -28,7 +29,7 @@ #include "chip.h" #include -void __attribute__((weak)) platform_FchParams_reset( +void __weak platform_FchParams_reset( FCH_RESET_DATA_BLOCK *FchParams_reset) {} AGESA_STATUS agesa_fch_initreset(UINT32 Func, UINTN FchData, VOID *ConfigPtr) @@ -159,7 +160,7 @@ AGESA_STATUS agesa_HaltThisAp(UINT32 Func, UINTN Data, VOID *ConfigPtr) } /* Allow mainboards to fill the SPD buffer */ -__attribute__((weak)) int mainboard_read_spd(uint8_t spdAddress, char *buf, +__weak int mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 6c9726a02d..0e019f7a86 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -34,7 +35,7 @@ #include #include -void __attribute__((weak)) mainboard_romstage_entry(int s3_resume) +void __weak mainboard_romstage_entry(int s3_resume) { /* By default, don't do anything */ } diff --git a/src/soc/amd/stoneyridge/usb.c b/src/soc/amd/stoneyridge/usb.c index 0665976c89..e6d608e7dc 100644 --- a/src/soc/amd/stoneyridge/usb.c +++ b/src/soc/amd/stoneyridge/usb.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -42,13 +43,13 @@ static void set_usb_over_current(struct device *dev) } } -int __attribute__((weak)) mainboard_get_xhci_oc_map(uint16_t *map) +int __weak mainboard_get_xhci_oc_map(uint16_t *map) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); return -1; } -int __attribute__((weak)) mainboard_get_ehci_oc_map(uint16_t *map) +int __weak mainboard_get_ehci_oc_map(uint16_t *map) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); return -1; diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index c563f54438..e4084fe813 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -518,7 +519,7 @@ static void glk_fsp_silicon_init_params_cb( sizeof(silconfig->PcieRpSelectableDeemphasis)); } -void __attribute__((weak)) mainboard_devtree_update(struct device *dev) +void __weak mainboard_devtree_update(struct device *dev) { /* Override dev tree settings per board */ } diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index a8a0dd1d44..3d695ea52f 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -370,13 +371,13 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) car_set_var(fsp_version, version); } -__attribute__((weak)) +__weak void mainboard_memory_init_params(FSPM_UPD *mupd) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } -__attribute__((weak)) +__weak void mainboard_save_dimm_info(void) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c index 57ad0a7028..5da510486b 100644 --- a/src/soc/intel/baytrail/gpio.c +++ b/src/soc/intel/baytrail/gpio.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -234,7 +235,7 @@ void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap) } } -struct soc_gpio_config* __attribute__((weak)) mainboard_get_gpios(void) +struct soc_gpio_config* __weak mainboard_get_gpios(void) { printk(BIOS_DEBUG, "Default/empty GPIO config\n"); return NULL; diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index d16c4ff148..84ae0ee0d3 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -536,7 +537,7 @@ static const struct pci_driver southcluster __pci_driver = { .device = LPC_DEVID, }; -int __attribute__((weak)) mainboard_get_spi_config(struct spi_config *cfg) +int __weak mainboard_get_spi_config(struct spi_config *cfg) { return -1; } diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 9ac5574c6f..a672f7f5de 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -552,6 +553,6 @@ void southcluster_inject_dsdt(device_t device) } } -__attribute__((weak)) void acpi_create_serialio_ssdt(acpi_header_t *ssdt) +__weak void acpi_create_serialio_ssdt(acpi_header_t *ssdt) { } diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index 1f68e842c8..3da5763925 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -15,6 +15,7 @@ */ #include +#include #include #include #include @@ -81,7 +82,7 @@ static void enable_dev(device_t dev) } } -__attribute__((weak)) void board_silicon_USB2_override(SILICON_INIT_UPD *params) +__weak void board_silicon_USB2_override(SILICON_INIT_UPD *params) { } diff --git a/src/soc/intel/braswell/gpio.c b/src/soc/intel/braswell/gpio.c index a742f73119..23be45a1c1 100644 --- a/src/soc/intel/braswell/gpio.c +++ b/src/soc/intel/braswell/gpio.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ - +#include #include #include #include @@ -305,7 +305,7 @@ void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap) printk(BIOS_DEBUG, "Tri-state TDO and TMS\n"); } -__attribute__((weak)) struct soc_gpio_config *mainboard_get_gpios(void) +__weak struct soc_gpio_config *mainboard_get_gpios(void) { printk(BIOS_DEBUG, "Default/empty GPIO config\n"); return NULL; diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 6eb61c72af..05fa855dc6 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -21,6 +21,7 @@ #include #include #include "chip.h" +#include #include #include #include @@ -457,7 +458,7 @@ static const struct pci_driver southcluster __pci_driver = { .device = LPC_DEVID, }; -int __attribute__((weak)) mainboard_get_spi_config(struct spi_config *cfg) +int __weak mainboard_get_spi_config(struct spi_config *cfg) { printk(BIOS_SPEW, "%s/%s ( 0x%p )\n", __FILE__, __func__, (void *)cfg); diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 4a1e67dded..025855b47b 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -123,4 +124,4 @@ asmlinkage void romstage_after_car(void) ; } -void __attribute__((weak)) mainboard_pre_console_init(void) {} +void __weak mainboard_pre_console_init(void) {} diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 5fc3a55c26..49b98eecda 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -307,7 +308,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } /* Mainboard GPIO Configuration */ -__attribute__((weak)) void mainboard_silicon_init_params(FSP_S_CONFIG *params) +__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index c8cb927078..0459095261 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -194,7 +195,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mainboard_memory_init_params(mupd); } -__attribute__((weak)) void mainboard_memory_init_params(FSPM_UPD *mupd) +__weak void mainboard_memory_init_params(FSPM_UPD *mupd) { /* Do nothing */ } diff --git a/src/soc/intel/common/acpi_wake_source.c b/src/soc/intel/common/acpi_wake_source.c index 4166801e70..e0d8bfb8fc 100644 --- a/src/soc/intel/common/acpi_wake_source.c +++ b/src/soc/intel/common/acpi_wake_source.c @@ -16,13 +16,14 @@ #include #include #include +#include #include #include #include #include #include "acpi.h" -__attribute__((weak)) int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) +__weak int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) { return -1; } diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index bf4003d575..02ab886ac0 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -100,7 +101,7 @@ unsigned long acpi_fill_madt(unsigned long current) return acpi_madt_irq_overrides(current); } -__attribute__ ((weak)) void soc_fill_fadt(acpi_fadt_t *fadt) +__weak void soc_fill_fadt(acpi_fadt_t *fadt) { } @@ -173,7 +174,7 @@ unsigned long southbridge_write_acpi_tables(device_t device, return acpi_write_hpet(device, current, rsdp); } -__attribute__ ((weak)) +__weak uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, const struct chipset_power_state *ps) { @@ -219,7 +220,7 @@ static int acpi_fill_wake(uint32_t *pm1, uint32_t **gpe0) return GPE0_REG_MAX; } -__attribute__ ((weak)) void acpi_create_gnvs(struct global_nvs_t *gnvs) +__weak void acpi_create_gnvs(struct global_nvs_t *gnvs) { } @@ -401,7 +402,7 @@ void generate_t_state_entries(int core, int cores_per_package) acpigen_write_TSS_package(entries, soc_tss_table); } -__attribute__ ((weak)) void soc_power_states_generation(int core_id, +__weak void soc_power_states_generation(int core_id, int cores_per_package) { } diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 085a34052e..23f2fb0d47 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -30,12 +31,12 @@ static const void *microcode_patch; /* SoC override function */ -__attribute__((weak)) void soc_core_init(device_t dev) +__weak void soc_core_init(device_t dev) { /* no-op */ } -__attribute__((weak)) void soc_init_cpus(struct bus *cpu_bus) +__weak void soc_init_cpus(struct bus *cpu_bus) { /* no-op */ } diff --git a/src/soc/intel/common/block/ebda/ebda.c b/src/soc/intel/common/block/ebda/ebda.c index d16ad6e4c0..41c77a8f2c 100644 --- a/src/soc/intel/common/block/ebda/ebda.c +++ b/src/soc/intel/common/block/ebda/ebda.c @@ -14,6 +14,7 @@ */ #include +#include #include #include @@ -24,7 +25,7 @@ */ /* Fill up EBDA structure inside Mainboard directory */ -__attribute__((weak)) void create_mainboard_ebda(struct ebda_config *cfg) +__weak void create_mainboard_ebda(struct ebda_config *cfg) { /* no-op */ } diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index dcf8200250..ddea99fedb 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -21,7 +22,7 @@ #include /* SoC Overrides */ -__attribute__((weak)) void graphics_soc_init(struct device *dev) +__weak void graphics_soc_init(struct device *dev) { /* * User needs to implement SoC override in case wishes diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 175fad8b24..c7e1c6af0c 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -357,7 +358,7 @@ static int gspi_cs_change(const struct spi_slave *dev, enum cs_assert cs_assert) return 0; } -int __attribute__((weak)) gspi_get_soc_spi_cfg(unsigned int gspi_bus, +int __weak gspi_get_soc_spi_cfg(unsigned int gspi_bus, struct spi_cfg *cfg) { cfg->clk_phase = SPI_CLOCK_PHASE_FIRST; diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 079ecde624..c462d9daa0 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -24,13 +25,13 @@ /* SoC overrides */ /* Common weak definition, needs to be implemented in each soc LPC driver. */ -__attribute__((weak)) void lpc_soc_init(struct device *dev) +__weak void lpc_soc_init(struct device *dev) { /* no-op */ } /* Fill up LPC IO resource structure inside SoC directory */ -__attribute__((weak)) void pch_lpc_soc_fill_io_resources(struct device *dev) +__weak void pch_lpc_soc_fill_io_resources(struct device *dev) { /* no-op */ } diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index d3fef5567c..c8e8026171 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -25,7 +26,7 @@ /* SoC overrides */ /* Fill up PMC resource structure inside SoC directory */ -__attribute__((weak)) int pmc_soc_get_resources( +__weak int pmc_soc_get_resources( struct pmc_resource_config *cfg) { /* no-op */ @@ -33,7 +34,7 @@ __attribute__((weak)) int pmc_soc_get_resources( } /* SoC override PMC initialization */ -__attribute__((weak)) void pmc_soc_init(struct device *dev) +__weak void pmc_soc_init(struct device *dev) { /* no-op */ } diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index cf87d05d07..38d41960ad 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -75,7 +76,7 @@ static void print_num_status_bits(int num_bits, uint32_t status, } } -__attribute__ ((weak)) uint32_t soc_get_smi_status(uint32_t generic_sts) +__weak uint32_t soc_get_smi_status(uint32_t generic_sts) { return generic_sts; } @@ -84,7 +85,7 @@ __attribute__ ((weak)) uint32_t soc_get_smi_status(uint32_t generic_sts) * Set PMC register to know which state system should be after * power reapplied */ -__attribute__ ((weak)) void pmc_soc_restore_power_failure(void) +__weak void pmc_soc_restore_power_failure(void) { /* * SoC code should set PMC config register in order to set @@ -332,7 +333,7 @@ void pmc_clear_all_gpe_status(void) pmc_clear_gpi_gpe_status(); } -__attribute__ ((weak)) +__weak void soc_clear_pm_registers(uintptr_t pmc_bar) { } @@ -351,7 +352,7 @@ void pmc_clear_prsts(void) soc_clear_pm_registers(pmc_bar); } -__attribute__ ((weak)) +__weak int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state) { diff --git a/src/soc/intel/common/block/rtc/rtc.c b/src/soc/intel/common/block/rtc/rtc.c index 9e76768e65..cb97953557 100644 --- a/src/soc/intel/common/block/rtc/rtc.c +++ b/src/soc/intel/common/block/rtc/rtc.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -31,7 +32,7 @@ void enable_rtc_upper_bank(void) pcr_or32(PID_RTC, PCR_RTC_CONF, PCR_RTC_CONF_UCMOS_EN); } -__attribute__((weak)) int soc_get_rtc_failed(void) +__weak int soc_get_rtc_failed(void) { return 0; } diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index d492459dc8..d8ac2f3469 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -16,6 +16,7 @@ #include #include +#include #include #include #include @@ -40,18 +41,18 @@ static struct global_nvs_t *gnvs; /* SoC overrides. */ /* Specific SOC SMI handler during ramstage finalize phase */ -__attribute__((weak)) void smihandler_soc_at_finalize(void) +__weak void smihandler_soc_at_finalize(void) { return; } -__attribute__((weak)) int smihandler_soc_disable_busmaster(device_t dev) +__weak int smihandler_soc_disable_busmaster(device_t dev) { return 1; } /* SMI handlers that should be serviced in SCI mode too. */ -__attribute__((weak)) uint32_t smihandler_soc_get_sci_mask(void) +__weak uint32_t smihandler_soc_get_sci_mask(void) { return 0; /* No valid SCI mask for SMI handler */ } @@ -60,7 +61,7 @@ __attribute__((weak)) uint32_t smihandler_soc_get_sci_mask(void) * Needs to implement the mechanism to know if an illegal attempt * has been made to write to the BIOS area. */ -__attribute__((weak)) void smihandler_soc_check_illegal_access( +__weak void smihandler_soc_check_illegal_access( uint32_t tco_sts) { return; @@ -68,13 +69,13 @@ __attribute__((weak)) void smihandler_soc_check_illegal_access( /* Mainboard overrides. */ -__attribute__((weak)) void mainboard_smi_gpi_handler( +__weak void mainboard_smi_gpi_handler( const struct gpi_status *sts) { return; } -__attribute__((weak)) void mainboard_smi_espi_handler(void) +__weak void mainboard_smi_espi_handler(void) { return; } diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c index 49367e196b..9028952286 100644 --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -14,13 +14,14 @@ * GNU General Public License for more details. */ +#include #include #include #include #include #include -__attribute__((weak)) void soc_sram_init(struct device *dev) { /* no-op */ } +__weak void soc_sram_init(struct device *dev) { /* no-op */ } static void sram_read_resources(struct device *dev) { diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 25b47737b1..54646c9595 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -25,25 +26,25 @@ #include "systemagent_def.h" /* SoC override function */ -__attribute__((weak)) void soc_systemagent_init(struct device *dev) +__weak void soc_systemagent_init(struct device *dev) { /* no-op */ } -__attribute__((weak)) void soc_add_fixed_mmio_resources(struct device *dev, +__weak void soc_add_fixed_mmio_resources(struct device *dev, int *resource_cnt) { /* no-op */ } -__attribute__((weak)) int soc_get_uncore_prmmr_base_and_mask(uint64_t *base, +__weak int soc_get_uncore_prmmr_base_and_mask(uint64_t *base, uint64_t *mask) { /* return failure for this dummy API */ return -1; } -__attribute__((weak)) size_t soc_reserved_mmio_size(void) +__weak size_t soc_reserved_mmio_size(void) { return 0; } diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 9f26ef1718..cdbe56b519 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -45,7 +46,7 @@ void uart_common_init(device_t dev, uintptr_t baseaddr) uart_lpss_init(baseaddr); } -__attribute__((weak)) device_t pch_uart_get_debug_controller(void) +__weak device_t pch_uart_get_debug_controller(void) { /* * device_t can either be a pointer to struct device (e.g. ramstage) or @@ -78,12 +79,12 @@ bool uart_debug_controller_is_initialized(void) #if ENV_RAMSTAGE -__attribute__((weak)) void pch_uart_read_resources(struct device *dev) +__weak void pch_uart_read_resources(struct device *dev) { pci_dev_read_resources(dev); } -__attribute__((weak)) bool pch_uart_init_debug_controller_on_resume(void) +__weak bool pch_uart_init_debug_controller_on_resume(void) { /* By default, do not initialize controller. */ return false; diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c index 07093dfb5e..cc42f2c65c 100644 --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -15,13 +15,14 @@ */ #include +#include #include #include #include #include #include -__attribute__((weak)) void soc_xdci_init(struct device *dev) { /* no-op */ } +__weak void soc_xdci_init(struct device *dev) { /* no-op */ } /* Only allow xDCI controller in developer mode if VBOOT is enabled */ int xdci_can_enable(void) diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index e5a4f9b692..737c8cfe7e 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -14,13 +14,14 @@ * GNU General Public License for more details. */ +#include #include #include #include #include #include -__attribute__((weak)) void soc_xhci_init(struct device *dev) { /* no-op */ } +__weak void soc_xhci_init(struct device *dev) { /* no-op */ } static struct device_operations usb_xhci_ops = { .read_resources = &pci_dev_read_resources, diff --git a/src/soc/intel/common/vbt.c b/src/soc/intel/common/vbt.c index eba7d40430..3d8f2bffbe 100644 --- a/src/soc/intel/common/vbt.c +++ b/src/soc/intel/common/vbt.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -23,7 +24,7 @@ #define VBT_SIGNATURE 0x54425624 -__attribute__((weak)) +__weak const char *mainboard_vbt_filename(void) { return "vbt.bin"; diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 7386db34b8..1071ab52d3 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -329,4 +330,4 @@ void southcluster_inject_dsdt(device_t device) } } -__attribute__((weak)) void acpi_create_serialio_ssdt(acpi_header_t *ssdt) {} +__weak void acpi_create_serialio_ssdt(acpi_header_t *ssdt) {} diff --git a/src/soc/intel/denverton_ns/fiamux.c b/src/soc/intel/denverton_ns/fiamux.c index 36b8223d04..418ccfa322 100644 --- a/src/soc/intel/denverton_ns/fiamux.c +++ b/src/soc/intel/denverton_ns/fiamux.c @@ -15,6 +15,7 @@ * */ +#include #include #include @@ -140,7 +141,7 @@ BL_FIA_MUX_CONFIG_HOB *get_fiamux_hob_data(void) return fiamux_hob_data; } -__attribute__((weak)) size_t mainboard_get_hsio_config(BL_HSIO_INFORMATION **p_hsio_config) +__weak size_t mainboard_get_hsio_config(BL_HSIO_INFORMATION **p_hsio_config) { *p_hsio_config = NULL; return 0; diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index f675933046..b57ffc4c90 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -15,6 +15,7 @@ */ #include +#include #include #include #include @@ -28,7 +29,7 @@ #include #include -void __attribute__((weak)) mainboard_config_gpios(void) {} +void __weak mainboard_config_gpios(void) {} #define FSP_SMBIOS_MEMORY_INFO_GUID \ { \ @@ -279,7 +280,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg) } } -__attribute__((weak)) void mainboard_memory_init_params(FSPM_UPD *mupd) +__weak void mainboard_memory_init_params(FSPM_UPD *mupd) { /* Do nothing */ } diff --git a/src/soc/intel/fsp_baytrail/gpio.c b/src/soc/intel/fsp_baytrail/gpio.c index 862e42b9fe..72cf158b21 100644 --- a/src/soc/intel/fsp_baytrail/gpio.c +++ b/src/soc/intel/fsp_baytrail/gpio.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -245,7 +246,7 @@ void setup_soc_gpios(struct soc_gpio_config *config) } -struct soc_gpio_config* __attribute__((weak)) mainboard_get_gpios(void) +struct soc_gpio_config* __weak mainboard_get_gpios(void) { printk(BIOS_DEBUG, "Default/empty GPIO config\n"); return NULL; diff --git a/src/soc/intel/quark/gpio_i2c.c b/src/soc/intel/quark/gpio_i2c.c index d5543b803c..1a9c5ae3bd 100644 --- a/src/soc/intel/quark/gpio_i2c.c +++ b/src/soc/intel/quark/gpio_i2c.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -23,7 +24,7 @@ #include #include -__attribute__((weak)) void mainboard_gpio_i2c_init(device_t dev) +__weak void mainboard_gpio_i2c_init(device_t dev) { /* Initialize any of the GPIOs or I2C devices */ printk(BIOS_SPEW, "WEAK; mainboard_gpio_i2c_init\n"); diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 3d133f9266..914b9d51a3 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -707,7 +708,7 @@ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) return GPE0_REG_MAX; } -__attribute__((weak)) void acpi_mainboard_gnvs(global_nvs_t *gnvs) +__weak void acpi_mainboard_gnvs(global_nvs_t *gnvs) { } diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 054ed089dc..6e9181677e 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -346,7 +347,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } /* Mainboard GPIO Configuration */ -__attribute__((weak)) void mainboard_silicon_init_params(FSP_S_CONFIG *params) +__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 0b2d276a73..760dcc1e8c 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -295,7 +296,7 @@ void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, memory_cfg->SaGv = 0x02; } -__attribute__((weak)) void mainboard_memory_init_params(FSPM_UPD *mupd) +__weak void mainboard_memory_init_params(FSPM_UPD *mupd) { /* Do nothing */ } diff --git a/src/soc/nvidia/tegra210/bootblock.c b/src/soc/nvidia/tegra210/bootblock.c index 3d4e8812a6..4d1ddf5d60 100644 --- a/src/soc/nvidia/tegra210/bootblock.c +++ b/src/soc/nvidia/tegra210/bootblock.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -50,7 +51,7 @@ static void save_odmdata(void) } } -void __attribute__((weak)) bootblock_mainboard_early_init(void) +void __weak bootblock_mainboard_early_init(void) { /* Empty default implementation. */ } diff --git a/src/soc/nvidia/tegra210/funitcfg.c b/src/soc/nvidia/tegra210/funitcfg.c index a26da86bf6..e8d0c9754d 100644 --- a/src/soc/nvidia/tegra210/funitcfg.c +++ b/src/soc/nvidia/tegra210/funitcfg.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -175,7 +176,7 @@ void soc_configure_funits(const struct funit_cfg * const entries, size_t num) } } -void __attribute__((weak)) usb_setup_utmip(void *usb_base) +void __weak usb_setup_utmip(void *usb_base) { /* default empty implementation required if usb.c is not included */ printk(BIOS_ERR, "USB setup is not supported in current stage\n"); diff --git a/src/soc/nvidia/tegra210/romstage.c b/src/soc/nvidia/tegra210/romstage.c index 8fb839dbea..8958a6bb1e 100644 --- a/src/soc/nvidia/tegra210/romstage.c +++ b/src/soc/nvidia/tegra210/romstage.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -33,7 +34,7 @@ #include #include -void __attribute__((weak)) romstage_mainboard_init(void) +void __weak romstage_mainboard_init(void) { /* Default empty implementation. */ } diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c index 537c2c08b4..2045d52f2d 100644 --- a/src/southbridge/amd/sb700/sata.c +++ b/src/southbridge/amd/sb700/sata.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -66,7 +67,7 @@ static int sata_drive_detect(int portnum, uint16_t iobar) } /* This function can be overloaded in mainboard.c */ -void __attribute__((weak)) sb7xx_51xx_setup_sata_phys(struct device *dev) +void __weak sb7xx_51xx_setup_sata_phys(struct device *dev) { /* RPR7.6.1 Program the PHY Global Control to 0x2C00 */ pci_write_config16(dev, 0x86, 0x2c00); @@ -89,7 +90,7 @@ void __attribute__((weak)) sb7xx_51xx_setup_sata_phys(struct device *dev) } /* This function can be overloaded in mainboard.c */ -void __attribute__((weak)) sb7xx_51xx_setup_sata_port_indication(void *sata_bar5) +void __weak sb7xx_51xx_setup_sata_port_indication(void *sata_bar5) { uint32_t dword; diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 0e372d69da..17fae11db3 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -108,11 +109,11 @@ static void busmaster_disable_on_bus(int bus) } } -__attribute__((weak)) void southbridge_gate_memory_reset(void) +__weak void southbridge_gate_memory_reset(void) { } -__attribute__((weak)) void southbridge_smm_xhci_sleep(u8 slp_type) +__weak void southbridge_smm_xhci_sleep(u8 slp_type) { } diff --git a/src/southbridge/via/vt8237r/ide.c b/src/southbridge/via/vt8237r/ide.c index 457917174d..e500c2cbdf 100644 --- a/src/southbridge/via/vt8237r/ide.c +++ b/src/southbridge/via/vt8237r/ide.c @@ -15,6 +15,7 @@ /* Based on other VIA SB code. */ +#include #include #include #include @@ -25,7 +26,7 @@ /** * Cable type detect function, weak so it can be overloaded in mainboard.c */ -u32 __attribute__((weak)) vt8237_ide_80pin_detect(struct device *dev) +u32 __weak vt8237_ide_80pin_detect(struct device *dev) { struct southbridge_via_vt8237r_config *sb = (struct southbridge_via_vt8237r_config *)dev->chip_info; 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