From 6f925064152f2227b12ff68ef72289cf76be5d7c Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 17 May 2021 17:57:19 +0200 Subject: mb/asus/p8z77-m_pro: Transform into variant To preserve reproducibility, temporarily guard mainboard.c contents. Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8Z77-M PRO remains identical when not adding the .config file in it. Change-Id: I05e272690ca78f6b9e22b1db1c36cb9e5a7afe3c Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/54411 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- MAINTAINERS | 6 +- src/mainboard/asus/p8z77-m_pro/Kconfig | 31 ---- src/mainboard/asus/p8z77-m_pro/Kconfig.name | 4 - src/mainboard/asus/p8z77-m_pro/Makefile.inc | 8 - src/mainboard/asus/p8z77-m_pro/acpi/ec.asl | 1 - src/mainboard/asus/p8z77-m_pro/acpi/platform.asl | 10 -- src/mainboard/asus/p8z77-m_pro/acpi/superio.asl | 3 - src/mainboard/asus/p8z77-m_pro/board_info.txt | 7 - src/mainboard/asus/p8z77-m_pro/cmos.default | 11 -- src/mainboard/asus/p8z77-m_pro/cmos.layout | 150 ----------------- src/mainboard/asus/p8z77-m_pro/data.vbt | Bin 3902 -> 0 bytes src/mainboard/asus/p8z77-m_pro/devicetree.cb | 93 ----------- src/mainboard/asus/p8z77-m_pro/dsdt.asl | 26 --- src/mainboard/asus/p8z77-m_pro/early_init.c | 156 ------------------ src/mainboard/asus/p8z77-m_pro/gma-mainboard.ads | 17 -- src/mainboard/asus/p8z77-m_pro/gpio.c | 182 --------------------- src/mainboard/asus/p8z77-m_pro/hda_verb.c | 36 ---- src/mainboard/asus/p8z77-m_pro/mainboard.c | 16 -- src/mainboard/asus/p8z77-series/Kconfig | 2 + src/mainboard/asus/p8z77-series/Kconfig.name | 10 ++ src/mainboard/asus/p8z77-series/mainboard.c | 21 +++ .../variants/p8z77-m_pro/board_info.txt | 7 + .../p8z77-series/variants/p8z77-m_pro/cmos.default | 11 ++ .../p8z77-series/variants/p8z77-m_pro/cmos.layout | 150 +++++++++++++++++ .../p8z77-series/variants/p8z77-m_pro/data.vbt | Bin 0 -> 3902 bytes .../variants/p8z77-m_pro/devicetree.cb | 93 +++++++++++ .../p8z77-series/variants/p8z77-m_pro/early_init.c | 156 ++++++++++++++++++ .../variants/p8z77-m_pro/gma-mainboard.ads | 17 ++ .../asus/p8z77-series/variants/p8z77-m_pro/gpio.c | 182 +++++++++++++++++++++ .../p8z77-series/variants/p8z77-m_pro/hda_verb.c | 36 ++++ 30 files changed, 686 insertions(+), 756 deletions(-) delete mode 100644 src/mainboard/asus/p8z77-m_pro/Kconfig delete mode 100644 src/mainboard/asus/p8z77-m_pro/Kconfig.name delete mode 100644 src/mainboard/asus/p8z77-m_pro/Makefile.inc delete mode 100644 src/mainboard/asus/p8z77-m_pro/acpi/ec.asl delete mode 100644 src/mainboard/asus/p8z77-m_pro/acpi/platform.asl delete mode 100644 src/mainboard/asus/p8z77-m_pro/acpi/superio.asl delete mode 100644 src/mainboard/asus/p8z77-m_pro/board_info.txt delete mode 100644 src/mainboard/asus/p8z77-m_pro/cmos.default delete mode 100644 src/mainboard/asus/p8z77-m_pro/cmos.layout delete mode 100644 src/mainboard/asus/p8z77-m_pro/data.vbt delete mode 100644 src/mainboard/asus/p8z77-m_pro/devicetree.cb delete mode 100644 src/mainboard/asus/p8z77-m_pro/dsdt.asl delete mode 100644 src/mainboard/asus/p8z77-m_pro/early_init.c delete mode 100644 src/mainboard/asus/p8z77-m_pro/gma-mainboard.ads delete mode 100644 src/mainboard/asus/p8z77-m_pro/gpio.c delete mode 100644 src/mainboard/asus/p8z77-m_pro/hda_verb.c delete mode 100644 src/mainboard/asus/p8z77-m_pro/mainboard.c create mode 100644 src/mainboard/asus/p8z77-series/mainboard.c create mode 100644 src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/board_info.txt create mode 100644 src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/cmos.default create mode 100644 src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/cmos.layout create mode 100644 src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/data.vbt create mode 100644 src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/devicetree.cb create mode 100644 src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/early_init.c create mode 100644 src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/gma-mainboard.ads create mode 100644 src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/gpio.c create mode 100644 src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/hda_verb.c diff --git a/MAINTAINERS b/MAINTAINERS index f6ee6dd3b4..74f1854489 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -196,13 +196,9 @@ M: Angel Pons S: Maintained F: src/mainboard/asus/p5qpl-am/ -ASUS P8Z77-M PRO MAINBOARD -M: Vlado Cibic -S: Maintained -F: src/mainboard/asus/p8z77-m_pro/ - ASUS P8Z77 SERIES MAINBOARDS M: Angel Pons +M: Vlado Cibic S: Maintained F: src/mainboard/asus/p8z77-series/ diff --git a/src/mainboard/asus/p8z77-m_pro/Kconfig b/src/mainboard/asus/p8z77-m_pro/Kconfig deleted file mode 100644 index 19a1fe1e5e..0000000000 --- a/src/mainboard/asus/p8z77-m_pro/Kconfig +++ /dev/null @@ -1,31 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -if BOARD_ASUS_P8Z77_M_PRO - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select BOARD_ROMSIZE_KB_8192 - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select INTEL_INT15 - select NORTHBRIDGE_INTEL_SANDYBRIDGE - select SERIRQ_CONTINUOUS_MODE - select SOUTHBRIDGE_INTEL_C216 - select MAINBOARD_HAS_LPC_TPM - select MAINBOARD_HAS_TPM1 - select HAVE_OPTION_TABLE - select HAVE_CMOS_DEFAULT - select MAINBOARD_HAS_LIBGFXINIT - select INTEL_GMA_HAVE_VBT - select SUPERIO_NUVOTON_NCT6779D - select DRIVERS_ASMEDIA_ASPM_BLACKLIST # for ASM1061 eSATA - -config MAINBOARD_DIR - string - default "asus/p8z77-m_pro" - -config MAINBOARD_PART_NUMBER - string - default "P8Z77-M PRO" - -endif # BOARD_ASUS_P8Z77_M_PRO diff --git a/src/mainboard/asus/p8z77-m_pro/Kconfig.name b/src/mainboard/asus/p8z77-m_pro/Kconfig.name deleted file mode 100644 index 372ec4a7da..0000000000 --- a/src/mainboard/asus/p8z77-m_pro/Kconfig.name +++ /dev/null @@ -1,4 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -config BOARD_ASUS_P8Z77_M_PRO - bool "P8Z77-M PRO" diff --git a/src/mainboard/asus/p8z77-m_pro/Makefile.inc b/src/mainboard/asus/p8z77-m_pro/Makefile.inc deleted file mode 100644 index 26b20d7ece..0000000000 --- a/src/mainboard/asus/p8z77-m_pro/Makefile.inc +++ /dev/null @@ -1,8 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-or-later - -bootblock-y += gpio.c -romstage-y += gpio.c - -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -bootblock-y += early_init.c -romstage-y += early_init.c diff --git a/src/mainboard/asus/p8z77-m_pro/acpi/ec.asl b/src/mainboard/asus/p8z77-m_pro/acpi/ec.asl deleted file mode 100644 index 8b13789179..0000000000 --- a/src/mainboard/asus/p8z77-m_pro/acpi/ec.asl +++ /dev/null @@ -1 +0,0 @@ - diff --git a/src/mainboard/asus/p8z77-m_pro/acpi/platform.asl b/src/mainboard/asus/p8z77-m_pro/acpi/platform.asl deleted file mode 100644 index 90cf05bf75..0000000000 --- a/src/mainboard/asus/p8z77-m_pro/acpi/platform.asl +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -Method(_PTS,1) -{ -} - -Method(_WAK,1) -{ - Return(Package(){0,0}) -} diff --git a/src/mainboard/asus/p8z77-m_pro/acpi/superio.asl b/src/mainboard/asus/p8z77-m_pro/acpi/superio.asl deleted file mode 100644 index ee2eabeb75..0000000000 --- a/src/mainboard/asus/p8z77-m_pro/acpi/superio.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include diff --git a/src/mainboard/asus/p8z77-m_pro/board_info.txt b/src/mainboard/asus/p8z77-m_pro/board_info.txt deleted file mode 100644 index 66e6f0d6f9..0000000000 --- a/src/mainboard/asus/p8z77-m_pro/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Category: desktop -Board URL: https://www.asus.com/Motherboards/P8Z77M_PRO/ -ROM package: DIP-8 -ROM protocol: SPI -ROM socketed: y -Flashrom support: y -Release year: 2013 diff --git a/src/mainboard/asus/p8z77-m_pro/cmos.default b/src/mainboard/asus/p8z77-m_pro/cmos.default deleted file mode 100644 index 6811b0b076..0000000000 --- a/src/mainboard/asus/p8z77-m_pro/cmos.default +++ /dev/null @@ -1,11 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -boot_option=Fallback -debug_level=Debug -gfx_uma_size=224M -nmi=Enable -sata_mode=AHCI -#usb3_xxxx options are only used with MRC blob, ignored else -usb3_mode=Enable -usb3_drv=Enable -usb3_streams=Enable diff --git a/src/mainboard/asus/p8z77-m_pro/cmos.layout b/src/mainboard/asus/p8z77-m_pro/cmos.layout deleted file mode 100644 index 3d717b444d..0000000000 --- a/src/mainboard/asus/p8z77-m_pro/cmos.layout +++ /dev/null @@ -1,150 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -# ----------------------------------------------------------------- -entries - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 3 boot_option -388 4 h 0 reboot_counter - -# ----------------------------------------------------------------- -# coreboot config options: console -395 4 e 4 debug_level -#400 8 r 0 reserved for century byte - -# ----------------------------------------------------------------- -# coreboot config options: southbridge - -# Non Maskable Interrupt(NMI) support, which is an interrupt that may -# occur on a RAM or unrecoverable error. -408 1 e 1 nmi - -409 2 e 5 power_on_after_fail -411 1 e 6 sata_mode - -# ----------------------------------------------------------------- -# coreboot config options: northbridge - -# gfx_uma_size -# Quantity of shared video memory the IGP can use -# -416 5 e 7 gfx_uma_size - -# ----------------------------------------------------------------- -# coreboot config options: usb3 - -# usb3_mode -# Controls how the motherboard's USB3 ports act at boot time -421 2 e 8 usb3_mode - -# usb3_drv -# Load (or not) pre-OS xHCI USB3 BIOS driver -# -423 1 e 1 usb3_drv - -# usb3_streams -# Streams can provide more speed (as they can use 64Kb packets), -# but they might cause incompatibilities with some devices. -# -424 1 e 1 usb3_streams - -# ----------------------------------------------------------------- -# Sandy/Ivy Bridge MRC Scrambler Seed values -# note: MUST NOT be covered by checksum! -464 32 r 0 mrc_scrambler_seed -496 32 r 0 mrc_scrambler_seed_s3 -528 16 r 0 mrc_scrambler_seed_chk - -# ----------------------------------------------------------------- -# coreboot config options: check sums -544 16 h 0 check_sum - -# ----------------------------------------------------------------- - -enumerations -#ID value text - -# Generic on/off enum -1 0 Disable -1 1 Enable - -# boot_option -3 0 Fallback -3 1 Normal - -# debug_level -4 0 Emergency -4 1 Alert -4 2 Critical -4 3 Error -4 4 Warning -4 5 Notice -4 6 Info -4 7 Debug -4 8 Spew - -# power_on_after_fail -5 0 Disable -5 1 Enable -5 2 Keep - -# sata_mode -6 0 AHCI -6 1 Compatible - -# gfx_uma_size (Intel IGP Video RAM size) -7 0 32M -7 1 64M -7 2 96M -7 3 128M -7 4 160M -7 5 192M -7 6 224M -7 7 256M -7 8 288M -7 9 320M -7 10 352M -7 11 384M -7 12 416M -7 13 448M -7 14 480M -7 15 512M -7 16 544M -7 17 576M -7 18 608M -7 19 640M -7 20 672M -7 21 704M -7 22 736M -7 23 768M -7 24 800M -7 25 832M -7 26 864M -7 27 896M -7 28 928M -7 29 960M -7 30 992M - -# usb3_mode -# Disable = Use the port always as USB 2.0 for compatibility -# Enable = Use the port always as USB 3.0 for speed -# Auto = Initialize the port as USB 2.0, until the OS loads -# xHCI USB 3.0 driver -# SmartAuto = Same as Auto but, if the OS loads the xHCI USB 3.0 driver -# and the computer is reset, keep the USB 3.0 mode. -# -8 0 Disable -8 1 Enable -8 2 Auto -8 3 SmartAuto - -# ----------------------------------------------------------------- -# -# -checksums - -checksum 392 431 544 diff --git a/src/mainboard/asus/p8z77-m_pro/data.vbt b/src/mainboard/asus/p8z77-m_pro/data.vbt deleted file mode 100644 index 34679b36a9..0000000000 Binary files a/src/mainboard/asus/p8z77-m_pro/data.vbt and /dev/null differ diff --git a/src/mainboard/asus/p8z77-m_pro/devicetree.cb b/src/mainboard/asus/p8z77-m_pro/devicetree.cb deleted file mode 100644 index a915499502..0000000000 --- a/src/mainboard/asus/p8z77-m_pro/devicetree.cb +++ /dev/null @@ -1,93 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -chip northbridge/intel/sandybridge - device cpu_cluster 0 on - chip cpu/intel/model_206ax - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" - device lapic 0 on end - device lapic 0xacac off end - end - end - device domain 0 on - subsystemid 0x1043 0x84ca inherit - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Internal graphics VGA controller - - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" - register "gen1_dec" = "0x000c0291" - register "gen4_dec" = "0x0000ff29" - register "pcie_port_coalesce" = "1" - register "sata_interface_speed_support" = "0x3" # 0x3=SATAIII - register "sata_port_map" = "0x3f" # Enable the six SATA ports - register "spi_lvscc" = "0x2005" - register "spi_uvscc" = "0x2005" - register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" - register "xhci_switchable_ports" = "0x0000000f" # the 4 ports - - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI 2 - device pci 1b.0 on end # High Definition Audio controller - device pci 1c.0 on end # PCIe Port 1 PCIEX_16_3 - device pci 1c.1 on end # PCIe Port 2 RTL8111F - device pci 1c.2 off end # PCIe Port 3 unused - device pci 1c.3 off end # PCIe Port 4 unused - device pci 1c.4 off end # PCIe Port 5 unused - device pci 1c.5 on end # PCIe Port 6 ASM1042 USB3 - device pci 1c.6 on end # PCIe Port 7 ASM1061 eSATA - device pci 1c.7 off end # PCIe Port 8 unused - device pci 1d.0 on end # USB2 EHCI 1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge - chip superio/nuvoton/nct6779d - device pnp 2e.1 off end # Parallel - device pnp 2e.2 off end # UART A - device pnp 2e.3 on # UART B, IR - io 0x60 = 0x2f8 # COM2 address - end - device pnp 2e.5 on # PS2 KBC - io 0x60 = 0x0060 # KBC1 base - io 0x62 = 0x0064 # KBC2 base - irq 0x70 = 1 # Keyboard IRQ - irq 0x72 = 12 # Mouse IRQ - - # KBC 12Mhz/A20 speed/sw KBRST - drq 0xf0 = 0x82 - end - device pnp 2e.6 off end # CIR - device pnp 2e.7 on end # GPIOs 6-8 - device pnp 2e.8 off end # WDT1 GPIO 0-1 - device pnp 2e.9 off end # GPIO 1-8 - device pnp 2e.a on # ACPI - drq 0xe4 = 0x10 # Enable 3VSBS to power RAM on S3 - drq 0xe7 = 0x10 # 0.5s S3 delay for compatibility - end - device pnp 2e.b off end # HWM, LED - device pnp 2e.d off end # WDT1 - device pnp 2e.e off end # CIR wake-up - device pnp 2e.f on # GPIO PP/OD - drq 0xe6 = 0x7f # GP7 PP - end - device pnp 2e.14 on end # Port 80 UART - device pnp 2e.16 off end # Deep sleep - end - chip drivers/pc80/tpm - device pnp 4e.0 on end # TPM - end - end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal - end - end -end diff --git a/src/mainboard/asus/p8z77-m_pro/dsdt.asl b/src/mainboard/asus/p8z77-m_pro/dsdt.asl deleted file mode 100644 index 19a528f694..0000000000 --- a/src/mainboard/asus/p8z77-m_pro/dsdt.asl +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -DefinitionBlock( - "dsdt.aml", - "DSDT", - ACPI_DSDT_REV_2, - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20141018 /* OEM revision */ -) -{ - #include - #include "acpi/platform.asl" - #include - #include - - #include - #include - - Device (\_SB.PCI0) - { - #include - #include - } -} diff --git a/src/mainboard/asus/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8z77-m_pro/early_init.c deleted file mode 100644 index 78ad877715..0000000000 --- a/src/mainboard/asus/p8z77-m_pro/early_init.c +++ /dev/null @@ -1,156 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -#include -#include -#include -#include - -#include -#include - -#include - -#include -#include -#include - -#define GLOBAL_DEV PNP_DEV(0x2e, 0) -#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP2) - -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* {enable, current, oc_pin} */ - { 1, 2, 0 }, /* Port 0: USB3 front internal header, top */ - { 1, 2, 0 }, /* Port 1: USB3 front internal header, bottom */ - { 1, 2, 1 }, /* Port 2: USB3 rear, ETH top */ - { 1, 2, 1 }, /* Port 3: USB3 rear, ETH bottom */ - { 1, 2, 2 }, /* Port 4: USB2 rear, PS2 top */ - { 1, 2, 2 }, /* Port 5: USB2 rear, PS2 bottom */ - { 1, 2, 3 }, /* Port 6: USB2 internal header USB78, top */ - { 1, 2, 3 }, /* Port 7: USB2 internal header USB78, bottom */ - { 1, 2, 4 }, /* Port 8: USB2 internal header USB910, top */ - { 1, 2, 4 }, /* Port 9: USB2 internal header USB910, bottom */ - { 1, 2, 6 }, /* Port 10: USB2 internal header USB1112, top */ - { 1, 2, 5 }, /* Port 11: USB2 internal header USB1112, bottom */ - { 0, 2, 5 }, /* Port 12: Unused. Asus proprietary DEBUG_PORT ??? */ - { 0, 2, 6 } /* Port 13: Unused. Asus proprietary DEBUG_PORT ??? */ -}; - -void bootblock_mainboard_early_init(void) -{ - /* Setup COM/UART */ - nuvoton_pnp_enter_conf_state(GLOBAL_DEV); - - /* TODO / FIXME: Setup Multifuncion/SIO pins for COM */ - - pnp_set_logical_device(SERIAL_DEV); - nuvoton_pnp_exit_conf_state(GLOBAL_DEV); - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x51, id_only); - read_spd(&spd[2], 0x52, id_only); - read_spd(&spd[3], 0x53, id_only); -} - -int mainboard_should_reset_usb(int s3resume) -{ - return !s3resume; -} - -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ - /* - * USB3 mode: - * 0 = Disable: work always as USB 2.0(ehci) - * 1 = Enable: work always as USB 3.0(xhci) - * 2 = Auto: work as USB2.0(ehci) until OS loads USB3 xhci driver - * 3 = Smart Auto : same than Auto, but if OS loads USB3 driver - * and reboots, it will keep the USB3.0 speed - */ - unsigned int usb3_mode = get_uint_option("usb3_mode", 1); - usb3_mode &= 0x3; /* ensure it's 0/1/2/3 only */ - - /* Load USB3 pre-OS xHCI driver */ - unsigned int usb3_drv = get_uint_option("usb3_drv", 1); - usb3_drv &= 0x1; /* ensure it's 0/1 only */ - - /* Use USB3 xHCI streams */ - unsigned int usb3_streams = get_uint_option("usb3_streams", 1); - usb3_streams &= 0x1; /* ensure it's 0/1 only */ - - struct pei_data pd = { - .pei_version = PEI_VERSION, - .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, - .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, - .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 1, /* 0=Mobile, 1=Desktop/Server */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* SMBus mul 2 */ - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 0, /* Asus 2203 BIOS shows XUECA016, but no EC */ - .gbe_enable = 0, /* Board uses no Intel GbE but a RTL8111F */ - .max_ddr3_freq = 1600, /* 1333=Sandy; 1600=Ivy */ - .usb_port_config = { - /* {enabled, oc_pin, cable len 0x0080=<8inches/20cm} */ - { 1, 0, 0x0080 }, /* USB3 front internal header */ - { 1, 0, 0x0080 }, /* USB3 front internal header */ - { 1, 1, 0x0080 }, /* USB3 ETH top connector */ - { 1, 1, 0x0080 }, /* USB3 ETH botton connector */ - { 1, 2, 0x0080 }, /* USB2 PS2 top connector */ - { 1, 2, 0x0080 }, /* USB2 PS2 botton connector */ - { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */ - { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */ - { 1, 4, 0x0080 }, /* USB2 internal header (USB910) */ - { 1, 4, 0x0080 }, /* USB2 internal header (USB910) */ - { 1, 6, 0x0080 }, /* USB2 internal header (USB1112) */ - { 1, 5, 0x0080 }, /* USB2 internal header (USB1112) */ - { 0, 5, 0x0080 }, /* Unused. Asus DEBUG_PORT ??? */ - { 0, 6, 0x0080 } /* Unused. Asus DEBUG_PORT ??? */ - }, - .usb3 = { - /* 0=Disable; 1=Enable (start at USB3 speed) - * 2=Auto (start as USB2 speed until OS loads) - * 3=Smart Auto (like Auto but keep speed on reboot) - */ - usb3_mode, - /* 4 bit switch mask. 0=not switchable, 1=switchable - * Means once it's loaded the OS, it can swap ports - * from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf - */ - 0xf, - usb3_drv, /* 1=Load xHCI pre-OS drv */ - /* 0=Don't use xHCI streams for better compatibility - * 1=use xHCI streams for better speed - */ - usb3_streams - }, - /* ASUS P8Z77-M PRO manual says 1.35v DIMMs are supported */ - .ddr3lv_support = 1, - /* PCIe 3.0 support. As we use Ivy Bridge, let's enable it, - * but might cause some system instability ! - */ - .pcie_init = 1, - /* Command Rate. 0=Auto; 1=1N; 2=2N. - * Leave it always at Auto for compatibility & stability - */ - .nmode = 0, - /* DDR refresh rate. 0=Auto based on DRAM's temperature; - * 1=Normal rate for speed; 2=Double rate for stability - */ - .ddr_refresh_rate_config = 0 - }; - - /* copy the data to output PEI */ - *pei_data = pd; -} diff --git a/src/mainboard/asus/p8z77-m_pro/gma-mainboard.ads b/src/mainboard/asus/p8z77-m_pro/gma-mainboard.ads deleted file mode 100644 index 09d2e1556a..0000000000 --- a/src/mainboard/asus/p8z77-m_pro/gma-mainboard.ads +++ /dev/null @@ -1,17 +0,0 @@ --- SPDX-License-Identifier: GPL-2.0-or-later - -with HW.GFX.GMA; -with HW.GFX.GMA.Display_Probing; - -use HW.GFX.GMA; -use HW.GFX.GMA.Display_Probing; - -private package GMA.Mainboard is - - ports : constant Port_List := - (HDMI1, -- DVI-D port on rear - HDMI3, -- real HDMI port on rear - Analog, -- VGA port on rear - others => Disabled); - -end GMA.Mainboard; diff --git a/src/mainboard/asus/p8z77-m_pro/gpio.c b/src/mainboard/asus/p8z77-m_pro/gpio.c deleted file mode 100644 index 2455bd6711..0000000000 --- a/src/mainboard/asus/p8z77-m_pro/gpio.c +++ /dev/null @@ -1,182 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -static const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_GPIO, - .gpio1 = GPIO_MODE_GPIO, - .gpio2 = GPIO_MODE_NATIVE, - .gpio3 = GPIO_MODE_NATIVE, - .gpio4 = GPIO_MODE_NATIVE, - .gpio5 = GPIO_MODE_NATIVE, - .gpio6 = GPIO_MODE_GPIO, - .gpio7 = GPIO_MODE_GPIO, - .gpio8 = GPIO_MODE_GPIO, - .gpio9 = GPIO_MODE_NATIVE, - .gpio10 = GPIO_MODE_NATIVE, - .gpio11 = GPIO_MODE_NATIVE, - .gpio12 = GPIO_MODE_GPIO, - .gpio13 = GPIO_MODE_GPIO, - .gpio14 = GPIO_MODE_NATIVE, - .gpio15 = GPIO_MODE_GPIO, - .gpio16 = GPIO_MODE_GPIO, - .gpio17 = GPIO_MODE_GPIO, - .gpio18 = GPIO_MODE_NATIVE, - .gpio19 = GPIO_MODE_NATIVE, - .gpio20 = GPIO_MODE_NATIVE, - .gpio21 = GPIO_MODE_GPIO, - .gpio22 = GPIO_MODE_NATIVE, - .gpio23 = GPIO_MODE_NATIVE, - .gpio24 = GPIO_MODE_GPIO, - .gpio25 = GPIO_MODE_NATIVE, - .gpio26 = GPIO_MODE_NATIVE, - .gpio27 = GPIO_MODE_GPIO, - .gpio28 = GPIO_MODE_GPIO, - .gpio29 = GPIO_MODE_GPIO, - .gpio30 = GPIO_MODE_NATIVE, - .gpio31 = GPIO_MODE_GPIO, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio0 = GPIO_DIR_INPUT, - .gpio1 = GPIO_DIR_INPUT, - .gpio6 = GPIO_DIR_INPUT, - .gpio7 = GPIO_DIR_INPUT, - .gpio8 = GPIO_DIR_OUTPUT, - .gpio12 = GPIO_DIR_OUTPUT, - .gpio13 = GPIO_DIR_INPUT, - .gpio15 = GPIO_DIR_OUTPUT, - .gpio16 = GPIO_DIR_INPUT, - .gpio17 = GPIO_DIR_INPUT, - .gpio21 = GPIO_DIR_INPUT, - .gpio24 = GPIO_DIR_OUTPUT, - .gpio27 = GPIO_DIR_INPUT, - .gpio28 = GPIO_DIR_OUTPUT, - .gpio29 = GPIO_DIR_OUTPUT, - .gpio31 = GPIO_DIR_OUTPUT, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio8 = GPIO_LEVEL_HIGH, - .gpio12 = GPIO_LEVEL_LOW, - .gpio15 = GPIO_LEVEL_LOW, - .gpio24 = GPIO_LEVEL_LOW, - .gpio28 = GPIO_LEVEL_LOW, - .gpio29 = GPIO_LEVEL_HIGH, - .gpio31 = GPIO_LEVEL_HIGH, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_reset = { -}; - -static const struct pch_gpio_set1 pch_gpio_set1_invert = { - .gpio1 = GPIO_INVERT, - .gpio13 = GPIO_INVERT, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_blink = { -}; - -static const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio32 = GPIO_MODE_GPIO, - .gpio33 = GPIO_MODE_GPIO, - .gpio34 = GPIO_MODE_GPIO, - .gpio35 = GPIO_MODE_NATIVE, - .gpio36 = GPIO_MODE_NATIVE, - .gpio37 = GPIO_MODE_NATIVE, - .gpio38 = GPIO_MODE_NATIVE, - .gpio39 = GPIO_MODE_NATIVE, - .gpio40 = GPIO_MODE_NATIVE, - .gpio41 = GPIO_MODE_NATIVE, - .gpio42 = GPIO_MODE_NATIVE, - .gpio43 = GPIO_MODE_NATIVE, - .gpio44 = GPIO_MODE_NATIVE, - .gpio45 = GPIO_MODE_GPIO, - .gpio46 = GPIO_MODE_GPIO, - .gpio47 = GPIO_MODE_NATIVE, - .gpio48 = GPIO_MODE_NATIVE, - .gpio49 = GPIO_MODE_GPIO, - .gpio50 = GPIO_MODE_NATIVE, - .gpio51 = GPIO_MODE_NATIVE, - .gpio52 = GPIO_MODE_NATIVE, - .gpio53 = GPIO_MODE_NATIVE, - .gpio54 = GPIO_MODE_NATIVE, - .gpio55 = GPIO_MODE_NATIVE, - .gpio56 = GPIO_MODE_NATIVE, - .gpio57 = GPIO_MODE_GPIO, - .gpio58 = GPIO_MODE_NATIVE, - .gpio59 = GPIO_MODE_NATIVE, - .gpio60 = GPIO_MODE_NATIVE, - .gpio61 = GPIO_MODE_NATIVE, - .gpio62 = GPIO_MODE_NATIVE, - .gpio63 = GPIO_MODE_NATIVE, -}; - -static const struct pch_gpio_set2 pch_gpio_set2_direction = { - .gpio32 = GPIO_DIR_OUTPUT, - .gpio33 = GPIO_DIR_OUTPUT, - .gpio34 = GPIO_DIR_INPUT, - .gpio45 = GPIO_DIR_INPUT, - .gpio46 = GPIO_DIR_INPUT, - .gpio49 = GPIO_DIR_INPUT, - .gpio57 = GPIO_DIR_OUTPUT, -}; - -static const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio32 = GPIO_LEVEL_HIGH, - .gpio33 = GPIO_LEVEL_HIGH, - .gpio57 = GPIO_LEVEL_LOW, -}; - -static const struct pch_gpio_set2 pch_gpio_set2_reset = { -}; - -static const struct pch_gpio_set3 pch_gpio_set3_mode = { - .gpio64 = GPIO_MODE_NATIVE, - .gpio65 = GPIO_MODE_NATIVE, - .gpio66 = GPIO_MODE_NATIVE, - .gpio67 = GPIO_MODE_NATIVE, - .gpio68 = GPIO_MODE_GPIO, - .gpio69 = GPIO_MODE_GPIO, - .gpio70 = GPIO_MODE_NATIVE, - .gpio71 = GPIO_MODE_NATIVE, - .gpio72 = GPIO_MODE_GPIO, - .gpio73 = GPIO_MODE_NATIVE, - .gpio74 = GPIO_MODE_NATIVE, - .gpio75 = GPIO_MODE_NATIVE, -}; - -static const struct pch_gpio_set3 pch_gpio_set3_direction = { - .gpio68 = GPIO_DIR_INPUT, - .gpio69 = GPIO_DIR_INPUT, - .gpio72 = GPIO_DIR_INPUT, -}; - -static const struct pch_gpio_set3 pch_gpio_set3_level = { -}; - -static const struct pch_gpio_set3 pch_gpio_set3_reset = { -}; - -const struct pch_gpio_map mainboard_gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - .blink = &pch_gpio_set1_blink, - .invert = &pch_gpio_set1_invert, - .reset = &pch_gpio_set1_reset, - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - .reset = &pch_gpio_set2_reset, - }, - .set3 = { - .mode = &pch_gpio_set3_mode, - .direction = &pch_gpio_set3_direction, - .level = &pch_gpio_set3_level, - .reset = &pch_gpio_set3_reset, - }, -}; diff --git a/src/mainboard/asus/p8z77-m_pro/hda_verb.c b/src/mainboard/asus/p8z77-m_pro/hda_verb.c deleted file mode 100644 index a4a7a3e091..0000000000 --- a/src/mainboard/asus/p8z77-m_pro/hda_verb.c +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -const u32 cim_verb_data[] = { - 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ - 0x10438436, /* Subsystem ID */ - 15, /* Number of 4 dword sets */ - AZALIA_SUBVENDOR(0, 0x10438436), - AZALIA_PIN_CFG(0, 0x11, 0x99430140), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), - AZALIA_PIN_CFG(0, 0x14, 0x01014010), - AZALIA_PIN_CFG(0, 0x15, 0x01011012), - AZALIA_PIN_CFG(0, 0x16, 0x01016011), - AZALIA_PIN_CFG(0, 0x17, 0x01012014), - AZALIA_PIN_CFG(0, 0x18, 0x01a19850), - AZALIA_PIN_CFG(0, 0x19, 0x02a19c60), - AZALIA_PIN_CFG(0, 0x1a, 0x0181305f), - AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1d, 0x4005e601), - AZALIA_PIN_CFG(0, 0x1e, 0x01456130), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), - - 0x80862806, /* Codec Vendor / Device ID: Intel */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of 4 dword sets */ - AZALIA_SUBVENDOR(3, 0x80860101), - AZALIA_PIN_CFG(3, 0x05, 0x58560010), - AZALIA_PIN_CFG(3, 0x06, 0x58560020), - AZALIA_PIN_CFG(3, 0x07, 0x18560030), -}; - -const u32 pc_beep_verbs[0] = {}; - -AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/p8z77-m_pro/mainboard.c b/src/mainboard/asus/p8z77-m_pro/mainboard.c deleted file mode 100644 index ac992f6ffb..0000000000 --- a/src/mainboard/asus/p8z77-m_pro/mainboard.c +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -static void mainboard_enable(struct device *dev) -{ - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, - GMA_INT15_PANEL_FIT_DEFAULT, - GMA_INT15_BOOT_DISPLAY_DEFAULT, - 0); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable -}; diff --git a/src/mainboard/asus/p8z77-series/Kconfig b/src/mainboard/asus/p8z77-series/Kconfig index 99c76a0418..8927ff5fd5 100644 --- a/src/mainboard/asus/p8z77-series/Kconfig +++ b/src/mainboard/asus/p8z77-series/Kconfig @@ -20,10 +20,12 @@ config MAINBOARD_DIR config VARIANT_DIR string + default "p8z77-m_pro" if BOARD_ASUS_P8Z77_M_PRO default "p8z77-v_lx2" if BOARD_ASUS_P8Z77_V_LX2 config MAINBOARD_PART_NUMBER string + default "P8Z77-M PRO" if BOARD_ASUS_P8Z77_M_PRO default "P8Z77-V LX2" if BOARD_ASUS_P8Z77_V_LX2 config DEVICETREE diff --git a/src/mainboard/asus/p8z77-series/Kconfig.name b/src/mainboard/asus/p8z77-series/Kconfig.name index 4ab8943dcf..44dae8127a 100644 --- a/src/mainboard/asus/p8z77-series/Kconfig.name +++ b/src/mainboard/asus/p8z77-series/Kconfig.name @@ -1,3 +1,13 @@ +config BOARD_ASUS_P8Z77_M_PRO + bool "P8Z77-M PRO" + select BOARD_ASUS_P8Z77_SERIES + select BOARD_ROMSIZE_KB_8192 + select DRIVERS_ASMEDIA_ASPM_BLACKLIST # for ASM1061 eSATA + select INTEL_INT15 + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + select SUPERIO_NUVOTON_NCT6779D + config BOARD_ASUS_P8Z77_V_LX2 bool "P8Z77-V LX2" select BOARD_ASUS_P8Z77_SERIES diff --git a/src/mainboard/asus/p8z77-series/mainboard.c b/src/mainboard/asus/p8z77-series/mainboard.c new file mode 100644 index 0000000000..bc45baf8a7 --- /dev/null +++ b/src/mainboard/asus/p8z77-series/mainboard.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: remove */ +#if CONFIG(INTEL_INT15) + +#include +#include + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, + 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable +}; + +#endif diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/board_info.txt b/src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/board_info.txt new file mode 100644 index 0000000000..66e6f0d6f9 --- /dev/null +++ b/src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/Motherboards/P8Z77M_PRO/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2013 diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/cmos.default b/src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/cmos.default new file mode 100644 index 0000000000..6811b0b076 --- /dev/null +++ b/src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/cmos.default @@ -0,0 +1,11 @@ +## SPDX-License-Identifier: GPL-2.0-only + +boot_option=Fallback +debug_level=Debug +gfx_uma_size=224M +nmi=Enable +sata_mode=AHCI +#usb3_xxxx options are only used with MRC blob, ignored else +usb3_mode=Enable +usb3_drv=Enable +usb3_streams=Enable diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/cmos.layout b/src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/cmos.layout new file mode 100644 index 0000000000..3d717b444d --- /dev/null +++ b/src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/cmos.layout @@ -0,0 +1,150 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 3 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 4 debug_level +#400 8 r 0 reserved for century byte + +# ----------------------------------------------------------------- +# coreboot config options: southbridge + +# Non Maskable Interrupt(NMI) support, which is an interrupt that may +# occur on a RAM or unrecoverable error. +408 1 e 1 nmi + +409 2 e 5 power_on_after_fail +411 1 e 6 sata_mode + +# ----------------------------------------------------------------- +# coreboot config options: northbridge + +# gfx_uma_size +# Quantity of shared video memory the IGP can use +# +416 5 e 7 gfx_uma_size + +# ----------------------------------------------------------------- +# coreboot config options: usb3 + +# usb3_mode +# Controls how the motherboard's USB3 ports act at boot time +421 2 e 8 usb3_mode + +# usb3_drv +# Load (or not) pre-OS xHCI USB3 BIOS driver +# +423 1 e 1 usb3_drv + +# usb3_streams +# Streams can provide more speed (as they can use 64Kb packets), +# but they might cause incompatibilities with some devices. +# +424 1 e 1 usb3_streams + +# ----------------------------------------------------------------- +# Sandy/Ivy Bridge MRC Scrambler Seed values +# note: MUST NOT be covered by checksum! +464 32 r 0 mrc_scrambler_seed +496 32 r 0 mrc_scrambler_seed_s3 +528 16 r 0 mrc_scrambler_seed_chk + +# ----------------------------------------------------------------- +# coreboot config options: check sums +544 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations +#ID value text + +# Generic on/off enum +1 0 Disable +1 1 Enable + +# boot_option +3 0 Fallback +3 1 Normal + +# debug_level +4 0 Emergency +4 1 Alert +4 2 Critical +4 3 Error +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew + +# power_on_after_fail +5 0 Disable +5 1 Enable +5 2 Keep + +# sata_mode +6 0 AHCI +6 1 Compatible + +# gfx_uma_size (Intel IGP Video RAM size) +7 0 32M +7 1 64M +7 2 96M +7 3 128M +7 4 160M +7 5 192M +7 6 224M +7 7 256M +7 8 288M +7 9 320M +7 10 352M +7 11 384M +7 12 416M +7 13 448M +7 14 480M +7 15 512M +7 16 544M +7 17 576M +7 18 608M +7 19 640M +7 20 672M +7 21 704M +7 22 736M +7 23 768M +7 24 800M +7 25 832M +7 26 864M +7 27 896M +7 28 928M +7 29 960M +7 30 992M + +# usb3_mode +# Disable = Use the port always as USB 2.0 for compatibility +# Enable = Use the port always as USB 3.0 for speed +# Auto = Initialize the port as USB 2.0, until the OS loads +# xHCI USB 3.0 driver +# SmartAuto = Same as Auto but, if the OS loads the xHCI USB 3.0 driver +# and the computer is reset, keep the USB 3.0 mode. +# +8 0 Disable +8 1 Enable +8 2 Auto +8 3 SmartAuto + +# ----------------------------------------------------------------- +# +# +checksums + +checksum 392 431 544 diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/data.vbt b/src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/data.vbt new file mode 100644 index 0000000000..34679b36a9 Binary files /dev/null and b/src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/data.vbt differ diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/devicetree.cb b/src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/devicetree.cb new file mode 100644 index 0000000000..a915499502 --- /dev/null +++ b/src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/devicetree.cb @@ -0,0 +1,93 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/sandybridge + device cpu_cluster 0 on + chip cpu/intel/model_206ax + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" + device lapic 0 on end + device lapic 0xacac off end + end + end + device domain 0 on + subsystemid 0x1043 0x84ca inherit + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics VGA controller + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "gen1_dec" = "0x000c0291" + register "gen4_dec" = "0x0000ff29" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" # 0x3=SATAIII + register "sata_port_map" = "0x3f" # Enable the six SATA ports + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" # the 4 ports + + device pci 14.0 on end # USB 3.0 Controller + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI 2 + device pci 1b.0 on end # High Definition Audio controller + device pci 1c.0 on end # PCIe Port 1 PCIEX_16_3 + device pci 1c.1 on end # PCIe Port 2 RTL8111F + device pci 1c.2 off end # PCIe Port 3 unused + device pci 1c.3 off end # PCIe Port 4 unused + device pci 1c.4 off end # PCIe Port 5 unused + device pci 1c.5 on end # PCIe Port 6 ASM1042 USB3 + device pci 1c.6 on end # PCIe Port 7 ASM1061 eSATA + device pci 1c.7 off end # PCIe Port 8 unused + device pci 1d.0 on end # USB2 EHCI 1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6779d + device pnp 2e.1 off end # Parallel + device pnp 2e.2 off end # UART A + device pnp 2e.3 on # UART B, IR + io 0x60 = 0x2f8 # COM2 address + end + device pnp 2e.5 on # PS2 KBC + io 0x60 = 0x0060 # KBC1 base + io 0x62 = 0x0064 # KBC2 base + irq 0x70 = 1 # Keyboard IRQ + irq 0x72 = 12 # Mouse IRQ + + # KBC 12Mhz/A20 speed/sw KBRST + drq 0xf0 = 0x82 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 on end # GPIOs 6-8 + device pnp 2e.8 off end # WDT1 GPIO 0-1 + device pnp 2e.9 off end # GPIO 1-8 + device pnp 2e.a on # ACPI + drq 0xe4 = 0x10 # Enable 3VSBS to power RAM on S3 + drq 0xe7 = 0x10 # 0.5s S3 delay for compatibility + end + device pnp 2e.b off end # HWM, LED + device pnp 2e.d off end # WDT1 + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f on # GPIO PP/OD + drq 0xe6 = 0x7f # GP7 PP + end + device pnp 2e.14 on end # Port 80 UART + device pnp 2e.16 off end # Deep sleep + end + chip drivers/pc80/tpm + device pnp 4e.0 on end # TPM + end + end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/early_init.c new file mode 100644 index 0000000000..78ad877715 --- /dev/null +++ b/src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/early_init.c @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include +#include + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP2) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* {enable, current, oc_pin} */ + { 1, 2, 0 }, /* Port 0: USB3 front internal header, top */ + { 1, 2, 0 }, /* Port 1: USB3 front internal header, bottom */ + { 1, 2, 1 }, /* Port 2: USB3 rear, ETH top */ + { 1, 2, 1 }, /* Port 3: USB3 rear, ETH bottom */ + { 1, 2, 2 }, /* Port 4: USB2 rear, PS2 top */ + { 1, 2, 2 }, /* Port 5: USB2 rear, PS2 bottom */ + { 1, 2, 3 }, /* Port 6: USB2 internal header USB78, top */ + { 1, 2, 3 }, /* Port 7: USB2 internal header USB78, bottom */ + { 1, 2, 4 }, /* Port 8: USB2 internal header USB910, top */ + { 1, 2, 4 }, /* Port 9: USB2 internal header USB910, bottom */ + { 1, 2, 6 }, /* Port 10: USB2 internal header USB1112, top */ + { 1, 2, 5 }, /* Port 11: USB2 internal header USB1112, bottom */ + { 0, 2, 5 }, /* Port 12: Unused. Asus proprietary DEBUG_PORT ??? */ + { 0, 2, 6 } /* Port 13: Unused. Asus proprietary DEBUG_PORT ??? */ +}; + +void bootblock_mainboard_early_init(void) +{ + /* Setup COM/UART */ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* TODO / FIXME: Setup Multifuncion/SIO pins for COM */ + + pnp_set_logical_device(SERIAL_DEV); + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} + +int mainboard_should_reset_usb(int s3resume) +{ + return !s3resume; +} + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + /* + * USB3 mode: + * 0 = Disable: work always as USB 2.0(ehci) + * 1 = Enable: work always as USB 3.0(xhci) + * 2 = Auto: work as USB2.0(ehci) until OS loads USB3 xhci driver + * 3 = Smart Auto : same than Auto, but if OS loads USB3 driver + * and reboots, it will keep the USB3.0 speed + */ + unsigned int usb3_mode = get_uint_option("usb3_mode", 1); + usb3_mode &= 0x3; /* ensure it's 0/1/2/3 only */ + + /* Load USB3 pre-OS xHCI driver */ + unsigned int usb3_drv = get_uint_option("usb3_drv", 1); + usb3_drv &= 0x1; /* ensure it's 0/1 only */ + + /* Use USB3 xHCI streams */ + unsigned int usb3_streams = get_uint_option("usb3_streams", 1); + usb3_streams &= 0x1; /* ensure it's 0/1 only */ + + struct pei_data pd = { + .pei_version = PEI_VERSION, + .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, + .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, + .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = CONFIG_HPET_ADDRESS, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .thermalbase = 0xfed08000, + .system_type = 1, /* 0=Mobile, 1=Desktop/Server */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* SMBus mul 2 */ + .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, + .ec_present = 0, /* Asus 2203 BIOS shows XUECA016, but no EC */ + .gbe_enable = 0, /* Board uses no Intel GbE but a RTL8111F */ + .max_ddr3_freq = 1600, /* 1333=Sandy; 1600=Ivy */ + .usb_port_config = { + /* {enabled, oc_pin, cable len 0x0080=<8inches/20cm} */ + { 1, 0, 0x0080 }, /* USB3 front internal header */ + { 1, 0, 0x0080 }, /* USB3 front internal header */ + { 1, 1, 0x0080 }, /* USB3 ETH top connector */ + { 1, 1, 0x0080 }, /* USB3 ETH botton connector */ + { 1, 2, 0x0080 }, /* USB2 PS2 top connector */ + { 1, 2, 0x0080 }, /* USB2 PS2 botton connector */ + { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */ + { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */ + { 1, 4, 0x0080 }, /* USB2 internal header (USB910) */ + { 1, 4, 0x0080 }, /* USB2 internal header (USB910) */ + { 1, 6, 0x0080 }, /* USB2 internal header (USB1112) */ + { 1, 5, 0x0080 }, /* USB2 internal header (USB1112) */ + { 0, 5, 0x0080 }, /* Unused. Asus DEBUG_PORT ??? */ + { 0, 6, 0x0080 } /* Unused. Asus DEBUG_PORT ??? */ + }, + .usb3 = { + /* 0=Disable; 1=Enable (start at USB3 speed) + * 2=Auto (start as USB2 speed until OS loads) + * 3=Smart Auto (like Auto but keep speed on reboot) + */ + usb3_mode, + /* 4 bit switch mask. 0=not switchable, 1=switchable + * Means once it's loaded the OS, it can swap ports + * from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf + */ + 0xf, + usb3_drv, /* 1=Load xHCI pre-OS drv */ + /* 0=Don't use xHCI streams for better compatibility + * 1=use xHCI streams for better speed + */ + usb3_streams + }, + /* ASUS P8Z77-M PRO manual says 1.35v DIMMs are supported */ + .ddr3lv_support = 1, + /* PCIe 3.0 support. As we use Ivy Bridge, let's enable it, + * but might cause some system instability ! + */ + .pcie_init = 1, + /* Command Rate. 0=Auto; 1=1N; 2=2N. + * Leave it always at Auto for compatibility & stability + */ + .nmode = 0, + /* DDR refresh rate. 0=Auto based on DRAM's temperature; + * 1=Normal rate for speed; 2=Double rate for stability + */ + .ddr_refresh_rate_config = 0 + }; + + /* copy the data to output PEI */ + *pei_data = pd; +} diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/gma-mainboard.ads b/src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/gma-mainboard.ads new file mode 100644 index 0000000000..09d2e1556a --- /dev/null +++ b/src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, -- DVI-D port on rear + HDMI3, -- real HDMI port on rear + Analog, -- VGA port on rear + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/gpio.c b/src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/gpio.c new file mode 100644 index 0000000000..2455bd6711 --- /dev/null +++ b/src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/gpio.c @@ -0,0 +1,182 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/hda_verb.c b/src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/hda_verb.c new file mode 100644 index 0000000000..a4a7a3e091 --- /dev/null +++ b/src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/hda_verb.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ + 0x10438436, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x10438436), + AZALIA_PIN_CFG(0, 0x11, 0x99430140), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x01012014), + AZALIA_PIN_CFG(0, 0x18, 0x01a19850), + AZALIA_PIN_CFG(0, 0x19, 0x02a19c60), + AZALIA_PIN_CFG(0, 0x1a, 0x0181305f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4005e601), + AZALIA_PIN_CFG(0, 0x1e, 0x01456130), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x58560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; -- cgit v1.2.3