From 739c50340431f34a8e4fbc0736ebb11e161fdf0f Mon Sep 17 00:00:00 2001 From: Jes Klinke Date: Fri, 31 Jul 2020 09:48:35 -0700 Subject: soc/intel/common/block/gspi: Recalculate BAR after resource allocation The base address of the memory mapped I/O registers should not be cached across resource allocation. This CL will evict the cached value upon exiting the BS_DEV_RESOURCES stage. Change-Id: I81f2b5bfadbf1aaa3b38cca2bcc44ce521666821 Signed-off-by: jbk@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/44084 Reviewed-by: Karthik Ramasubramanian Reviewed-by: Furquan Shaikh Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/gspi/gspi.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 599ab7e52c..836371372a 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -257,6 +258,17 @@ static uintptr_t gspi_get_bus_base_addr(unsigned int gspi_bus) return gspi_base[gspi_bus]; } +/* + * PCI resource allocation will likely change the base address of the mapped + * I/O registers. Clearing the cached value after the allocation step will + * cause it to be recomputed by gspi_calc_base_addr() on next access. + */ +static void gspi_clear_cached_base(void *unused) +{ + memset(gspi_base, 0, sizeof(gspi_base)); +} +BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, gspi_clear_cached_base, NULL); + /* Parameters for GSPI controller operation. */ struct gspi_ctrlr_params { uintptr_t mmio_base; -- cgit v1.2.3