From 75d8d8da47a3cc759d7395f5b0ef91ba13a59e51 Mon Sep 17 00:00:00 2001
From: Li Cheng Sooi
Date: Fri, 24 Feb 2017 02:52:13 +0800
Subject: soc/intel/skylake: Add GPIO macros for IOxAPIC and SCI
Add two GPIO macros:
1. PAD_CFG_GPI_APIC_EDGE allows a pin to be route to the
APIC with input assuming the events are edge triggered.
2. PAD_CFG_GPI_ACPI_SCI_LEVEL to route the general purpose
input to SCI assuming the events are level triggered.
Change-Id: I944a9abac66b7780b2336148ae8c7fa3a8410f3f
Signed-off-by: Rahul Kumar Gupta
Reviewed-on: https://review.coreboot.org/18533
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin
Reviewed-by: Paul Menzel
---
src/soc/intel/skylake/include/soc/gpio.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h
index 75d8abe63a..c0e37db91e 100644
--- a/src/soc/intel/skylake/include/soc/gpio.h
+++ b/src/soc/intel/skylake/include/soc/gpio.h
@@ -152,12 +152,23 @@ void gpio_configure_pads(const struct pad_config *cfgs, size_t num);
_DW0_VALS(rst_, RAW, NO, LEVEL, NO, YES, YES, NO, NO, NO, GPIO, NO, \
YES))
+/* General purpose input passed through to IOxAPIC. This assumes edge
+ * triggered events. */
+#define PAD_CFG_GPI_APIC_EDGE(pad_, term_, rst_) \
+ _PAD_CFG(pad_, term_, \
+ _DW0_VALS(rst_, RAW, NO, EDGE, NO, NO, YES, NO, NO, NO, GPIO, NO, YES))
+
/* General purpose input routed to SCI. This assumes edge triggered events. */
#define PAD_CFG_GPI_ACPI_SCI(pad_, term_, rst_, inv_) \
_PAD_CFG_ATTRS(pad_, term_, \
_DW0_VALS(rst_, RAW, NO, EDGE, NO, inv_, \
NO, YES, NO, NO, GPIO, NO, YES), PAD_FIELD(HOSTSW, ACPI))
+#define PAD_CFG_GPI_ACPI_SCI_LEVEL(pad_, term_, rst_, inv_) \
+ _PAD_CFG_ATTRS(pad_, term_, \
+ _DW0_VALS(rst_, RAW, NO, LEVEL, NO, inv_, \
+ NO, YES, NO, NO, GPIO, NO, YES), PAD_FIELD(HOSTSW, ACPI))
+
/* General purpose input routed to SMI. This assumes edge triggered events. */
#define PAD_CFG_GPI_ACPI_SMI(pad_, term_, rst_, inv_) \
_PAD_CFG_ATTRS(pad_, term_, \
--
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