From 77a30af41cd252bb72883f30e57683b1d11a8c36 Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Thu, 10 May 2018 09:54:08 +0800
Subject: soc/intel/skylake: check DPTF_TSR1_ACTIVE_AC* in _ACx methods

Because thermal table is not included the values of DPTF_TSR1_ACTIVE_AC
from internal nami/vayne thermal team. Add conditional compilation
in _ACx methods if DPTF_ENABLE_FAN_CONTROL is defined in the dptf.asl.

BUG=b:72974136
TEST=Match the result.

Change-Id: I4b593118ca460a59aa49786cb99df417d135112a
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
---
 src/soc/intel/skylake/acpi/dptf/thermal.asl | 33 +++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/src/soc/intel/skylake/acpi/dptf/thermal.asl b/src/soc/intel/skylake/acpi/dptf/thermal.asl
index 829039242c..f99b7c3fc7 100644
--- a/src/soc/intel/skylake/acpi/dptf/thermal.asl
+++ b/src/soc/intel/skylake/acpi/dptf/thermal.asl
@@ -263,6 +263,39 @@ Device (TSR1)
 	{
 		\_SB.PCI0.LPCB.EC0.PATD (TMPI)
 	}
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+#ifdef DPTF_TSR1_ACTIVE_AC0
+        Method (_AC0)
+        {
+                Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC0))
+        }
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC1
+        Method (_AC1)
+        {
+                Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC1))
+        }
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC2
+        Method (_AC2)
+        {
+                Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC2))
+        }
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC3
+        Method (_AC3)
+        {
+                Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC3))
+        }
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC4
+        Method (_AC4)
+        {
+                Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC4))
+        }
+#endif
+#endif
 }
 #endif
 
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