From 8104effa0dc25bac4693e8d76c1e10039dd47bad Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sun, 5 Jul 2020 19:13:15 +0530 Subject: mainboard/intel/tglrvp: Remove unused PrmrrSize chip config MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Refer to commit 7736bfc TEST=Able to build and boot TGLRVP. Change-Id: Ie9a97cee7d7793077167db3a642dcbca45b09427 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/43139 Reviewed-by: Angel Pons Reviewed-by: Michael Niewöhner Reviewed-by: Wonkyu Kim Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 2 -- src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 2 -- src/soc/intel/tigerlake/chip.h | 10 ---------- src/soc/intel/tigerlake/romstage/fsp_params.c | 3 ++- 4 files changed, 2 insertions(+), 15 deletions(-) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 401077229a..1396d3ac82 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -38,8 +38,6 @@ chip soc/intel/tigerlake # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" - register "PrmrrSize" = "0x10000000" - register "PcieRpEnable[2]" = "1" register "PcieRpEnable[3]" = "1" register "PcieRpEnable[8]" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index d095ff39c9..c3e41a2644 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -38,8 +38,6 @@ chip soc/intel/tigerlake # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" - register "PrmrrSize" = "0x10000000" - register "PcieRpEnable[2]" = "1" register "PcieRpEnable[3]" = "1" register "PcieRpEnable[8]" = "1" diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 26ed64e0f1..fee7105245 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -192,16 +192,6 @@ struct soc_intel_tigerlake_config { /* Enable C6 DRAM */ uint8_t enable_c6dram; - /* - * PRMRR size setting with below options - * Disable: 0x0 - * 32MB: 0x2000000 - * 64MB: 0x4000000 - * 128 MB: 0x8000000 - * 256 MB: 0x10000000 - * 512 MB: 0x20000000 - */ - uint32_t PrmrrSize; uint8_t PmTimerDisabled; /* * SerialIO device mode selection: diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 1f60b52656..662ca06928 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -63,7 +64,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq, sizeof(config->PcieClkSrcClkReq)); - m_cfg->PrmrrSize = config->PrmrrSize; + m_cfg->PrmrrSize = get_prmrr_size(); m_cfg->EnableC6Dram = config->enable_c6dram; /* Disable BIOS Guard */ m_cfg->BiosGuard = 0; -- cgit v1.2.3