From 817d7542f708215c4128b6cdc39ca7d7e1256b26 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Thu, 8 Jul 2010 00:37:23 +0000 Subject: get rid of even more fam10 and k8 warnings. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5659 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/cpu/amd/dualcore/dualcore_id.c | 2 +- src/cpu/amd/model_10xxx/init_cpus.c | 15 ++++++------- src/cpu/amd/model_fxx/init_cpus.c | 2 +- src/cpu/amd/quadcore/quadcore_id.c | 4 +++- src/include/cpu/amd/multicore.h | 2 ++ src/northbridge/amd/amdfam10/amdfam10.h | 10 ++++++++- src/northbridge/amd/amdfam10/raminit_amdmct.c | 2 -- .../amd/amdfam10/raminit_sysinfo_in_ram.c | 3 ++- src/northbridge/amd/amdfam10/setup_resource_map.c | 10 ++++----- src/northbridge/amd/amdmct/mct/mct.h | 1 - src/northbridge/amd/amdmct/mct/mct_fd.c | 25 ---------------------- src/northbridge/amd/amdmct/mct/mctpro_d.c | 3 ++- src/northbridge/amd/amdmct/mct/mctsrc1p.c | 5 ++--- src/northbridge/amd/amdmct/wrappers/mcti_d.c | 2 ++ src/southbridge/amd/amd8111/amd8111.h | 4 ++++ src/southbridge/amd/amd8111/amd8111_early_ctrl.c | 3 ++- 16 files changed, 40 insertions(+), 53 deletions(-) delete mode 100644 src/northbridge/amd/amdmct/mct/mct_fd.c diff --git a/src/cpu/amd/dualcore/dualcore_id.c b/src/cpu/amd/dualcore/dualcore_id.c index 9a1a9c53d4..0eb461f4f8 100644 --- a/src/cpu/amd/dualcore/dualcore_id.c +++ b/src/cpu/amd/dualcore/dualcore_id.c @@ -14,7 +14,7 @@ unsigned int read_nb_cfg_54(void) return ( ( msr.hi >> (54-32)) & 1); } -static inline unsigned get_initial_apicid(void) +u32 get_initial_apicid(void) { return ((cpuid_ebx(1) >> 24) & 0xf); } diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index 15e9ed4f85..52fbdd2658 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -252,12 +252,11 @@ void wait_all_other_cores_started(u32 bsp_apicid) printk(BIOS_DEBUG, "\n"); } -static void allow_all_aps_stop(u32 bsp_apicid) +void allow_all_aps_stop(u32 bsp_apicid) { /* Called by the BSP to indicate AP can stop */ - /* FIXME Do APs use this? - Looks like wait_till_sysinfo_in_ram is used instead. */ + /* FIXME Do APs use this? */ // allow aps to stop use 6 bits for state lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | 0x14); @@ -395,15 +394,11 @@ static u32 init_cpus(u32 cpu_init_detectedx) } #endif - /* AP is ready, Wait for the BSP to get memory configured */ - /* FIXME: many cores spinning on node0 pci register seems to be bad. - * Why do we need to wait? These APs are just going to go sit in a hlt. - */ - //wait_till_sysinfo_in_ram(); - + /* AP is ready, configure MTRRs and go to sleep */ set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); STOP_CAR_AND_CPU(); + printk(BIOS_DEBUG, "\nAP %02x should be halted but you are reading this....\n", apicid); @@ -912,6 +907,7 @@ static void cpuSetAMDPCI(u8 node) printk(BIOS_DEBUG, " done\n"); } +#ifdef UNUSED_CODE static void cpuInitializeMCA(void) { /* Clears Machine Check Architecture (MCA) registers, which power on @@ -939,6 +935,7 @@ static void cpuInitializeMCA(void) } } } +#endif /** * finalize_node_setup() diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 23edfa08ae..a318929609 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -191,7 +191,7 @@ void wait_all_other_cores_started(u32 bsp_apicid) printk(BIOS_DEBUG, "\n"); } -static void allow_all_aps_stop(u32 bsp_apicid) +void allow_all_aps_stop(u32 bsp_apicid) { // allow aps to stop diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c index 9e4da8b90f..7d09435214 100644 --- a/src/cpu/amd/quadcore/quadcore_id.c +++ b/src/cpu/amd/quadcore/quadcore_id.c @@ -32,7 +32,7 @@ u32 read_nb_cfg_54(void) return ( ( msr.hi >> (54-32)) & 1); } -static u32 get_initial_apicid(void) +u32 get_initial_apicid(void) { return ((cpuid_ebx(1) >> 24) & 0xff); } @@ -67,10 +67,12 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54) return id; } +#ifdef UNUSED_CODE static u32 get_core_num(void) { return (cpuid_ecx(0x80000008) & 0xff); } +#endif static struct node_core_id get_node_core_id_x(void) { diff --git a/src/include/cpu/amd/multicore.h b/src/include/cpu/amd/multicore.h index 21cb23c9eb..5441c30cd3 100644 --- a/src/include/cpu/amd/multicore.h +++ b/src/include/cpu/amd/multicore.h @@ -41,6 +41,8 @@ void amd_sibling_init(struct device *cpu); #else void wait_all_other_cores_started(u32 bsp_apicid); void wait_all_aps_started(u32 bsp_apicid); +void allow_all_aps_stop(u32 bsp_apicid); #endif +u32 get_initial_apicid(void); #endif /* CPU_AMD_QUADCORE_H */ diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index a69e624520..472e55594f 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -1169,8 +1169,16 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo) #endif -#ifndef __ROMCC__ +#ifdef __PRE_RAM__ void showallroutes(int level, device_t dev); + +void setup_resource_map_offset(const u32 *register_values, u32 max, u32 + offset_pci_dev, u32 offset_io_base); + +void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 + offset_pci_dev, u32 offset_io_base); + +void setup_resource_map_x(const u32 *register_values, u32 max); #endif #endif /* AMDFAM10_H */ diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index 09bdd70437..fc89ba39c4 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -111,8 +111,6 @@ static void print_t(const char *strval) //#include "../amdmct/mct/mctardk5.c" #endif -#include "../amdmct/mct/mct_fd.c" - #endif /* DDR2 */ int mctRead_SPD(u32 smaddr, u32 reg) diff --git a/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c b/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c index 6feeacb58e..ec07fea74a 100644 --- a/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c +++ b/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c @@ -28,7 +28,7 @@ static void set_htic_bit(u8 i, u32 val, u8 bit) pci_write_config32(NODE_PCI(i, 0), HT_INIT_CONTROL, dword); } - +#ifdef UNUSED_CODE static u32 get_htic_bit(u8 i, u8 bit) { u32 dword; @@ -47,6 +47,7 @@ static void wait_till_sysinfo_in_ram(void) if(get_htic_bit(0, 9)) return; } } +#endif static void set_sysinfo_in_ram(u32 val) { diff --git a/src/northbridge/amd/amdfam10/setup_resource_map.c b/src/northbridge/amd/amdfam10/setup_resource_map.c index 31daa68b51..4a1da02f5a 100644 --- a/src/northbridge/amd/amdfam10/setup_resource_map.c +++ b/src/northbridge/amd/amdfam10/setup_resource_map.c @@ -41,9 +41,7 @@ static void setup_resource_map(const u32 *register_values, u32 max) } -static void setup_resource_map_offset(const u32 *register_values, - u32 max, u32 offset_pci_dev, - u32 offset_io_base) +void setup_resource_map_offset(const u32 *register_values, u32 max, u32 offset_pci_dev, u32 offset_io_base) { u32 i; // print_debug("setting up resource map offset...."); @@ -66,8 +64,7 @@ static void setup_resource_map_offset(const u32 *register_values, #define RES_PORT_IO_32 0x20 #define RES_MEM_IO 0x40 -static void setup_resource_map_x_offset(const u32 *register_values, u32 max, - u32 offset_pci_dev, u32 offset_io_base) +void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset_pci_dev, u32 offset_io_base) { u32 i; @@ -133,7 +130,8 @@ static void setup_resource_map_x_offset(const u32 *register_values, u32 max, print_debug("done.\n"); #endif } -static void setup_resource_map_x(const u32 *register_values, u32 max) + +void setup_resource_map_x(const u32 *register_values, u32 max) { u32 i; diff --git a/src/northbridge/amd/amdmct/mct/mct.h b/src/northbridge/amd/amdmct/mct/mct.h index 354a83c80c..5fc3d99b45 100644 --- a/src/northbridge/amd/amdmct/mct/mct.h +++ b/src/northbridge/amd/amdmct/mct/mct.h @@ -538,7 +538,6 @@ u32 SetUpperFSbase(u32 addr_hi); void K8FECCInit(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -unsigned amd_FD_support(void); void amd_MCTInit(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); void K8FCPUMemTyping(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); diff --git a/src/northbridge/amd/amdmct/mct/mct_fd.c b/src/northbridge/amd/amdmct/mct/mct_fd.c deleted file mode 100644 index 168d9957d9..0000000000 --- a/src/northbridge/amd/amdmct/mct/mct_fd.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - - - -static u8 amd_FD_support(void) -{ - return 1; -} diff --git a/src/northbridge/amd/amdmct/mct/mctpro_d.c b/src/northbridge/amd/amdmct/mct/mctpro_d.c index 961d1f5771..1724ca0640 100644 --- a/src/northbridge/amd/amdmct/mct/mctpro_d.c +++ b/src/northbridge/amd/amdmct/mct/mctpro_d.c @@ -375,7 +375,7 @@ static void beforeInterleaveChannels_D(struct DCTStatStruc *pDCTstatA, u8 *enabl *enabled = 0; } - +#ifdef UNUSED_CODE static u8 mctDoAxRdPtrInit_D(struct DCTStatStruc *pDCTstat, u8 *Rdtr) { u32 tmp; @@ -387,6 +387,7 @@ static u8 mctDoAxRdPtrInit_D(struct DCTStatStruc *pDCTstat, u8 *Rdtr) } return 0; } +#endif void mct_AdjustScrub_D(struct DCTStatStruc *pDCTstat, u16 *scrub_request) { diff --git a/src/northbridge/amd/amdmct/mct/mctsrc1p.c b/src/northbridge/amd/amdmct/mct/mctsrc1p.c index 5209e0d710..2daeedb212 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc1p.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc1p.c @@ -70,13 +70,12 @@ static u8 mct_Average_RcvrEnDly_1Pass(struct DCTStatStruc *pDCTstat, u8 Channel, return MaxValue; } - - +#ifdef UNUSED_CODE static u8 mct_AdjustFinalDQSRcvValue_1Pass(u8 val_1p, u8 val_2p) { return (val_1p & 0xff) + ((val_2p & 0xff)<<8); } - +#endif u8 mct_SaveRcvEnDly_D_1Pass(struct DCTStatStruc *pDCTstat, u8 pass) { diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index a4a87fca01..b6bd6dfa38 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -337,6 +337,7 @@ static void mctHookAfterDramInit(void) static void coreDelay (void); +#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ /* Erratum 350 */ static void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { @@ -398,6 +399,7 @@ static void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTs coreDelay(); } +#endif static void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) diff --git a/src/southbridge/amd/amd8111/amd8111.h b/src/southbridge/amd/amd8111/amd8111.h index da4fa1d840..e877f2a13b 100644 --- a/src/southbridge/amd/amd8111/amd8111.h +++ b/src/southbridge/amd/amd8111/amd8111.h @@ -5,4 +5,8 @@ void amd8111_enable(device_t dev); +#ifdef __PRE_RAM__ +void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); +#endif + #endif /* AMD8111_H */ diff --git a/src/southbridge/amd/amd8111/amd8111_early_ctrl.c b/src/southbridge/amd/amd8111/amd8111_early_ctrl.c index 0365662d58..ece99ed40a 100644 --- a/src/southbridge/amd/amd8111/amd8111_early_ctrl.c +++ b/src/southbridge/amd/amd8111/amd8111_early_ctrl.c @@ -1,3 +1,4 @@ +#include "amd8111.h" #include /* by yhlu 2005.10 */ @@ -45,7 +46,7 @@ void hard_reset(void) outb(0x0e, 0x0cf9); // make sure cf9 is enabled } -static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) +void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) { device_t dev; -- cgit v1.2.3