From 819c005cf626a808ba15b069c5e8fa0c6d3d5b90 Mon Sep 17 00:00:00 2001
From: Iru Cai <mytbk920423@gmail.com>
Date: Thu, 13 Jun 2019 21:51:53 +0800
Subject: PEI_WDT_PPI

---
 src/northbridge/intel/haswell/mrc_wdt.c | 34 ++++++++++++++-------------------
 src/northbridge/intel/haswell/mrc_wdt.h |  9 +++++++++
 2 files changed, 23 insertions(+), 20 deletions(-)
 create mode 100644 src/northbridge/intel/haswell/mrc_wdt.h

diff --git a/src/northbridge/intel/haswell/mrc_wdt.c b/src/northbridge/intel/haswell/mrc_wdt.c
index c0830f1342..25030b5b8b 100644
--- a/src/northbridge/intel/haswell/mrc_wdt.c
+++ b/src/northbridge/intel/haswell/mrc_wdt.c
@@ -1,16 +1,10 @@
 #include <southbridge/intel/lynxpoint/pch.h>
 #include <arch/io.h>
 #include <device/pci_ops.h>
+#include "mrc_wdt.h"
 
 static uint8_t *status = (uint8_t *)0xff7d7540;
 
-int fcn_fffc5b14(void);
-int fcn_fffc5b27(void);
-void fcn_fffc5b3c(void);
-int fcn_fffc5b65(void);
-void fcn_fffc5b78(void);
-int fcn_fffc5b9a(uint32_t v);
-
 static uint32_t pm54(void)
 {
 	/* 0x54 is C3_RES, but it seems not in lynxpoint */
@@ -18,38 +12,38 @@ static uint32_t pm54(void)
 	return pmbase + 0x54;
 }
 
-int fcn_fffc5b14(void)
+static int fcn_fffc5b14(void)
 {
 	uint32_t tmp = inl(pm54());
 	return ((tmp >> 14) & 1);
 }
 
-int fcn_fffc5b27(void)
+static int fcn_fffc5b27(void)
 {
 	uint32_t tmp = inl(pm54());
 	return ((tmp & 0x3f0000)?1:0);
 }
 
-void fcn_fffc5b3c(void)
+static void fcn_fffc5b3c(void)
 {
 	*status = 1;
 	u32 tmp = inl(pm54()) & 0xffbf7fff;
 	outl(tmp, pm54());
 }
 
-int fcn_fffc5b65(void)
+static int fcn_fffc5b65(void)
 {
 	u32 tmp = inl(pm54());
 	return ((tmp >> 0x17) & 1);
 }
 
-void fcn_fffc5b78(void)
+static void fcn_fffc5b78(void)
 {
 	u32 tmp = inl(pm54()) & 0xffbf3fff;
 	outl(tmp, pm54());
 }
 
-int fcn_fffc5b9a(uint32_t v)
+static int fcn_fffc5b9a(uint32_t v)
 {
 	v--;
 	if (v > 0x3fe)
@@ -68,11 +62,11 @@ int fcn_fffc5b9a(uint32_t v)
 	return 0;
 }
 
-const void* const mrc_wdt_ppi[6] = {
-	(const void*) fcn_fffc5b9a,
-	(const void*) fcn_fffc5b65,
-	(const void*) fcn_fffc5b78,
-	(const void*) fcn_fffc5b3c,
-	(const void*) fcn_fffc5b27,
-	(const void*) fcn_fffc5b14,
+const PEI_WDT_PPI mrc_wdt_ppi = {
+	fcn_fffc5b9a,
+	fcn_fffc5b65,
+	fcn_fffc5b78,
+	fcn_fffc5b3c,
+	fcn_fffc5b27,
+	fcn_fffc5b14,
 };
diff --git a/src/northbridge/intel/haswell/mrc_wdt.h b/src/northbridge/intel/haswell/mrc_wdt.h
new file mode 100644
index 0000000000..38d3e93a26
--- /dev/null
+++ b/src/northbridge/intel/haswell/mrc_wdt.h
@@ -0,0 +1,9 @@
+typedef struct
+{
+	int (*wdt_f0)(uint32_t);
+	int (*wdt_f1)(void);
+	void (*wdt_f2)(void);
+	void (*wdt_f3)(void);
+	int (*wdt_f4)(void);
+	int (*wdt_f5)(void);
+} PEI_WDT_PPI;
-- 
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