From 8971ccd576a7b0edbd02101b0c3bc3541cb6a741 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 29 Sep 2020 14:36:40 +0530 Subject: soc/intel: Move pch_misc_init() to common code List of changes: 1. Move pch_misc_init() into common block code. 2. Remove redundant LPC functions from SoC directory and refer from block/lpc directory. 3. Create macros for IO port 0x61 and 0x70 as applicable. TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact. Change-Id: Ie36ee63869c076d251ccfa5409001d18f22600d7 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/45789 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Angel Pons --- src/soc/intel/cannonlake/lpc.c | 12 ------------ .../intel/common/block/include/intelblocks/lpc_lib.h | 6 ++++++ src/soc/intel/common/block/lpc/lpc_lib.c | 18 ++++++++++++++++++ src/soc/intel/elkhartlake/espi.c | 12 ------------ src/soc/intel/elkhartlake/include/soc/espi.h | 2 -- src/soc/intel/icelake/espi.c | 12 ------------ src/soc/intel/jasperlake/espi.c | 12 ------------ src/soc/intel/skylake/lpc.c | 5 +---- src/soc/intel/tigerlake/espi.c | 12 ------------ 9 files changed, 25 insertions(+), 66 deletions(-) diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index e220678cb1..b21c117df0 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -90,18 +90,6 @@ static void soc_mirror_dmi_pcr_io_dec(void) soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); } -static void pch_misc_init(void) -{ - uint8_t reg8; - - /* Setup NMI on errors, disable SERR */ - reg8 = (inb(0x61)) & 0xf0; - outb((reg8 | (1 << 2)), 0x61); - - /* Disable NMI sources */ - outb((1 << 7), 0x70); -}; - void lpc_soc_init(struct device *dev) { const config_t *config = dev->chip_info; diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h index 52b0ff8e72..b04df76844 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h +++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h @@ -109,5 +109,11 @@ void pch_lpc_add_new_resource(struct device *dev, uint8_t offset, void pch_enable_ioapic(void); /* Retrieve and setup PCH LPC interrupt routing. */ void pch_pirq_init(void); +/* + * LPC MISC programming + * 1. Setup NMI on errors, disable SERR + * 2. Disable NMI sources + */ +void pch_misc_init(void); #endif /* _SOC_COMMON_BLOCK_LPC_LIB_H_ */ diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index d189a5e398..67dd661460 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -386,3 +386,21 @@ void pch_pirq_init(void) pci_write_config8(PCI_BDF(irq_dev), PCI_INTERRUPT_LINE, int_line); } } + +#define PPI_PORT_B 0x61 +#define SERR_DIS (1 << 2) +#define CMOS_NMI 0x70 +#define NMI_DIS (1 << 7) + +/* LPC MISC programming */ +void pch_misc_init(void) +{ + uint8_t reg8; + + /* Setup NMI on errors, disable SERR */ + reg8 = (inb(PPI_PORT_B)) & 0xf0; + outb((reg8 | SERR_DIS), PPI_PORT_B); + + /* Disable NMI sources */ + outb(NMI_DIS, CMOS_NMI); +} diff --git a/src/soc/intel/elkhartlake/espi.c b/src/soc/intel/elkhartlake/espi.c index 6e6f887842..a531fccbb0 100644 --- a/src/soc/intel/elkhartlake/espi.c +++ b/src/soc/intel/elkhartlake/espi.c @@ -64,18 +64,6 @@ static void soc_mirror_dmi_pcr_io_dec(void) soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); } -static void pch_misc_init(void) -{ - uint8_t reg8; - - /* Setup NMI on errors, disable SERR */ - reg8 = (inb(NMI_STS_CNT) & 0xf0); - outb((reg8 | (1 << 2)), NMI_STS_CNT); - - /* Disable NMI sources */ - outb((1 << 7), NMI_EN); -}; - void lpc_soc_init(struct device *dev) { /* Legacy initialization */ diff --git a/src/soc/intel/elkhartlake/include/soc/espi.h b/src/soc/intel/elkhartlake/include/soc/espi.h index 6c2615816e..65ee732e9f 100644 --- a/src/soc/intel/elkhartlake/include/soc/espi.h +++ b/src/soc/intel/elkhartlake/include/soc/espi.h @@ -22,8 +22,6 @@ #define ESPI_GEN3_DEC 0x8c /* ESPI IF Generic Decode Range 3 */ #define ESPI_GEN4_DEC 0x90 /* ESPI IF Generic Decode Range 4 */ #define LGMR 0x98 /* ESPI Generic Memory Range */ -#define NMI_EN 0x70 -#define NMI_STS_CNT 0x61 #define PCCTL 0xE0 /* PCI Clock Control */ #define CLKRUN_EN (1 << 0) diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c index 388d9fa503..7f9ff2fee2 100644 --- a/src/soc/intel/icelake/espi.c +++ b/src/soc/intel/icelake/espi.c @@ -83,18 +83,6 @@ static void soc_mirror_dmi_pcr_io_dec(void) soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); } -static void pch_misc_init(void) -{ - uint8_t reg8; - - /* Setup NMI on errors, disable SERR */ - reg8 = (inb(0x61)) & 0xf0; - outb((reg8 | (1 << 2)), 0x61); - - /* Disable NMI sources */ - outb((1 << 7), 0x70); -}; - void lpc_soc_init(struct device *dev) { /* Legacy initialization */ diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c index ef1ed953fb..0977857684 100644 --- a/src/soc/intel/jasperlake/espi.c +++ b/src/soc/intel/jasperlake/espi.c @@ -65,18 +65,6 @@ static void soc_mirror_dmi_pcr_io_dec(void) soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); } -static void pch_misc_init(void) -{ - uint8_t reg8; - - /* Setup NMI on errors, disable SERR */ - reg8 = (inb(0x61)) & 0xf0; - outb((reg8 | (1 << 2)), 0x61); - - /* Disable NMI sources */ - outb((1 << 7), 0x70); -}; - void lpc_soc_init(struct device *dev) { /* Legacy initialization */ diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index 0eaeb9ff93..f9c663980e 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -49,10 +49,6 @@ void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) } static const struct reg_script pch_misc_init_script[] = { - /* Setup NMI on errors, disable SERR */ - REG_IO_RMW8(0x61, ~0xf0, (1 << 2)), - /* Disable NMI sources */ - REG_IO_OR8(0x70, (1 << 7)), /* Enable BIOS updates outside of SMM */ REG_PCI_RMW8(0xdc, ~(1 << 5), 0), REG_SCRIPT_END @@ -64,6 +60,7 @@ void lpc_soc_init(struct device *dev) /* Legacy initialization */ isa_dma_init(); + pch_misc_init(); reg_script_run_on_dev(PCH_DEV_LPC, pch_misc_init_script); /* Enable CLKRUN_EN for power gating LPC */ diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c index 668e95f41d..acd3b12244 100644 --- a/src/soc/intel/tigerlake/espi.c +++ b/src/soc/intel/tigerlake/espi.c @@ -71,18 +71,6 @@ static void soc_mirror_dmi_pcr_io_dec(void) soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); } -static void pch_misc_init(void) -{ - uint8_t reg8; - - /* Setup NMI on errors, disable SERR */ - reg8 = (inb(0x61)) & 0xf0; - outb((reg8 | (1 << 2)), 0x61); - - /* Disable NMI sources */ - outb((1 << 7), 0x70); -}; - void lpc_soc_init(struct device *dev) { /* Legacy initialization */ -- cgit v1.2.3