From 8e7facf3437d633af747f6163cd66525ea14860e Mon Sep 17 00:00:00 2001 From: Deepti Deshatty Date: Wed, 12 May 2021 17:45:37 +0530 Subject: soc/intel/alderlake: mb/intel/sm: Add tcss code Enable FSP 'MultiPhaseSilicon' init to execute tcss configure during silicon init. Type-c aux lines DC bias changes are propagated from tigerlake platform. TEST=Verified superspeed pendrive detection on coldboot. Signed-off-by: Deepti Deshatty Change-Id: Ifce6abb0fce20e408931b904426131a42a5a4a36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54089 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../variants/baseboard/devicetree.cb | 3 +-- src/soc/intel/alderlake/chip.h | 17 +++++++---------- src/soc/intel/alderlake/fsp_params.c | 22 +++++++++++++++------- src/soc/intel/alderlake/include/soc/tcss.h | 12 ++++++++++++ 4 files changed, 35 insertions(+), 19 deletions(-) create mode 100644 src/soc/intel/alderlake/include/soc/tcss.h diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index beaf8fd1ec..55d250539c 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -14,8 +14,7 @@ chip soc/intel/alderlake # TCSS register "TcssAuxOri" = "1" - register "IomTypeCPortPadCfg[0]" = "0x09020005" - register "IomTypeCPortPadCfg[1]" = "0x09020006" + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_A5, .pad_auxn_dc = GPP_A6}" # Enable heci communication register "HeciEnabled" = "1" diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index fb9dd73730..57b78688ee 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -212,17 +212,14 @@ struct soc_intel_alderlake_config { bool CnviBtAudioOffload; /* - * IOM Port Config - * If a port orientation needs to be controlled by the SOC this setting must be - * updated to reflect the correct GPIOs being used for the SOC port flipping. - * There are 4 ports each with a pair of GPIOs for Pull Up and Pull Down - * 0,1 are pull up and pull down for port 0 - * 2,3 are pull up and pull down for port 1 - * 4,5 are pull up and pull down for port 2 - * 6,7 are pull up and pull down for port 3 - * values to be programmed correspond to the GPIO family and offsets + * These GPIOs will be programmed by the IOM to handle biasing of the + * Type-C aux (SBU) signals when certain alternate modes are used. + * `pad_auxn_dc` should be assigned to the GPIO pad providing negative + * bias (name usually contains `AUXN_DC` or `AUX_N`); similarly, + * `pad_auxp_dc` should be assigned to the GPIO providing positive bias + * (name often contains `AUXP_DC` or `_AUX_P`). */ - uint32_t IomTypeCPortPadCfg[8]; + struct typec_aux_bias_pads typec_aux_bias_pads[MAX_TYPE_C_PORTS]; /* * SOC Aux orientation override: diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 2ab182571e..8664fe6f46 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -94,6 +95,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) const struct microcode *microcode_file; size_t microcode_len; FSP_S_CONFIG *params = &supd->FspsConfig; + FSPS_ARCH_UPD *pfsps_arch_upd = &supd->FspsArchUpd; uint32_t enable_mask; struct device *dev; @@ -129,8 +131,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->D3ColdEnable = !config->TcssD3ColdDisable; params->TcssAuxOri = config->TcssAuxOri; - for (i = 0; i < 8; i++) - params->IomTypeCPortPadCfg[i] = config->IomTypeCPortPadCfg[i]; + + /* Explicitly clear this field to avoid using defaults */ + memset(params->IomTypeCPortPadCfg, 0, sizeof(params->IomTypeCPortPadCfg)); /* * Set FSPS UPD ITbtConnectTopologyTimeoutInMs with value 0. FSP will @@ -189,6 +192,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin; } + /* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */ + pfsps_arch_upd->EnableMultiPhaseSiliconInit = 1; + /* Enable xDCI controller if enabled in devicetree and allowed */ dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); if (dev) { @@ -298,11 +304,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) mainboard_silicon_init_params(params); } -int soc_fsp_multi_phase_init_is_enable(void) -{ - return 0; -} - /* * Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit * This platform supports below MultiPhaseSIInit Phase(s): @@ -315,6 +316,13 @@ void platform_fsp_multi_phase_init_cb(uint32_t phase_index) switch (phase_index) { case 1: /* TCSS specific initialization here */ + printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n", + __FILE__, __func__); + + if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS)) { + const config_t *config = config_of_soc(); + tcss_configure(config->typec_aux_bias_pads); + } break; default: break; diff --git a/src/soc/intel/alderlake/include/soc/tcss.h b/src/soc/intel/alderlake/include/soc/tcss.h new file mode 100644 index 0000000000..713528bdbb --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/tcss.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _SOC_TCSS_H_ +#define _SOC_TCSS_H_ + +/* IOM aux bias control registers in REGBAR MMIO space */ +#define IOM_AUX_BIAS_CTRL_PULLUP_OFFSET_0 0x1070 +#define IOM_AUX_BIAS_CTRL_PULLUP_OFFSET(x) (IOM_AUX_BIAS_CTRL_PULLUP_OFFSET_0 + (x) * 4) +#define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0 0x1088 +#define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET(x) (IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0 + (x) * 4) + +#endif /* _SOC_TCSS_H_ */ -- cgit v1.2.3