From 91aea428b5932c031b81a6c4921ac416f2b2c995 Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Thu, 8 Sep 2016 07:27:29 +0200 Subject: fsp_broadwell_de: Correct access to SIRQ_CNTL register The serial IRQ configuration register is only 8 bit wide so switch the PCI access from 16 bits to 8 bits. Change-Id: Ia9fbc02251e00b31440bf103e2afc2ff285b7f2e Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/16534 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/intel/fsp_broadwell_de/southcluster.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/fsp_broadwell_de/southcluster.c b/src/soc/intel/fsp_broadwell_de/southcluster.c index 7024814bb2..7ed889662e 100644 --- a/src/soc/intel/fsp_broadwell_de/southcluster.c +++ b/src/soc/intel/fsp_broadwell_de/southcluster.c @@ -215,7 +215,7 @@ static void sc_init(struct device *dev) PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); /* Program Serial IRQ register. */ - pci_write_config16(dev, 0x64, 0xd0); + pci_write_config8(dev, 0x64, 0xd0); sc_pirq_init(dev); write_pci_config_irqs(); -- cgit v1.2.3