From 967d94d62630f46a2fab808754e7a2702658f3f0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 22 Nov 2016 11:52:14 +0200 Subject: AGESA: Introduce AGESA_LEGACY and its counterpart MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We define AGESA_LEGACY as an implementation of mainboard that has its romstage main completely under mainboard/ directory. We have learnt from other platforms this approach has several downsides when it comes to making platform-wide improvements. We start by creating per-family romstage.c file, which boards will gradually take into use by removing the AGESA_LEGACY Kconfig option we here apply to all of them. Change-Id: Id01931e185a023039a60af16a678de9966db8d65 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/18619 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones Reviewed-by: Martin Roth --- src/cpu/amd/agesa/Kconfig | 7 ++ src/cpu/amd/agesa/family12/Makefile.inc | 1 + src/cpu/amd/agesa/family12/romstage.c | 88 ++++++++++++++++++++++ src/cpu/amd/agesa/family14/Makefile.inc | 1 + src/cpu/amd/agesa/family14/romstage.c | 108 +++++++++++++++++++++++++++ src/cpu/amd/agesa/family15/Makefile.inc | 1 + src/cpu/amd/agesa/family15/romstage.c | 97 ++++++++++++++++++++++++ src/cpu/amd/agesa/family15rl/Makefile.inc | 1 + src/cpu/amd/agesa/family15rl/romstage.c | 91 ++++++++++++++++++++++ src/cpu/amd/agesa/family15tn/Makefile.inc | 1 + src/cpu/amd/agesa/family15tn/romstage.c | 93 +++++++++++++++++++++++ src/cpu/amd/agesa/family16kb/Makefile.inc | 1 + src/cpu/amd/agesa/family16kb/romstage.c | 93 +++++++++++++++++++++++ src/mainboard/amd/dinar/Kconfig | 1 + src/mainboard/amd/inagua/Kconfig | 1 + src/mainboard/amd/olivehill/Kconfig | 1 + src/mainboard/amd/parmer/Kconfig | 1 + src/mainboard/amd/persimmon/Kconfig | 1 + src/mainboard/amd/south_station/Kconfig | 1 + src/mainboard/amd/thatcher/Kconfig | 1 + src/mainboard/amd/torpedo/Kconfig | 1 + src/mainboard/amd/union_station/Kconfig | 1 + src/mainboard/asrock/e350m1/Kconfig | 1 + src/mainboard/asrock/imb-a180/Kconfig | 1 + src/mainboard/asus/f2a85-m/Kconfig | 1 + src/mainboard/bap/ode_e20XX/Kconfig | 1 + src/mainboard/biostar/am1ml/Kconfig | 1 + src/mainboard/elmex/pcm205400/Kconfig | 1 + src/mainboard/gizmosphere/gizmo/Kconfig | 1 + src/mainboard/gizmosphere/gizmo2/Kconfig | 1 + src/mainboard/hp/abm/Kconfig | 1 + src/mainboard/hp/pavilion_m6_1035dx/Kconfig | 1 + src/mainboard/jetway/nf81-t56n-lf/Kconfig | 1 + src/mainboard/lenovo/g505s/Kconfig | 1 + src/mainboard/lippert/frontrunner-af/Kconfig | 1 + src/mainboard/lippert/toucan-af/Kconfig | 1 + src/mainboard/msi/ms7721/Kconfig | 1 + src/mainboard/pcengines/apu1/Kconfig | 1 + src/mainboard/supermicro/h8qgi/Kconfig | 1 + src/mainboard/supermicro/h8scm/Kconfig | 1 + src/mainboard/tyan/s8226/Kconfig | 1 + src/northbridge/amd/agesa/state_machine.h | 28 +++++++ 42 files changed, 639 insertions(+) create mode 100644 src/cpu/amd/agesa/family12/romstage.c create mode 100644 src/cpu/amd/agesa/family14/romstage.c create mode 100644 src/cpu/amd/agesa/family15/romstage.c create mode 100644 src/cpu/amd/agesa/family15rl/romstage.c create mode 100644 src/cpu/amd/agesa/family15tn/romstage.c create mode 100644 src/cpu/amd/agesa/family16kb/romstage.c create mode 100644 src/northbridge/amd/agesa/state_machine.h diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index ae5e8549df..cd14975031 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -34,6 +34,13 @@ config CPU_AMD_AGESA if CPU_AMD_AGESA +config AGESA_LEGACY + def_bool n + +config AGESA_NO_LEGACY + bool + default !AGESA_LEGACY + config XIP_ROM_SIZE hex default 0x100000 diff --git a/src/cpu/amd/agesa/family12/Makefile.inc b/src/cpu/amd/agesa/family12/Makefile.inc index 578e178505..5673c6b502 100644 --- a/src/cpu/amd/agesa/family12/Makefile.inc +++ b/src/cpu/amd/agesa/family12/Makefile.inc @@ -28,6 +28,7 @@ #***************************************************************************** romstage-y += fixme.c +romstage-$(CONFIG_AGESA_NO_LEGACY) += romstage.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/agesa/family12/romstage.c b/src/cpu/amd/agesa/family12/romstage.c new file mode 100644 index 0000000000..4fb2e685a7 --- /dev/null +++ b/src/cpu/amd/agesa/family12/romstage.c @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "sb_cimx.h" +#include "SbPlatform.h" +#include +#include "platform_cfg.h" + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + struct sysinfo *cb = NULL; + u32 val; + + post_code(0x35); + amd_initmmio(); + + if (!cpu_init_detectedx && boot_cpu()) { + post_code(0x30); + gpioEarlyInit(); + sb_poweron_init(); + + post_code(0x31); + + board_BeforeAgesa(cb); + + post_code(0x32); + post_code(0x33); + console_init(); + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + // Load MPB + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); + + post_code(0x36); + agesawrapper_amdinitreset(); + + post_code(0x37); + agesawrapper_amdinitearly(); + + post_code(0x38); + agesawrapper_amdinitpost(); + + post_code(0x39); + printk(BIOS_DEBUG, "sb_before_pci_init "); + sb_before_pci_init(); + printk(BIOS_DEBUG, "passed.\n"); + + post_code(0x40); + agesawrapper_amdinitenv(); + + post_code(0x43); + copy_and_run(); +} diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index 9b4e76b96f..71d15fbbf6 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -14,6 +14,7 @@ # romstage-y += fixme.c +romstage-$(CONFIG_AGESA_NO_LEGACY) += romstage.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/agesa/family14/romstage.c b/src/cpu/amd/agesa/family14/romstage.c new file mode 100644 index 0000000000..16f1408a4a --- /dev/null +++ b/src/cpu/amd/agesa/family14/romstage.c @@ -0,0 +1,108 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + struct sysinfo *cb = NULL; + u32 val; + + amd_initmmio(); + + if (!cpu_init_detectedx && boot_cpu()) { + post_code(0x30); + sb_Poweron_Init(); + + post_code(0x31); + + board_BeforeAgesa(cb); + + console_init(); + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + /* Load MPB */ + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); + + post_code(0x37); + agesawrapper_amdinitreset(); + + post_code(0x39); + agesawrapper_amdinitearly(); + + int s3resume = acpi_is_wakeup_s3(); + if (!s3resume) { + + printk(BIOS_INFO, "Normal boot\n"); + + post_code(0x40); + agesawrapper_amdinitpost(); + + post_code(0x41); + agesawrapper_amdinitenv(); + + post_code(0x42); + amd_initenv(); + + } else { + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + + agesawrapper_amdinitresume(); + + post_code(0x61); + + agesawrapper_amds3laterestore(); + + post_code(0x62); + + prepare_for_resume(); + } + + post_code(0x50); + copy_and_run(); +} + diff --git a/src/cpu/amd/agesa/family15/Makefile.inc b/src/cpu/amd/agesa/family15/Makefile.inc index 5742e7afca..d7cdff7a30 100644 --- a/src/cpu/amd/agesa/family15/Makefile.inc +++ b/src/cpu/amd/agesa/family15/Makefile.inc @@ -22,6 +22,7 @@ subdirs-y += ../../../x86/pae subdirs-y += ../../../x86/smm romstage-y += fixme.c +romstage-$(CONFIG_AGESA_NO_LEGACY) += romstage.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/agesa/family15/romstage.c b/src/cpu/amd/agesa/family15/romstage.c new file mode 100644 index 0000000000..fb02b4fbd0 --- /dev/null +++ b/src/cpu/amd/agesa/family15/romstage.c @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "cpu/x86/bist.h" +#include "cpu/x86/lapic.h" +#include +#include +#include +#include +#include "northbridge/amd/agesa/family10/reset_test.h" +#include +#include + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + struct sysinfo *cb = NULL; + u32 val; + + post_code(0x30); + amd_initmmio(); + post_code(0x31); + + /* Halt if there was a built in self test failure */ + post_code(0x33); + report_bist_failure(bist); + + board_BeforeAgesa(cb); + console_init(); + + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); + + post_code(0x37); + agesawrapper_amdinitreset(); + + if (!cpu_init_detectedx && boot_cpu()) { + post_code(0x38); + /* + * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, + * Disable all Pcie Bridges to work around It. + */ + sr56x0_rd890_disable_pcie_bridge(); + post_code(0x39); + nb_Poweron_Init(); + post_code(0x3A); + sb_Poweron_Init(); + } + post_code(0x3B); + agesawrapper_amdinitearly(); + + post_code(0x3C); + + nb_Ht_Init(); + post_code(0x3D); + /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */ + if (!warm_reset_detect(0)) { + printk(BIOS_INFO, "...WARM RESET...\n\n\n"); + distinguish_cpu_resets(0); + soft_reset(); + die("After soft_reset_x - shouldn't see this message!!!\n"); + } + + post_code(0x40); + agesawrapper_amdinitpost(); + + post_code(0x41); + agesawrapper_amdinitenv(); + post_code(0x42); + + post_code(0x50); + print_debug("Disabling cache as ram "); + disable_cache_as_ram(); + print_debug("done\n"); + + post_code(0x51); + copy_and_run(); +} diff --git a/src/cpu/amd/agesa/family15rl/Makefile.inc b/src/cpu/amd/agesa/family15rl/Makefile.inc index 98a7050c21..4fcaff7405 100644 --- a/src/cpu/amd/agesa/family15rl/Makefile.inc +++ b/src/cpu/amd/agesa/family15rl/Makefile.inc @@ -14,6 +14,7 @@ # romstage-y += fixme.c +romstage-$(CONFIG_AGESA_NO_LEGACY) += romstage.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/agesa/family15rl/romstage.c b/src/cpu/amd/agesa/family15rl/romstage.c new file mode 100644 index 0000000000..e0a434c8f4 --- /dev/null +++ b/src/cpu/amd/agesa/family15rl/romstage.c @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + struct sysinfo *cb = NULL; + u32 val; + + amd_initmmio(); + + if (!cpu_init_detectedx && boot_cpu()) { + post_code(0x30); + board_BeforeAgesa(cb); + + post_code(0x31); + console_init(); + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + /* Load MPB */ + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); + + post_code(0x37); + agesawrapper_amdinitreset(); + + post_code(0x39); + agesawrapper_amdinitearly(); + + int s3resume = acpi_is_wakeup_s3(); + if (!s3resume) { + post_code(0x40); + agesawrapper_amdinitpost(); + + post_code(0x41); + agesawrapper_amdinitenv(); + + disable_cache_as_ram(); + } else { + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + agesawrapper_amdinitresume(); + + amd_initcpuio(); + agesawrapper_amds3laterestore(); + + post_code(0x61); + prepare_for_resume(); + } + + post_code(0x50); + copy_and_run(); +} + diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index 98a7050c21..4fcaff7405 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -14,6 +14,7 @@ # romstage-y += fixme.c +romstage-$(CONFIG_AGESA_NO_LEGACY) += romstage.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/agesa/family15tn/romstage.c b/src/cpu/amd/agesa/family15tn/romstage.c new file mode 100644 index 0000000000..fbb70adbb3 --- /dev/null +++ b/src/cpu/amd/agesa/family15tn/romstage.c @@ -0,0 +1,93 @@ + +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + struct sysinfo *cb = NULL; + u32 val; + + amd_initmmio(); + + if (!cpu_init_detectedx && boot_cpu()) { + post_code(0x30); + + post_code(0x31); + + board_BeforeAgesa(cb); + + console_init(); + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + /* Load MPB */ + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); + + post_code(0x37); + agesawrapper_amdinitreset(); + + post_code(0x39); + agesawrapper_amdinitearly(); + + int s3resume = acpi_is_wakeup_s3(); + if (!s3resume) { + post_code(0x40); + agesawrapper_amdinitpost(); + + post_code(0x41); + agesawrapper_amdinitenv(); + + disable_cache_as_ram(); + } else { + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + agesawrapper_amdinitresume(); + + amd_initcpuio(); + agesawrapper_amds3laterestore(); + + post_code(0x61); + prepare_for_resume(); + } + + post_code(0x50); + copy_and_run(); +} diff --git a/src/cpu/amd/agesa/family16kb/Makefile.inc b/src/cpu/amd/agesa/family16kb/Makefile.inc index 9367b458a3..31c3ecfabc 100644 --- a/src/cpu/amd/agesa/family16kb/Makefile.inc +++ b/src/cpu/amd/agesa/family16kb/Makefile.inc @@ -14,6 +14,7 @@ # romstage-y += fixme.c +romstage-$(CONFIG_AGESA_NO_LEGACY) += romstage.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/agesa/family16kb/romstage.c b/src/cpu/amd/agesa/family16kb/romstage.c new file mode 100644 index 0000000000..f1deeb9092 --- /dev/null +++ b/src/cpu/amd/agesa/family16kb/romstage.c @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + struct sysinfo *cb = NULL; + u32 val; + + amd_initmmio(); + + if (!cpu_init_detectedx && boot_cpu()) { + post_code(0x30); + + board_BeforeAgesa(cb); + + post_code(0x31); + console_init(); + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + /* Load MPB */ + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); + + post_code(0x37); + agesawrapper_amdinitreset(); + + post_code(0x39); + agesawrapper_amdinitearly(); + + int s3resume = acpi_is_wakeup_s3(); + if (!s3resume) { + post_code(0x40); + agesawrapper_amdinitpost(); + + post_code(0x41); + agesawrapper_amdinitenv(); + + /* TODO: Disable cache is not ok. */ + disable_cache_as_ram(); + } else { + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + agesawrapper_amdinitresume(); + + amd_initcpuio(); + agesawrapper_amds3laterestore(); + + post_code(0x61); + prepare_for_resume(); + } + + post_code(0x50); + copy_and_run(); +} + diff --git a/src/mainboard/amd/dinar/Kconfig b/src/mainboard/amd/dinar/Kconfig index b80af9cd29..02a6987b25 100644 --- a/src/mainboard/amd/dinar/Kconfig +++ b/src/mainboard/amd/dinar/Kconfig @@ -17,6 +17,7 @@ if BOARD_AMD_DINAR config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select AGESA_LEGACY select CPU_AMD_AGESA_FAMILY15 select CPU_AMD_SOCKET_G34 select NORTHBRIDGE_AMD_AGESA_FAMILY15 diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index 89bb516b38..0023f0f3b2 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -17,6 +17,7 @@ if BOARD_AMD_INAGUA config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select AGESA_LEGACY select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig index 37fb43fdad..3433115ad2 100644 --- a/src/mainboard/amd/olivehill/Kconfig +++ b/src/mainboard/amd/olivehill/Kconfig @@ -17,6 +17,7 @@ if BOARD_AMD_OLIVEHILL config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select AGESA_LEGACY select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig index aecf065571..e02664ea27 100644 --- a/src/mainboard/amd/parmer/Kconfig +++ b/src/mainboard/amd/parmer/Kconfig @@ -17,6 +17,7 @@ if BOARD_AMD_PARMER config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select AGESA_LEGACY select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index b365eba8c3..17c0ad7898 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -17,6 +17,7 @@ if BOARD_AMD_PERSIMMON config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select AGESA_LEGACY select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig index f92d27d23c..eabfb272ab 100644 --- a/src/mainboard/amd/south_station/Kconfig +++ b/src/mainboard/amd/south_station/Kconfig @@ -17,6 +17,7 @@ if BOARD_AMD_SOUTHSTATION config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select AGESA_LEGACY select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig index 73487b0a40..a740e8eb5e 100644 --- a/src/mainboard/amd/thatcher/Kconfig +++ b/src/mainboard/amd/thatcher/Kconfig @@ -17,6 +17,7 @@ if BOARD_AMD_THATCHER config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select AGESA_LEGACY select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/amd/torpedo/Kconfig b/src/mainboard/amd/torpedo/Kconfig index 5c85c4b74e..20e811cbf6 100644 --- a/src/mainboard/amd/torpedo/Kconfig +++ b/src/mainboard/amd/torpedo/Kconfig @@ -17,6 +17,7 @@ if BOARD_AMD_TORPEDO config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select AGESA_LEGACY select CPU_AMD_AGESA_FAMILY12 select NORTHBRIDGE_AMD_AGESA_FAMILY12 select SOUTHBRIDGE_AMD_CIMX_SB900 diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig index 83660bb77c..d8b5a34d82 100644 --- a/src/mainboard/amd/union_station/Kconfig +++ b/src/mainboard/amd/union_station/Kconfig @@ -17,6 +17,7 @@ if BOARD_AMD_UNIONSTATION config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select AGESA_LEGACY select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index 1c53212124..59bed14a05 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -17,6 +17,7 @@ if BOARD_ASROCK_E350M1 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select AGESA_LEGACY select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/asrock/imb-a180/Kconfig b/src/mainboard/asrock/imb-a180/Kconfig index e118bfbe60..d0c836d9dc 100644 --- a/src/mainboard/asrock/imb-a180/Kconfig +++ b/src/mainboard/asrock/imb-a180/Kconfig @@ -17,6 +17,7 @@ if BOARD_ASROCK_IMB_A180 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select AGESA_LEGACY select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig index f3b2d7d3aa..4ca32c30c7 100644 --- a/src/mainboard/asus/f2a85-m/Kconfig +++ b/src/mainboard/asus/f2a85-m/Kconfig @@ -18,6 +18,7 @@ if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO || BOARD_ASUS_F2A85_M_LE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select AGESA_LEGACY select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig index 6631ac8d71..c89bf38522 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig +++ b/src/mainboard/bap/ode_e20XX/Kconfig @@ -18,6 +18,7 @@ if BOARD_ODE_E20XX config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select AGESA_LEGACY select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/biostar/am1ml/Kconfig b/src/mainboard/biostar/am1ml/Kconfig index 1b131dd25f..abd0f987b2 100644 --- a/src/mainboard/biostar/am1ml/Kconfig +++ b/src/mainboard/biostar/am1ml/Kconfig @@ -19,6 +19,7 @@ if BOARD_BIOSTAR_AM1ML config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_4096 + select AGESA_LEGACY select CPU_AMD_AGESA_FAMILY16_KB select FORCE_AM1_SOCKET_SUPPORT select GFXUMA diff --git a/src/mainboard/elmex/pcm205400/Kconfig b/src/mainboard/elmex/pcm205400/Kconfig index a90130148b..d94787320e 100644 --- a/src/mainboard/elmex/pcm205400/Kconfig +++ b/src/mainboard/elmex/pcm205400/Kconfig @@ -29,6 +29,7 @@ if BOARD_ELMEX_PCM205400 || BOARD_ELMEX_PCM205401 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select AGESA_LEGACY select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/gizmosphere/gizmo/Kconfig b/src/mainboard/gizmosphere/gizmo/Kconfig index 4177b1dd87..435e372a55 100644 --- a/src/mainboard/gizmosphere/gizmo/Kconfig +++ b/src/mainboard/gizmosphere/gizmo/Kconfig @@ -18,6 +18,7 @@ if BOARD_GIZMOSPHERE_GIZMO config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select AGESA_LEGACY select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig b/src/mainboard/gizmosphere/gizmo2/Kconfig index f5509f6ecc..0c0f1870e3 100644 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig +++ b/src/mainboard/gizmosphere/gizmo2/Kconfig @@ -18,6 +18,7 @@ if BOARD_GIZMOSPHERE_GIZMO2 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select AGESA_LEGACY select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/hp/abm/Kconfig b/src/mainboard/hp/abm/Kconfig index fa6bf3cdc7..324863202f 100644 --- a/src/mainboard/hp/abm/Kconfig +++ b/src/mainboard/hp/abm/Kconfig @@ -18,6 +18,7 @@ if BOARD_HP_ABM config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select AGESA_LEGACY select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig index f78cfba26a..d916c42a9d 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig +++ b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig @@ -18,6 +18,7 @@ if BOARD_HP_PAVILION_M6_1035DX config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SYSTEM_TYPE_LAPTOP + select AGESA_LEGACY select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig index 14c534b447..f0778a452b 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig @@ -18,6 +18,7 @@ if BOARD_JETWAY_NF81_T56N_LF config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select AGESA_LEGACY select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index aac3a8417d..8006beaae3 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -18,6 +18,7 @@ if BOARD_LENOVO_G505S config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SYSTEM_TYPE_LAPTOP + select AGESA_LEGACY select CPU_AMD_AGESA_FAMILY15_RL select NORTHBRIDGE_AMD_AGESA_FAMILY15_RL select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig b/src/mainboard/lippert/frontrunner-af/Kconfig index 1ec219e931..dd1e7e66cf 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig +++ b/src/mainboard/lippert/frontrunner-af/Kconfig @@ -17,6 +17,7 @@ if BOARD_LIPPERT_FRONTRUNNER_AF config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select AGESA_LEGACY select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/lippert/toucan-af/Kconfig b/src/mainboard/lippert/toucan-af/Kconfig index 590909ba50..0fffa76431 100644 --- a/src/mainboard/lippert/toucan-af/Kconfig +++ b/src/mainboard/lippert/toucan-af/Kconfig @@ -17,6 +17,7 @@ if BOARD_LIPPERT_TOUCAN_AF config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select AGESA_LEGACY select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/msi/ms7721/Kconfig b/src/mainboard/msi/ms7721/Kconfig index 7a2623b80b..1fe6dd2079 100644 --- a/src/mainboard/msi/ms7721/Kconfig +++ b/src/mainboard/msi/ms7721/Kconfig @@ -20,6 +20,7 @@ if BOARD_MSI_MS7721 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select AGESA_LEGACY select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index 5e927cc95e..347ad92f31 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -18,6 +18,7 @@ if BOARD_PCENGINES_APU1 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select AGESA_LEGACY select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig index 5492d47418..c47bd5b73c 100644 --- a/src/mainboard/supermicro/h8qgi/Kconfig +++ b/src/mainboard/supermicro/h8qgi/Kconfig @@ -17,6 +17,7 @@ if BOARD_SUPERMICRO_H8QGI config BOARD_SPECIFIC_OPTIONS def_bool y + select AGESA_LEGACY select CPU_AMD_AGESA_FAMILY15 select CPU_AMD_SOCKET_G34 select NORTHBRIDGE_AMD_AGESA_FAMILY15 diff --git a/src/mainboard/supermicro/h8scm/Kconfig b/src/mainboard/supermicro/h8scm/Kconfig index 2f672169a5..a8a8bf8ceb 100644 --- a/src/mainboard/supermicro/h8scm/Kconfig +++ b/src/mainboard/supermicro/h8scm/Kconfig @@ -17,6 +17,7 @@ if BOARD_SUPERMICRO_H8SCM config BOARD_SPECIFIC_OPTIONS def_bool y + select AGESA_LEGACY select CPU_AMD_AGESA_FAMILY15 select CPU_AMD_SOCKET_C32 select NORTHBRIDGE_AMD_AGESA_FAMILY15 diff --git a/src/mainboard/tyan/s8226/Kconfig b/src/mainboard/tyan/s8226/Kconfig index 46107580c2..71ee5b80a0 100644 --- a/src/mainboard/tyan/s8226/Kconfig +++ b/src/mainboard/tyan/s8226/Kconfig @@ -17,6 +17,7 @@ if BOARD_TYAN_S8226 config BOARD_SPECIFIC_OPTIONS def_bool y + select AGESA_LEGACY select CPU_AMD_AGESA_FAMILY15 select CPU_AMD_SOCKET_C32 select NORTHBRIDGE_AMD_AGESA_FAMILY15 diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h new file mode 100644 index 0000000000..f34fd0e522 --- /dev/null +++ b/src/northbridge/amd/agesa/state_machine.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Kyösti Mälkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _STATE_MACHINE_H_ +#define _STATE_MACHINE_H_ + +#include + +struct sysinfo +{ + int s3resume; +}; + +void board_BeforeAgesa(struct sysinfo *cb); + +#endif /* _STATE_MACHINE_H_ */ -- cgit v1.2.3