From 9733f6a33687547a9a38589468a2b7b2b927461f Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 7 Jun 2020 19:23:03 +0200 Subject: nb/intel/sandybridge: Use PCI bitwise ops Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change. Change-Id: If7f3f06cd3524790b0ec96121ed0353c89eac595 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/42150 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/northbridge/intel/sandybridge/early_init.c | 37 +++++++++----------------- src/northbridge/intel/sandybridge/gma.c | 8 ++---- src/northbridge/intel/sandybridge/romstage.c | 6 +---- 3 files changed, 15 insertions(+), 36 deletions(-) diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 59f05047a3..0c9325da41 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -64,7 +64,7 @@ static void sandybridge_setup_graphics(void) { u32 reg32; u16 reg16; - u8 reg8, gfxsize; + u8 gfxsize; reg16 = pci_read_config16(PCI_DEV(0, 2, 0), PCI_DEVICE_ID); switch (reg16) { @@ -103,10 +103,7 @@ static void sandybridge_setup_graphics(void) pci_write_config16(HOST_BRIDGE, GGC, reg16); /* Enable 256MB aperture */ - reg8 = pci_read_config8(PCI_DEV(0, 2, 0), MSAC); - reg8 &= ~0x06; - reg8 |= 0x02; - pci_write_config8(PCI_DEV(0, 2, 0), MSAC, reg8); + pci_update_config8(PCI_DEV(0, 2, 0), MSAC, ~0x06, 0x02); /* Erratum workarounds */ reg32 = MCHBAR32(SAPMCTL); @@ -134,7 +131,7 @@ static void sandybridge_setup_graphics(void) static void start_peg_link_training(void) { - u32 tmp, deven; + u32 deven; const u16 base_rev = pci_read_config16(HOST_BRIDGE, PCI_DEVICE_ID) & BASE_REV_MASK; /* @@ -150,31 +147,22 @@ static void start_peg_link_training(void) * For each PEG device, set bit 5 to use three retries for OC (Offset Calibration). * We also clear DEFER_OC (bit 16) in order to start PEG training. */ - if (deven & DEVEN_PEG10) { - tmp = pci_read_config32(PCI_DEV(0, 1, 0), AFE_PWRON) & ~(1 << 16); - pci_write_config32(PCI_DEV(0, 1, 0), AFE_PWRON, tmp | (1 << 5)); - } + if (deven & DEVEN_PEG10) + pci_update_config32(PCI_DEV(0, 1, 0), AFE_PWRON, ~(1 << 16), 1 << 5); - if (deven & DEVEN_PEG11) { - tmp = pci_read_config32(PCI_DEV(0, 1, 1), AFE_PWRON) & ~(1 << 16); - pci_write_config32(PCI_DEV(0, 1, 1), AFE_PWRON, tmp | (1 << 5)); - } + if (deven & DEVEN_PEG11) + pci_update_config32(PCI_DEV(0, 1, 1), AFE_PWRON, ~(1 << 16), 1 << 5); - if (deven & DEVEN_PEG12) { - tmp = pci_read_config32(PCI_DEV(0, 1, 2), AFE_PWRON) & ~(1 << 16); - pci_write_config32(PCI_DEV(0, 1, 2), AFE_PWRON, tmp | (1 << 5)); - } + if (deven & DEVEN_PEG12) + pci_update_config32(PCI_DEV(0, 1, 2), AFE_PWRON, ~(1 << 16), 1 << 5); - if (deven & DEVEN_PEG60) { - tmp = pci_read_config32(PCI_DEV(0, 6, 0), AFE_PWRON) & ~(1 << 16); - pci_write_config32(PCI_DEV(0, 6, 0), AFE_PWRON, tmp | (1 << 5)); - } + if (deven & DEVEN_PEG60) + pci_update_config32(PCI_DEV(0, 6, 0), AFE_PWRON, ~(1 << 16), 1 << 5); } void systemagent_early_init(void) { u32 capid0_a; - u32 deven; u8 reg8; /* Device ID Override Enable should be done very early */ @@ -201,8 +189,7 @@ void systemagent_early_init(void) systemagent_vtd_init(); /* Device Enable, don't touch PEG bits */ - deven = pci_read_config32(HOST_BRIDGE, DEVEN) | DEVEN_IGD; - pci_write_config32(HOST_BRIDGE, DEVEN, deven); + pci_or_config32(HOST_BRIDGE, DEVEN, DEVEN_IGD); sandybridge_setup_graphics(); diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index aa66f4ae84..83a0279b09 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -636,12 +636,8 @@ static const char *gma_acpi_name(const struct device *dev) /* Called by PCI set_vga_bridge function */ static void gma_func0_disable(struct device *dev) { - u16 reg16; - struct device *dev_host = pcidev_on_root(0, 0); - - reg16 = pci_read_config16(dev_host, GGC); - reg16 |= (1 << 1); /* Disable VGA decode */ - pci_write_config16(dev_host, GGC, reg16); + /* Disable VGA decode */ + pci_or_config16(pcidev_on_root(0, 0), GGC, 1 << 1); dev->enabled = 0; } diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index dce024b033..b9841b5408 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -25,12 +25,8 @@ __weak void mainboard_late_rcba_config(void) static void early_pch_reset_pmcon(void) { - u8 reg8; - /* Reset RTC power status */ - reg8 = pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3); - reg8 &= ~(1 << 2); - pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, reg8); + pci_and_config8(PCH_LPC_DEV, GEN_PMCON_3, ~(1 << 2)); } /* The romstage entry point for this platform is not mainboard-specific, hence the name */ -- cgit v1.2.3