From a0336e3e9ca914c08c98bf5ec4b11a4c0429fa75 Mon Sep 17 00:00:00 2001 From: Iru Cai Date: Sun, 16 Aug 2020 21:27:44 +0800 Subject: mb/hp: EliteBook 820 G1 --- src/mainboard/hp/820g1/Kconfig | 37 +++++++++++ src/mainboard/hp/820g1/Kconfig.name | 2 + src/mainboard/hp/820g1/Makefile.inc | 4 ++ src/mainboard/hp/820g1/acpi/ec.asl | 7 ++ src/mainboard/hp/820g1/acpi/platform.asl | 10 +++ src/mainboard/hp/820g1/acpi/superio.asl | 1 + src/mainboard/hp/820g1/acpi_tables.c | 16 +++++ src/mainboard/hp/820g1/board_info.txt | 4 ++ src/mainboard/hp/820g1/bootblock.c | 7 ++ src/mainboard/hp/820g1/devicetree.cb | 106 +++++++++++++++++++++++++++++++ src/mainboard/hp/820g1/dsdt.asl | 28 ++++++++ src/mainboard/hp/820g1/gma-mainboard.ads | 23 +++++++ src/mainboard/hp/820g1/gpio.c | 102 +++++++++++++++++++++++++++++ src/mainboard/hp/820g1/hda_verb.c | 25 ++++++++ src/mainboard/hp/820g1/mainboard.c | 24 +++++++ src/mainboard/hp/820g1/romstage.c | 58 +++++++++++++++++ 16 files changed, 454 insertions(+) create mode 100644 src/mainboard/hp/820g1/Kconfig create mode 100644 src/mainboard/hp/820g1/Kconfig.name create mode 100644 src/mainboard/hp/820g1/Makefile.inc create mode 100644 src/mainboard/hp/820g1/acpi/ec.asl create mode 100644 src/mainboard/hp/820g1/acpi/platform.asl create mode 100644 src/mainboard/hp/820g1/acpi/superio.asl create mode 100644 src/mainboard/hp/820g1/acpi_tables.c create mode 100644 src/mainboard/hp/820g1/board_info.txt create mode 100644 src/mainboard/hp/820g1/bootblock.c create mode 100644 src/mainboard/hp/820g1/devicetree.cb create mode 100644 src/mainboard/hp/820g1/dsdt.asl create mode 100644 src/mainboard/hp/820g1/gma-mainboard.ads create mode 100644 src/mainboard/hp/820g1/gpio.c create mode 100644 src/mainboard/hp/820g1/hda_verb.c create mode 100644 src/mainboard/hp/820g1/mainboard.c create mode 100644 src/mainboard/hp/820g1/romstage.c diff --git a/src/mainboard/hp/820g1/Kconfig b/src/mainboard/hp/820g1/Kconfig new file mode 100644 index 0000000000..acd0ddbe2b --- /dev/null +++ b/src/mainboard/hp/820g1/Kconfig @@ -0,0 +1,37 @@ +if BOARD_HP_820G1 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select CPU_INTEL_HASWELL + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select INTEL_LYNXPOINT_LP + select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SYSTEM_TYPE_LAPTOP + +config MAINBOARD_DIR + string + default hp/820g1 + +config MAINBOARD_PART_NUMBER + string + default "HP EliteBook 820 G1" + +config VGA_BIOS_FILE + string + default "pci8086,0a16.rom" + +config VGA_BIOS_ID + string + default "8086,0a16" + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/hp/820g1/Kconfig.name b/src/mainboard/hp/820g1/Kconfig.name new file mode 100644 index 0000000000..cd1ea41564 --- /dev/null +++ b/src/mainboard/hp/820g1/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HP_820G1 + bool "HP EliteBook 820 G1" diff --git a/src/mainboard/hp/820g1/Makefile.inc b/src/mainboard/hp/820g1/Makefile.inc new file mode 100644 index 0000000000..ec8ca220a5 --- /dev/null +++ b/src/mainboard/hp/820g1/Makefile.inc @@ -0,0 +1,4 @@ +bootblock-y += bootblock.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/hp/820g1/acpi/ec.asl b/src/mainboard/hp/820g1/acpi/ec.asl new file mode 100644 index 0000000000..f7d06f194b --- /dev/null +++ b/src/mainboard/hp/820g1/acpi/ec.asl @@ -0,0 +1,7 @@ +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 6) +/* FIXME: EC support */ +} diff --git a/src/mainboard/hp/820g1/acpi/platform.asl b/src/mainboard/hp/820g1/acpi/platform.asl new file mode 100644 index 0000000000..6e6cac04f5 --- /dev/null +++ b/src/mainboard/hp/820g1/acpi/platform.asl @@ -0,0 +1,10 @@ +Method(_WAK, 1) +{ + /* FIXME: EC support */ + Return(Package() {0, 0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/hp/820g1/acpi/superio.asl b/src/mainboard/hp/820g1/acpi/superio.asl new file mode 100644 index 0000000000..f2b35ba9c1 --- /dev/null +++ b/src/mainboard/hp/820g1/acpi/superio.asl @@ -0,0 +1 @@ +#include diff --git a/src/mainboard/hp/820g1/acpi_tables.c b/src/mainboard/hp/820g1/acpi_tables.c new file mode 100644 index 0000000000..05e01f0961 --- /dev/null +++ b/src/mainboard/hp/820g1/acpi_tables.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* FIXME: check this function. */ +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + /* The lid is open by default. FIXME: not on desktops? */ + gnvs->lids = 1; + + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; +} diff --git a/src/mainboard/hp/820g1/board_info.txt b/src/mainboard/hp/820g1/board_info.txt new file mode 100644 index 0000000000..cdbf8b838a --- /dev/null +++ b/src/mainboard/hp/820g1/board_info.txt @@ -0,0 +1,4 @@ +Category: laptop +ROM protocol: SPI +Flashrom support: n +FIXME: put ROM package, ROM socketed, Release year diff --git a/src/mainboard/hp/820g1/bootblock.c b/src/mainboard/hp/820g1/bootblock.c new file mode 100644 index 0000000000..3c1a9414b2 --- /dev/null +++ b/src/mainboard/hp/820g1/bootblock.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void mainboard_config_superio(void) +{ +} \ No newline at end of file diff --git a/src/mainboard/hp/820g1/devicetree.cb b/src/mainboard/hp/820g1/devicetree.cb new file mode 100644 index 0000000000..53cb9c4820 --- /dev/null +++ b/src/mainboard/hp/820g1/devicetree.cb @@ -0,0 +1,106 @@ +chip northbridge/intel/haswell # FIXME: check ec_present, dq_pins_interleaved, usb_xhci_on_resume, gfx + register "dq_pins_interleaved" = "false" + register "ec_present" = "true" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_ddi_e_connected" = "0" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "1" + register "gpu_panel_power_backlight_on_delay" = "1" + register "gpu_panel_power_cycle_delay" = "6" + register "gpu_panel_power_down_delay" = "500" + register "gpu_panel_power_up_delay" = "2000" + register "gpu_pch_backlight_pwm_hz" = "200" + register "usb_xhci_on_resume" = "false" + device cpu_cluster 0x0 on + chip cpu/intel/haswell + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + device domain 0x0 on + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "docking_supported" = "0" + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen4_dec" = "0x000402e9" + register "sata_ahci" = "1" + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + register "sata_port_map" = "0x1" + device pci 14.0 on # xHCI Controller + subsystemid 0x103c 0x1991 + end + device pci 16.0 off # Management Engine Interface 1 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x103c 0x1991 + end + device pci 1a.0 off # USB2 EHCI #2 + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x103c 0x1991 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x103c 0x1991 + end + device pci 1c.1 off # PCIe Port #2 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 on # PCIe Port #4 + subsystemid 0x103c 0x1991 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 on # PCIe Port #6 + subsystemid 0x103c 0x1991 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x103c 0x1991 + end + device pci 1f.0 on # LPC bridge + subsystemid 0x103c 0x1991 + end + device pci 1f.2 on # SATA Controller (AHCI) + subsystemid 0x103c 0x1991 + end + device pci 1f.3 on # SMBus + subsystemid 0x103c 0x1991 + end + device pci 1f.5 off # SATA Controller (Legacy) + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x103c 0x1991 + end + device pci 01.0 off # PCIe Bridge for discrete graphics + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x103c 0x1991 + end + device pci 03.0 on # Mini-HD audio Unsupported PCI device 8086:0a0c + subsystemid 0x103c 0x1991 + end + end +end diff --git a/src/mainboard/hp/820g1/dsdt.asl b/src/mainboard/hp/820g1/dsdt.asl new file mode 100644 index 0000000000..5ed5e78ecd --- /dev/null +++ b/src/mainboard/hp/820g1/dsdt.asl @@ -0,0 +1,28 @@ + + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI 2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include + #include + /* global NVS and variables. */ + #include + #include + + Device (\_SB.PCI0) + { + #include + /* FIXME: remove this if the board doesn't have backlight. */ + #include + #include + } +} diff --git a/src/mainboard/hp/820g1/gma-mainboard.ads b/src/mainboard/hp/820g1/gma-mainboard.ads new file mode 100644 index 0000000000..133fde5f0c --- /dev/null +++ b/src/mainboard/hp/820g1/gma-mainboard.ads @@ -0,0 +1,23 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + LVDS, + eDP); + +end GMA.Mainboard; diff --git a/src/mainboard/hp/820g1/gpio.c b/src/mainboard/hp/820g1/gpio.c new file mode 100644 index 0000000000..0fd309100f --- /dev/null +++ b/src/mainboard/hp/820g1/gpio.c @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const struct pch_lp_gpio_map mainboard_gpio_map[] = { + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, /* 0 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, /* 1 */ + LP_GPIO_OUT_LOW, /* 2: OUTPUT LOW */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, /* 3 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, /* 4 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, /* 5 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, /* 6 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, /* 7 */ + LP_GPIO_OUT_HIGH, /* 8: OUTPUT HIGH */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, /* 9 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, /* 10 */ + LP_GPIO_OUT_LOW, /* 11: OUTPUT LOW */ + LP_GPIO_NATIVE, /* 12: NATIVE */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, /* 13 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, /* 14 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, /* 15 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, .route = GPIO_ROUTE_SMI }, /* 16 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, /* 17 */ + LP_GPIO_OUT_HIGH, /* 18: OUTPUT HIGH */ + LP_GPIO_NATIVE, /* 19: NATIVE */ + LP_GPIO_NATIVE, /* 20: NATIVE */ + LP_GPIO_NATIVE, /* 21: NATIVE */ + LP_GPIO_NATIVE, /* 22: NATIVE */ + LP_GPIO_NATIVE, /* 23: NATIVE */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, .reset = GPIO_RESET_RSMRST }, /* 24 */ + LP_GPIO_OUT_HIGH, /* 25: OUTPUT HIGH */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, /* 26 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, /* 27 */ + LP_GPIO_OUT_HIGH, /* 28: OUTPUT HIGH */ + LP_GPIO_OUT_HIGH, /* 29: OUTPUT HIGH */ + LP_GPIO_NATIVE, /* 30: NATIVE */ + LP_GPIO_NATIVE, /* 31: NATIVE */ + LP_GPIO_NATIVE, /* 32: NATIVE */ + LP_GPIO_OUT_LOW, /* 33: OUTPUT LOW */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, /* 34 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, /* 35 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, .route = GPIO_ROUTE_SMI }, /* 36 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, /* 37 */ + LP_GPIO_OUT_LOW, /* 38: OUTPUT LOW */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, .route = GPIO_ROUTE_SMI }, /* 39 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, .route = GPIO_ROUTE_SMI }, /* 40 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, /* 41 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, /* 42 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, /* 43 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, /* 44 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, /* 45 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, /* 46 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, /* 47 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, /* 48 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, /* 49 */ + LP_GPIO_OUT_HIGH, /* 50: OUTPUT HIGH */ + LP_GPIO_OUT_HIGH, /* 51: OUTPUT HIGH */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, /* 52 */ + LP_GPIO_OUT_HIGH, /* 53: OUTPUT HIGH */ + LP_GPIO_OUT_HIGH, /* 54: OUTPUT HIGH */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, .owner = GPIO_OWNER_GPIO, .irqen = GPIO_IRQ_ENABLE, .pirq = GPIO_PIRQ_APIC_ROUTE }, /* 55 */ + LP_GPIO_OUT_HIGH, /* 56: OUTPUT HIGH */ + LP_GPIO_OUT_LOW, /* 57: OUTPUT LOW */ + LP_GPIO_OUT_HIGH, /* 58: OUTPUT HIGH */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, /* 59 */ + LP_GPIO_OUT_HIGH, /* 60: OUTPUT HIGH */ + LP_GPIO_OUT_LOW, /* 61: OUTPUT LOW */ + LP_GPIO_NATIVE, /* 62: NATIVE */ + LP_GPIO_NATIVE, /* 63: NATIVE */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, /* 64 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, /* 65 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, /* 66 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, /* 67 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, /* 68 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, /* 69 */ + LP_GPIO_OUT_HIGH, /* 70: OUTPUT HIGH */ + LP_GPIO_OUT_HIGH, /* 71: OUTPUT HIGH */ + LP_GPIO_NATIVE, /* 72: NATIVE */ + LP_GPIO_NATIVE, /* 73: NATIVE */ + LP_GPIO_NATIVE, /* 74: NATIVE */ + LP_GPIO_NATIVE, /* 75: NATIVE */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, /* 76 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, /* 77 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, /* 78 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, /* 79 */ + LP_GPIO_OUT_LOW, /* 80: OUTPUT LOW */ + LP_GPIO_NATIVE, /* 81: NATIVE */ + LP_GPIO_OUT_HIGH, /* 82: OUTPUT HIGH */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, /* 83 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, /* 84 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, /* 85 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, /* 86 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, /* 87 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, /* 88 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, /* 89 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, /* 90 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, /* 91 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, /* 92 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, /* 93 */ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, /* 94 */ + LP_GPIO_END +}; \ No newline at end of file diff --git a/src/mainboard/hp/820g1/hda_verb.c b/src/mainboard/hp/820g1/hda_verb.c new file mode 100644 index 0000000000..439e0e6a55 --- /dev/null +++ b/src/mainboard/hp/820g1/hda_verb.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + 0x111d76e0, /* Codec Vendor / Device ID: IDT */ + 0x103c1991, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x103c1991), + AZALIA_PIN_CFG(0, 0x0a, 0x21011030), + AZALIA_PIN_CFG(0, 0x0b, 0x0421101f), + AZALIA_PIN_CFG(0, 0x0c, 0x04a11020), + AZALIA_PIN_CFG(0, 0x0d, 0x90170110), + AZALIA_PIN_CFG(0, 0x0e, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x0f, 0x2181102e), + AZALIA_PIN_CFG(0, 0x10, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x11, 0xd5a30140), + AZALIA_PIN_CFG(0, 0x1f, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x20, 0x40f000f0), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/820g1/mainboard.c b/src/mainboard/hp/820g1/mainboard.c new file mode 100644 index 0000000000..b681aeb696 --- /dev/null +++ b/src/mainboard/hp/820g1/mainboard.c @@ -0,0 +1,24 @@ +#include +#include +#include +#include +#include + +static void mainboard_init(struct device *dev) +{ + pc_keyboard_init(NO_AUX_DEVICE); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; + + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/hp/820g1/romstage.c b/src/mainboard/hp/820g1/romstage.c new file mode 100644 index 0000000000..09e176c816 --- /dev/null +++ b/src/mainboard/hp/820g1/romstage.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void mainboard_config_rcba(void) +{ + RCBA16(D31IR) = DIR_ROUTE(PIRQF, PIRQD, PIRQC, PIRQA); + RCBA16(D29IR) = DIR_ROUTE(PIRQB, PIRQD, PIRQA, PIRQC); + RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); + RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD); + RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD); + RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQB, PIRQC, PIRQD); + RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); + RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); +} + +/* FIXME: called after romstage_common, remove it if not used */ +void mb_late_romstage_setup(void) +{ +} + +void mb_get_spd_map(uint8_t spd_map[4]) +{ + /* FIXME: check this */ + /* note that SPD addresses are left-shifted by 1. */ + spd_map[0] = 0xa0; + spd_map[1] = 0xa2; + spd_map[2] = 0xa4; + spd_map[3] = 0xa6; +} + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0080, 1, 1, USB_PORT_MINI_PCIE }, + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + }; + struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, USB_OC_PIN_SKIP }, + { 1, USB_OC_PIN_SKIP }, + }; + memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); + memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); +} \ No newline at end of file -- cgit v1.2.3