From a7bf0df24f7aca50309232d185366eb94355f34f Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Thu, 13 May 2021 11:25:59 +0530 Subject: mb/google/brya: Enable HECI1 communication The patch enables HECI1 interface to allow OS applications to communicate with CSE. TEST=Verify PCI device 0:16.0 exposed in the lspci output Signed-off-by: Sridhar Siricilla Change-Id: I73acdd99788f9b60b7bcea372145e9694a124174 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54210 Reviewed-by: Rizwan Qureshi Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/mainboard/google/brya/variants/baseboard/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index 16678cb816..5f736719ff 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -25,6 +25,9 @@ chip soc/intel/alderlake .tdp_pl2_override = 55, }" + # Enable heci communication + register "HeciEnabled" = "1" + # This disabled autonomous GPIO power management, otherwise # old cr50 FW only supports short pulses; need to clarify # the minimum PCH IRQ pulse width with Intel, b/180111628 -- cgit v1.2.3