From ab3947a021c8fc5cde16875e79481555fd406a82 Mon Sep 17 00:00:00 2001 From: Chris Wang Date: Thu, 28 May 2020 21:16:34 +0800 Subject: soc/amd/picasso: Add UPD xhci0_force_gen1 Adding xhci0_force_gen1 UPD to force USB3 port to gen1. BUG=b:156314787 BRANCH=trembyle-bringup TEST=Build. Cq-Depend: chrome-internal:3013435 Change-Id: Iff3746e248625c253776c3bc3946d123b0635ffe Signed-off-by: Chris Wang Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2217662 Reviewed-by: Raul E Rangel Reviewed-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/42216 Reviewed-by: Marshall Dawson Reviewed-by: Eric Peers Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/chip.h | 2 ++ src/soc/amd/picasso/fsp_params.c | 7 +++++++ 2 files changed, 9 insertions(+) diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index e52751a2eb..f5fbe0fc2e 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -103,6 +103,8 @@ struct soc_amd_picasso_config { SD_EMMC_EMMC_HS400, SD_EMMC_EMMC_HS300, } sd_emmc_config; + + uint8_t xhci0_force_gen1; }; typedef struct soc_amd_picasso_config config_t; diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index 67fe7d8e97..9decbbf57b 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -95,6 +95,12 @@ static void fsp_fill_pcie_ddi_descriptors(FSP_S_CONFIG *scfg) fill_ddi_descriptors(scfg, fsp_ddi, num_ddi); } +static void fsp_usb_oem_customization(FSP_S_CONFIG *scfg, + const struct soc_amd_picasso_config *cfg) +{ + scfg->xhci0_force_gen1 = cfg->xhci0_force_gen1; +} + void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { const struct soc_amd_picasso_config *cfg; @@ -103,4 +109,5 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) cfg = config_of_soc(); fsps_update_emmc_config(scfg, cfg); fsp_fill_pcie_ddi_descriptors(scfg); + fsp_usb_oem_customization(scfg, cfg); } -- cgit v1.2.3